| 1 | ; VMM - World Switchers, 32Bit to AMD64.
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| 2 | ;
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| 3 |
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| 4 | ;
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| 5 | ; Copyright (C) 2006-2007 Sun Microsystems, Inc.
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| 6 | ;
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| 7 | ; This file is part of VirtualBox Open Source Edition (OSE), as
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| 8 | ; available from http://www.virtualbox.org. This file is free software;
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| 9 | ; you can redistribute it and/or modify it under the terms of the GNU
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| 10 | ; General Public License (GPL) as published by the Free Software
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| 11 | ; Foundation, in version 2 as it comes in the "COPYING" file of the
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| 12 | ; VirtualBox OSE distribution. VirtualBox OSE is distributed in the
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| 13 | ; hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
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| 14 | ;
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| 15 | ; Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
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| 16 | ; Clara, CA 95054 USA or visit http://www.sun.com if you need
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| 17 | ; additional information or have any questions.
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| 18 | ;
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| 19 |
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| 20 | ;%define DEBUG_STUFF 1
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| 21 | ;%define STRICT_IF 1
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| 22 |
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| 23 | ;*******************************************************************************
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| 24 | ;* Defined Constants And Macros *
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| 25 | ;*******************************************************************************
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| 26 | ;; Prefix all names.
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| 27 | %define NAME_OVERLOAD(name) vmmR3Switcher32BitToAMD64_ %+ name
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| 28 |
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| 29 |
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| 30 | ;*******************************************************************************
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| 31 | ;* Header Files *
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| 32 | ;*******************************************************************************
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| 33 | %include "VBox/asmdefs.mac"
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| 34 | %include "VBox/x86.mac"
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| 35 | %include "VBox/cpum.mac"
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| 36 | %include "VBox/stam.mac"
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| 37 | %include "VBox/vm.mac"
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| 38 | %include "CPUMInternal.mac"
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| 39 | %include "VMMSwitcher/VMMSwitcher.mac"
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| 40 |
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| 41 |
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| 42 | ;
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| 43 | ; Start the fixup records
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| 44 | ; We collect the fixups in the .data section as we go along
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| 45 | ; It is therefore VITAL that no-one is using the .data section
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| 46 | ; for anything else between 'Start' and 'End'.
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| 47 | ;
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| 48 | BEGINDATA
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| 49 | GLOBALNAME Fixups
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| 50 |
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| 51 |
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| 52 |
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| 53 | BEGINCODE
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| 54 | GLOBALNAME Start
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| 55 |
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| 56 | BITS 32
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| 57 |
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| 58 | ;;
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| 59 | ; The C interface.
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| 60 | ;
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| 61 | BEGINPROC vmmR0HostToGuest
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| 62 | %ifdef DEBUG_STUFF
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| 63 | COM32_S_NEWLINE
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| 64 | COM32_S_CHAR '^'
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| 65 | %endif
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| 66 |
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| 67 | %ifdef VBOX_WITH_STATISTICS
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| 68 | ;
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| 69 | ; Switcher stats.
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| 70 | ;
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| 71 | FIXUP FIX_HC_VM_OFF, 1, VM.StatSwitcherToGC
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| 72 | mov edx, 0ffffffffh
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| 73 | STAM_PROFILE_ADV_START edx
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| 74 | %endif
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| 75 |
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| 76 | ;
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| 77 | ; Call worker.
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| 78 | ;
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| 79 | FIXUP FIX_HC_CPUM_OFF, 1, 0
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| 80 | mov edx, 0ffffffffh
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| 81 | push cs ; allow for far return and restore cs correctly.
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| 82 | call NAME(vmmR0HostToGuestAsm)
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| 83 |
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| 84 | %ifdef VBOX_WITH_STATISTICS
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| 85 | ;
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| 86 | ; Switcher stats.
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| 87 | ;
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| 88 | FIXUP FIX_HC_VM_OFF, 1, VM.StatSwitcherToHC
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| 89 | mov edx, 0ffffffffh
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| 90 | STAM_PROFILE_ADV_STOP edx
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| 91 | %endif
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| 92 |
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| 93 | ret
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| 94 |
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| 95 | ENDPROC vmmR0HostToGuest
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| 96 |
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| 97 | ; *****************************************************************************
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| 98 | ; vmmR0HostToGuestAsm
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| 99 | ;
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| 100 | ; Phase one of the switch from host to guest context (host MMU context)
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| 101 | ;
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| 102 | ; INPUT:
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| 103 | ; - edx virtual address of CPUM structure (valid in host context)
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| 104 | ;
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| 105 | ; USES/DESTROYS:
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| 106 | ; - eax, ecx, edx, esi
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| 107 | ;
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| 108 | ; ASSUMPTION:
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| 109 | ; - current CS and DS selectors are wide open
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| 110 | ;
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| 111 | ; *****************************************************************************
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| 112 | ALIGNCODE(16)
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| 113 | BEGINPROC vmmR0HostToGuestAsm
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| 114 | ;;
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| 115 | ;; Save CPU host context
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| 116 | ;; Skip eax, edx and ecx as these are not preserved over calls.
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| 117 | ;;
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| 118 | CPUMCPU_FROM_CPUM(edx)
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| 119 | ; general registers.
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| 120 | mov [edx + CPUMCPU.Host.ebx], ebx
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| 121 | mov [edx + CPUMCPU.Host.edi], edi
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| 122 | mov [edx + CPUMCPU.Host.esi], esi
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| 123 | mov [edx + CPUMCPU.Host.esp], esp
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| 124 | mov [edx + CPUMCPU.Host.ebp], ebp
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| 125 | ; selectors.
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| 126 | mov [edx + CPUMCPU.Host.ds], ds
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| 127 | mov [edx + CPUMCPU.Host.es], es
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| 128 | mov [edx + CPUMCPU.Host.fs], fs
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| 129 | mov [edx + CPUMCPU.Host.gs], gs
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| 130 | mov [edx + CPUMCPU.Host.ss], ss
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| 131 | ; special registers.
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| 132 | sldt [edx + CPUMCPU.Host.ldtr]
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| 133 | sidt [edx + CPUMCPU.Host.idtr]
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| 134 | sgdt [edx + CPUMCPU.Host.gdtr]
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| 135 | str [edx + CPUMCPU.Host.tr]
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| 136 | ; flags
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| 137 | pushfd
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| 138 | pop dword [edx + CPUMCPU.Host.eflags]
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| 139 |
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| 140 | FIXUP FIX_NO_SYSENTER_JMP, 0, htg_no_sysenter - NAME(Start) ; this will insert a jmp htg_no_sysenter if host doesn't use sysenter.
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| 141 | ; save MSR_IA32_SYSENTER_CS register.
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| 142 | mov ecx, MSR_IA32_SYSENTER_CS
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| 143 | mov ebx, edx ; save edx
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| 144 | rdmsr ; edx:eax <- MSR[ecx]
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| 145 | mov [ebx + CPUMCPU.Host.SysEnter.cs], eax
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| 146 | mov [ebx + CPUMCPU.Host.SysEnter.cs + 4], edx
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| 147 | xor eax, eax ; load 0:0 to cause #GP upon sysenter
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| 148 | xor edx, edx
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| 149 | wrmsr
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| 150 | xchg ebx, edx ; restore edx
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| 151 | jmp short htg_no_sysenter
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| 152 |
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| 153 | ALIGNCODE(16)
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| 154 | htg_no_sysenter:
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| 155 |
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| 156 | ;; handle use flags.
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| 157 | mov esi, [edx + CPUMCPU.fUseFlags] ; esi == use flags.
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| 158 | and esi, ~CPUM_USED_FPU ; Clear CPUM_USED_* flags. ;;@todo FPU check can be optimized to use cr0 flags!
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| 159 | mov [edx + CPUMCPU.fUseFlags], esi
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| 160 |
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| 161 | ; debug registers.
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| 162 | test esi, CPUM_USE_DEBUG_REGS | CPUM_USE_DEBUG_REGS_HOST
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| 163 | jz htg_debug_regs_no
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| 164 | jmp htg_debug_regs_save_dr7and6
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| 165 | htg_debug_regs_no:
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| 166 |
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| 167 | ; control registers.
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| 168 | mov eax, cr0
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| 169 | mov [edx + CPUMCPU.Host.cr0], eax
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| 170 | ;Skip cr2; assume host os don't stuff things in cr2. (safe)
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| 171 | mov eax, cr3
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| 172 | mov [edx + CPUMCPU.Host.cr3], eax
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| 173 | mov eax, cr4
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| 174 | mov [edx + CPUMCPU.Host.cr4], eax
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| 175 |
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| 176 | ;;
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| 177 | ;; Load Intermediate memory context.
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| 178 | ;;
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| 179 | FIXUP FIX_INTER_32BIT_CR3, 1
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| 180 | mov eax, 0ffffffffh
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| 181 | mov cr3, eax
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| 182 | DEBUG_CHAR('?')
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| 183 |
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| 184 | ;;
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| 185 | ;; Jump to identity mapped location
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| 186 | ;;
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| 187 | FIXUP FIX_GC_2_ID_NEAR_REL, 1, NAME(IDEnterTarget) - NAME(Start)
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| 188 | jmp near NAME(IDEnterTarget)
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| 189 |
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| 190 |
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| 191 | ; We're now on identity mapped pages!
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| 192 | ALIGNCODE(16)
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| 193 | GLOBALNAME IDEnterTarget
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| 194 | DEBUG_CHAR('2')
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| 195 |
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| 196 | ; 1. Disable paging.
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| 197 | mov ebx, cr0
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| 198 | and ebx, ~X86_CR0_PG
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| 199 | mov cr0, ebx
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| 200 | DEBUG_CHAR('2')
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| 201 |
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| 202 | ; 2. Enable PAE.
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| 203 | mov ecx, cr4
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| 204 | or ecx, X86_CR4_PAE
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| 205 | mov cr4, ecx
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| 206 |
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| 207 | ; 3. Load long mode intermediate CR3.
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| 208 | FIXUP FIX_INTER_AMD64_CR3, 1
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| 209 | mov ecx, 0ffffffffh
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| 210 | mov cr3, ecx
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| 211 | DEBUG_CHAR('3')
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| 212 |
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| 213 | ; 4. Enable long mode.
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| 214 | mov ebp, edx
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| 215 | mov ecx, MSR_K6_EFER
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| 216 | rdmsr
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| 217 | or eax, MSR_K6_EFER_LME
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| 218 | wrmsr
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| 219 | mov edx, ebp
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| 220 | DEBUG_CHAR('4')
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| 221 |
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| 222 | ; 5. Enable paging.
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| 223 | or ebx, X86_CR0_PG
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| 224 | mov cr0, ebx
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| 225 | DEBUG_CHAR('5')
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| 226 |
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| 227 | ; Jump from compatability mode to 64-bit mode.
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| 228 | FIXUP FIX_ID_FAR32_TO_64BIT_MODE, 1, NAME(IDEnter64Mode) - NAME(Start)
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| 229 | jmp 0ffffh:0fffffffeh
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| 230 |
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| 231 | ;
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| 232 | ; We're in 64-bit mode (ds, ss, es, fs, gs are all bogus).
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| 233 | BITS 64
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| 234 | ALIGNCODE(16)
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| 235 | NAME(IDEnter64Mode):
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| 236 | DEBUG_CHAR('6')
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| 237 | jmp [NAME(pICEnterTarget) wrt rip]
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| 238 |
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| 239 | ; 64-bit jump target
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| 240 | NAME(pICEnterTarget):
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| 241 | FIXUP FIX_HC_64BIT, 0, NAME(ICEnterTarget) - NAME(Start)
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| 242 | dq 0ffffffffffffffffh
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| 243 |
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| 244 | ; 64-bit pCpum address.
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| 245 | NAME(pCpumIC):
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| 246 | FIXUP FIX_HC_64BIT_CPUM, 0
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| 247 | dq 0ffffffffffffffffh
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| 248 |
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| 249 | ;
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| 250 | ; When we arrive here we're at the 64 bit mode of intermediate context
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| 251 | ;
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| 252 | ALIGNCODE(16)
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| 253 | GLOBALNAME ICEnterTarget
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| 254 | ; at this moment we're in 64-bit mode. let's write something to CPUM
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| 255 | ; Load CPUM pointer into rdx
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| 256 | mov rdx, [NAME(pCpumIC) wrt rip]
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| 257 | ; Load the CPUMCPU offset.
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| 258 | mov r8, [rdx + CPUM.ulOffCPUMCPU]
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| 259 |
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| 260 | mov rsi, 012345678h
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| 261 | mov [rdx + r8 + CPUMCPU.uPadding], rsi
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| 262 |
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| 263 | ; now let's switch back
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| 264 | mov rax, 0666h
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| 265 | jmp NAME(VMMGCGuestToHostAsm) ; rax = returncode.
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| 266 |
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| 267 | BITS 32
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| 268 | ;;
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| 269 | ; Detour for saving the host DR7 and DR6.
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| 270 | ; esi and edx must be preserved.
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| 271 | htg_debug_regs_save_dr7and6:
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| 272 | DEBUG_S_CHAR('s');
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| 273 | mov eax, dr7 ; not sure, but if I read the docs right this will trap if GD is set. FIXME!!!
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| 274 | mov [edx + CPUMCPU.Host.dr7], eax
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| 275 | xor eax, eax ; clear everything. (bit 12? is read as 1...)
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| 276 | mov dr7, eax
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| 277 | mov eax, dr6 ; just in case we save the state register too.
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| 278 | mov [edx + CPUMCPU.Host.dr6], eax
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| 279 | jmp htg_debug_regs_no
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| 280 |
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| 281 |
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| 282 | BITS 64
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| 283 | ENDPROC vmmR0HostToGuestAsm
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| 284 |
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| 285 |
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| 286 | ;;
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| 287 | ; Trampoline for doing a call when starting the hyper visor execution.
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| 288 | ;
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| 289 | ; Push any arguments to the routine.
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| 290 | ; Push the argument frame size (cArg * 4).
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| 291 | ; Push the call target (_cdecl convention).
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| 292 | ; Push the address of this routine.
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| 293 | ;
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| 294 | ;
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| 295 | ALIGNCODE(16)
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| 296 | BEGINPROC vmmGCCallTrampoline
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| 297 | %ifdef DEBUG_STUFF
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| 298 | COM32_S_CHAR 'c'
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| 299 | COM32_S_CHAR 't'
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| 300 | COM32_S_CHAR '!'
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| 301 | %endif
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| 302 | int3
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| 303 | ENDPROC vmmGCCallTrampoline
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| 304 |
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| 305 |
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| 306 | BITS 64
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| 307 | ;;
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| 308 | ; The C interface.
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| 309 | ;
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| 310 | ALIGNCODE(16)
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| 311 | BEGINPROC vmmGCGuestToHost
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| 312 | %ifdef DEBUG_STUFF
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| 313 | push esi
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| 314 | COM_NEWLINE
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| 315 | DEBUG_CHAR('b')
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| 316 | DEBUG_CHAR('a')
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| 317 | DEBUG_CHAR('c')
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| 318 | DEBUG_CHAR('k')
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| 319 | DEBUG_CHAR('!')
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| 320 | COM_NEWLINE
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| 321 | pop esi
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| 322 | %endif
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| 323 | int3
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| 324 | ENDPROC vmmGCGuestToHost
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| 325 |
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| 326 | ;;
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| 327 | ; VMMGCGuestToHostAsm
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| 328 | ;
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| 329 | ; This is an alternative entry point which we'll be using
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| 330 | ; when the we have saved the guest state already or we haven't
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| 331 | ; been messing with the guest at all.
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| 332 | ;
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| 333 | ; @param eax Return code.
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| 334 | ; @uses eax, edx, ecx (or it may use them in the future)
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| 335 | ;
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| 336 | ALIGNCODE(16)
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| 337 | BEGINPROC VMMGCGuestToHostAsm
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| 338 | CPUMCPU_FROM_CPUM(rdx)
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| 339 | FIXUP FIX_INTER_AMD64_CR3, 1
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| 340 | mov rax, 0ffffffffh
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| 341 | mov cr3, rax
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| 342 | ;; We're now in intermediate memory context!
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| 343 |
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| 344 | ;;
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| 345 | ;; Jump to identity mapped location
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| 346 | ;;
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| 347 | FIXUP FIX_GC_2_ID_NEAR_REL, 1, NAME(IDExitTarget) - NAME(Start)
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| 348 | jmp near NAME(IDExitTarget)
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| 349 |
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| 350 | ; We're now on identity mapped pages!
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| 351 | ALIGNCODE(16)
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| 352 | GLOBALNAME IDExitTarget
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| 353 | BITS 32
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| 354 | DEBUG_CHAR('1')
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| 355 |
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| 356 | ; 1. Deactivate long mode by turning off paging.
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| 357 | mov ebx, cr0
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| 358 | and ebx, ~X86_CR0_PG
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| 359 | mov cr0, ebx
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| 360 | DEBUG_CHAR('2')
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| 361 |
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| 362 | ; 2. Load 32-bit intermediate page table.
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| 363 | FIXUP FIX_INTER_32BIT_CR3, 1
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| 364 | mov edx, 0ffffffffh
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| 365 | mov cr3, edx
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| 366 | DEBUG_CHAR('3')
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| 367 |
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| 368 | ; 3. Disable long mode.
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| 369 | mov ecx, MSR_K6_EFER
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| 370 | rdmsr
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| 371 | DEBUG_CHAR('5')
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| 372 | and eax, ~(MSR_K6_EFER_LME)
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| 373 | wrmsr
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| 374 | DEBUG_CHAR('6')
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| 375 |
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| 376 | ; 3b. Disable PAE.
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| 377 | mov eax, cr4
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| 378 | and eax, ~X86_CR4_PAE
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| 379 | mov cr4, eax
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| 380 | DEBUG_CHAR('7')
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| 381 |
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| 382 | ; 4. Enable paging.
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| 383 | or ebx, X86_CR0_PG
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| 384 | mov cr0, ebx
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| 385 | jmp short just_a_jump
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| 386 | just_a_jump:
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| 387 | DEBUG_CHAR('8')
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| 388 |
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| 389 | ;;
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| 390 | ;; 5. Jump to guest code mapping of the code and load the Hypervisor CS.
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| 391 | ;;
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| 392 | FIXUP FIX_ID_2_GC_NEAR_REL, 1, NAME(ICExitTarget) - NAME(Start)
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| 393 | jmp near NAME(ICExitTarget)
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| 394 |
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| 395 | ;;
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| 396 | ;; When we arrive at this label we're at the
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| 397 | ;; intermediate mapping of the switching code.
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| 398 | ;;
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| 399 | BITS 32
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| 400 | ALIGNCODE(16)
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| 401 | GLOBALNAME ICExitTarget
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| 402 | DEBUG_CHAR('8')
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| 403 | FIXUP FIX_HC_CPUM_OFF, 1, 0
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| 404 | mov edx, 0ffffffffh
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| 405 | CPUMCPU_FROM_CPUM(edx)
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| 406 | mov esi, [edx + CPUMCPU.Host.cr3]
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| 407 | mov cr3, esi
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| 408 |
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| 409 | ;; now we're in host memory context, let's restore regs
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| 410 |
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| 411 | ; activate host gdt and idt
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| 412 | lgdt [edx + CPUMCPU.Host.gdtr]
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| 413 | DEBUG_CHAR('0')
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| 414 | lidt [edx + CPUMCPU.Host.idtr]
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| 415 | DEBUG_CHAR('1')
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| 416 |
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| 417 | ; Restore TSS selector; must mark it as not busy before using ltr (!)
|
|---|
| 418 | ; ASSUME that this is supposed to be 'BUSY'. (saves 20-30 ticks on the T42p)
|
|---|
| 419 | movzx eax, word [edx + CPUMCPU.Host.tr] ; eax <- TR
|
|---|
| 420 | and al, 0F8h ; mask away TI and RPL bits, get descriptor offset.
|
|---|
| 421 | add eax, [edx + CPUMCPU.Host.gdtr + 2] ; eax <- GDTR.address + descriptor offset.
|
|---|
| 422 | and dword [eax + 4], ~0200h ; clear busy flag (2nd type2 bit)
|
|---|
| 423 | ltr word [edx + CPUMCPU.Host.tr]
|
|---|
| 424 |
|
|---|
| 425 | ; activate ldt
|
|---|
| 426 | DEBUG_CHAR('2')
|
|---|
| 427 | lldt [edx + CPUMCPU.Host.ldtr]
|
|---|
| 428 | ; Restore segment registers
|
|---|
| 429 | mov eax, [edx + CPUMCPU.Host.ds]
|
|---|
| 430 | mov ds, eax
|
|---|
| 431 | mov eax, [edx + CPUMCPU.Host.es]
|
|---|
| 432 | mov es, eax
|
|---|
| 433 | mov eax, [edx + CPUMCPU.Host.fs]
|
|---|
| 434 | mov fs, eax
|
|---|
| 435 | mov eax, [edx + CPUMCPU.Host.gs]
|
|---|
| 436 | mov gs, eax
|
|---|
| 437 | ; restore stack
|
|---|
| 438 | lss esp, [edx + CPUMCPU.Host.esp]
|
|---|
| 439 |
|
|---|
| 440 | FIXUP FIX_NO_SYSENTER_JMP, 0, gth_sysenter_no - NAME(Start) ; this will insert a jmp gth_sysenter_no if host doesn't use sysenter.
|
|---|
| 441 |
|
|---|
| 442 | ; restore MSR_IA32_SYSENTER_CS register.
|
|---|
| 443 | mov ecx, MSR_IA32_SYSENTER_CS
|
|---|
| 444 | mov eax, [edx + CPUMCPU.Host.SysEnter.cs]
|
|---|
| 445 | mov ebx, [edx + CPUMCPU.Host.SysEnter.cs + 4]
|
|---|
| 446 | xchg edx, ebx ; save/load edx
|
|---|
| 447 | wrmsr ; MSR[ecx] <- edx:eax
|
|---|
| 448 | xchg edx, ebx ; restore edx
|
|---|
| 449 | jmp short gth_sysenter_no
|
|---|
| 450 |
|
|---|
| 451 | ALIGNCODE(16)
|
|---|
| 452 | gth_sysenter_no:
|
|---|
| 453 |
|
|---|
| 454 | ;; @todo AMD syscall
|
|---|
| 455 |
|
|---|
| 456 | ; Restore FPU if guest has used it.
|
|---|
| 457 | ; Using fxrstor should ensure that we're not causing unwanted exception on the host.
|
|---|
| 458 | mov esi, [edx + CPUMCPU.fUseFlags] ; esi == use flags.
|
|---|
| 459 | test esi, CPUM_USED_FPU
|
|---|
| 460 | jz near gth_fpu_no
|
|---|
| 461 | mov ecx, cr0
|
|---|
| 462 | and ecx, ~(X86_CR0_TS | X86_CR0_EM)
|
|---|
| 463 | mov cr0, ecx
|
|---|
| 464 |
|
|---|
| 465 | FIXUP FIX_NO_FXSAVE_JMP, 0, gth_no_fxsave - NAME(Start) ; this will insert a jmp gth_no_fxsave if fxsave isn't supported.
|
|---|
| 466 | fxsave [edx + CPUMCPU.Guest.fpu]
|
|---|
| 467 | fxrstor [edx + CPUMCPU.Host.fpu]
|
|---|
| 468 | jmp near gth_fpu_no
|
|---|
| 469 |
|
|---|
| 470 | gth_no_fxsave:
|
|---|
| 471 | fnsave [edx + CPUMCPU.Guest.fpu]
|
|---|
| 472 | mov eax, [edx + CPUMCPU.Host.fpu] ; control word
|
|---|
| 473 | not eax ; 1 means exception ignored (6 LS bits)
|
|---|
| 474 | and eax, byte 03Fh ; 6 LS bits only
|
|---|
| 475 | test eax, [edx + CPUMCPU.Host.fpu + 4] ; status word
|
|---|
| 476 | jz gth_no_exceptions_pending
|
|---|
| 477 |
|
|---|
| 478 | ; technically incorrect, but we certainly don't want any exceptions now!!
|
|---|
| 479 | and dword [edx + CPUMCPU.Host.fpu + 4], ~03Fh
|
|---|
| 480 |
|
|---|
| 481 | gth_no_exceptions_pending:
|
|---|
| 482 | frstor [edx + CPUMCPU.Host.fpu]
|
|---|
| 483 | jmp short gth_fpu_no
|
|---|
| 484 |
|
|---|
| 485 | ALIGNCODE(16)
|
|---|
| 486 | gth_fpu_no:
|
|---|
| 487 |
|
|---|
| 488 | ; Control registers.
|
|---|
| 489 | ; Would've liked to have these highere up in case of crashes, but
|
|---|
| 490 | ; the fpu stuff must be done before we restore cr0.
|
|---|
| 491 | mov ecx, [edx + CPUMCPU.Host.cr4]
|
|---|
| 492 | mov cr4, ecx
|
|---|
| 493 | mov ecx, [edx + CPUMCPU.Host.cr0]
|
|---|
| 494 | mov cr0, ecx
|
|---|
| 495 | ;mov ecx, [edx + CPUMCPU.Host.cr2] ; assumes this is waste of time.
|
|---|
| 496 | ;mov cr2, ecx
|
|---|
| 497 |
|
|---|
| 498 | ; restore debug registers (if modified) (esi must still be fUseFlags!)
|
|---|
| 499 | ; (must be done after cr4 reload because of the debug extension.)
|
|---|
| 500 | test esi, CPUM_USE_DEBUG_REGS | CPUM_USE_DEBUG_REGS_HOST
|
|---|
| 501 | jz short gth_debug_regs_no
|
|---|
| 502 | jmp gth_debug_regs_restore
|
|---|
| 503 | gth_debug_regs_no:
|
|---|
| 504 |
|
|---|
| 505 | ; restore general registers.
|
|---|
| 506 | mov eax, edi ; restore return code. eax = return code !!
|
|---|
| 507 | mov edi, [edx + CPUMCPU.Host.edi]
|
|---|
| 508 | mov esi, [edx + CPUMCPU.Host.esi]
|
|---|
| 509 | mov ebx, [edx + CPUMCPU.Host.ebx]
|
|---|
| 510 | mov ebp, [edx + CPUMCPU.Host.ebp]
|
|---|
| 511 | push dword [edx + CPUMCPU.Host.eflags]
|
|---|
| 512 | popfd
|
|---|
| 513 |
|
|---|
| 514 | %ifdef DEBUG_STUFF
|
|---|
| 515 | ; COM_S_CHAR '4'
|
|---|
| 516 | %endif
|
|---|
| 517 | retf
|
|---|
| 518 |
|
|---|
| 519 | ;;
|
|---|
| 520 | ; Detour for restoring the host debug registers.
|
|---|
| 521 | ; edx and edi must be preserved.
|
|---|
| 522 | gth_debug_regs_restore:
|
|---|
| 523 | DEBUG_S_CHAR('d')
|
|---|
| 524 | xor eax, eax
|
|---|
| 525 | mov dr7, eax ; paranoia or not?
|
|---|
| 526 | test esi, CPUM_USE_DEBUG_REGS
|
|---|
| 527 | jz short gth_debug_regs_dr7
|
|---|
| 528 | DEBUG_S_CHAR('r')
|
|---|
| 529 | mov eax, [edx + CPUMCPU.Host.dr0]
|
|---|
| 530 | mov dr0, eax
|
|---|
| 531 | mov ebx, [edx + CPUMCPU.Host.dr1]
|
|---|
| 532 | mov dr1, ebx
|
|---|
| 533 | mov ecx, [edx + CPUMCPU.Host.dr2]
|
|---|
| 534 | mov dr2, ecx
|
|---|
| 535 | mov eax, [edx + CPUMCPU.Host.dr3]
|
|---|
| 536 | mov dr3, eax
|
|---|
| 537 | gth_debug_regs_dr7:
|
|---|
| 538 | mov ebx, [edx + CPUMCPU.Host.dr6]
|
|---|
| 539 | mov dr6, ebx
|
|---|
| 540 | mov ecx, [edx + CPUMCPU.Host.dr7]
|
|---|
| 541 | mov dr7, ecx
|
|---|
| 542 | jmp gth_debug_regs_no
|
|---|
| 543 |
|
|---|
| 544 | ENDPROC VMMGCGuestToHostAsm
|
|---|
| 545 |
|
|---|
| 546 | ;;
|
|---|
| 547 | ; VMMGCGuestToHostAsmHyperCtx
|
|---|
| 548 | ;
|
|---|
| 549 | ; This is an alternative entry point which we'll be using
|
|---|
| 550 | ; when the we have the hypervisor context and need to save
|
|---|
| 551 | ; that before going to the host.
|
|---|
| 552 | ;
|
|---|
| 553 | ; This is typically useful when abandoning the hypervisor
|
|---|
| 554 | ; because of a trap and want the trap state to be saved.
|
|---|
| 555 | ;
|
|---|
| 556 | ; @param eax Return code.
|
|---|
| 557 | ; @param ecx Points to CPUMCTXCORE.
|
|---|
| 558 | ; @uses eax,edx,ecx
|
|---|
| 559 | ALIGNCODE(16)
|
|---|
| 560 | BEGINPROC VMMGCGuestToHostAsmHyperCtx
|
|---|
| 561 | int3
|
|---|
| 562 |
|
|---|
| 563 | ;;
|
|---|
| 564 | ; VMMGCGuestToHostAsmGuestCtx
|
|---|
| 565 | ;
|
|---|
| 566 | ; Switches from Guest Context to Host Context.
|
|---|
| 567 | ; Of course it's only called from within the GC.
|
|---|
| 568 | ;
|
|---|
| 569 | ; @param eax Return code.
|
|---|
| 570 | ; @param esp + 4 Pointer to CPUMCTXCORE.
|
|---|
| 571 | ;
|
|---|
| 572 | ; @remark ASSUMES interrupts disabled.
|
|---|
| 573 | ;
|
|---|
| 574 | ALIGNCODE(16)
|
|---|
| 575 | BEGINPROC VMMGCGuestToHostAsmGuestCtx
|
|---|
| 576 | int3
|
|---|
| 577 |
|
|---|
| 578 | GLOBALNAME End
|
|---|
| 579 | ;
|
|---|
| 580 | ; The description string (in the text section).
|
|---|
| 581 | ;
|
|---|
| 582 | NAME(Description):
|
|---|
| 583 | db "32-bits to/from AMD64", 0
|
|---|
| 584 |
|
|---|
| 585 | extern NAME(Relocate)
|
|---|
| 586 |
|
|---|
| 587 | ;
|
|---|
| 588 | ; End the fixup records.
|
|---|
| 589 | ;
|
|---|
| 590 | BEGINDATA
|
|---|
| 591 | db FIX_THE_END ; final entry.
|
|---|
| 592 | GLOBALNAME FixupsEnd
|
|---|
| 593 |
|
|---|
| 594 | ;;
|
|---|
| 595 | ; The switcher definition structure.
|
|---|
| 596 | ALIGNDATA(16)
|
|---|
| 597 | GLOBALNAME Def
|
|---|
| 598 | istruc VMMSWITCHERDEF
|
|---|
| 599 | at VMMSWITCHERDEF.pvCode, RTCCPTR_DEF NAME(Start)
|
|---|
| 600 | at VMMSWITCHERDEF.pvFixups, RTCCPTR_DEF NAME(Fixups)
|
|---|
| 601 | at VMMSWITCHERDEF.pszDesc, RTCCPTR_DEF NAME(Description)
|
|---|
| 602 | at VMMSWITCHERDEF.pfnRelocate, RTCCPTR_DEF NAME(Relocate)
|
|---|
| 603 | at VMMSWITCHERDEF.enmType, dd VMMSWITCHER_32_TO_AMD64
|
|---|
| 604 | at VMMSWITCHERDEF.cbCode, dd NAME(End) - NAME(Start)
|
|---|
| 605 | at VMMSWITCHERDEF.offR0HostToGuest, dd NAME(vmmR0HostToGuest) - NAME(Start)
|
|---|
| 606 | at VMMSWITCHERDEF.offGCGuestToHost, dd NAME(vmmGCGuestToHost) - NAME(Start)
|
|---|
| 607 | at VMMSWITCHERDEF.offGCCallTrampoline, dd NAME(vmmGCCallTrampoline) - NAME(Start)
|
|---|
| 608 | at VMMSWITCHERDEF.offGCGuestToHostAsm, dd NAME(VMMGCGuestToHostAsm) - NAME(Start)
|
|---|
| 609 | at VMMSWITCHERDEF.offGCGuestToHostAsmHyperCtx, dd NAME(VMMGCGuestToHostAsmHyperCtx)- NAME(Start)
|
|---|
| 610 | at VMMSWITCHERDEF.offGCGuestToHostAsmGuestCtx, dd NAME(VMMGCGuestToHostAsmGuestCtx)- NAME(Start)
|
|---|
| 611 | ; disasm help
|
|---|
| 612 | at VMMSWITCHERDEF.offHCCode0, dd 0
|
|---|
| 613 | at VMMSWITCHERDEF.cbHCCode0, dd NAME(IDEnterTarget) - NAME(Start)
|
|---|
| 614 | at VMMSWITCHERDEF.offHCCode1, dd NAME(ICExitTarget) - NAME(Start)
|
|---|
| 615 | at VMMSWITCHERDEF.cbHCCode1, dd NAME(End) - NAME(ICExitTarget)
|
|---|
| 616 | at VMMSWITCHERDEF.offIDCode0, dd NAME(IDEnterTarget) - NAME(Start)
|
|---|
| 617 | at VMMSWITCHERDEF.cbIDCode0, dd NAME(ICEnterTarget) - NAME(IDEnterTarget)
|
|---|
| 618 | at VMMSWITCHERDEF.offIDCode1, dd NAME(IDExitTarget) - NAME(Start)
|
|---|
| 619 | at VMMSWITCHERDEF.cbIDCode1, dd NAME(ICExitTarget) - NAME(IDExitTarget)
|
|---|
| 620 | at VMMSWITCHERDEF.offGCCode, dd NAME(ICEnterTarget) - NAME(Start)
|
|---|
| 621 | at VMMSWITCHERDEF.cbGCCode, dd NAME(IDExitTarget) - NAME(ICEnterTarget)
|
|---|
| 622 |
|
|---|
| 623 | iend
|
|---|
| 624 |
|
|---|
