AMD64ToPAE.asm@ 2705

Last change on this file since 2705 was 1645, checked in by vboxsync, 18 years ago
removed some leftover debug code (amd64 tripple-fault)
Property svn:eol-style set to `native` Property svn:keywords set to `Id`
File size: 31.8 KB

Line
1	; $Id: AMD64ToPAE.asm 1645 2007-03-22 18:13:16Z vboxsync $
2	;; @file
3	; VMM - World Switchers, AMD64 to PAE.
4	;
5
6	;
7	; Copyright (C) 2006 InnoTek Systemberatung GmbH
8	;
9	; This file is part of VirtualBox Open Source Edition (OSE), as
10	; available from http://www.virtualbox.org. This file is free software;
11	; you can redistribute it and/or modify it under the terms of the GNU
12	; General Public License as published by the Free Software Foundation,
13	; in version 2 as it comes in the "COPYING" file of the VirtualBox OSE
14	; distribution. VirtualBox OSE is distributed in the hope that it will
15	; be useful, but WITHOUT ANY WARRANTY of any kind.
16	;
17	; If you received this file as part of a commercial VirtualBox
18	; distribution, then only the terms of your commercial VirtualBox
19	; license agreement apply instead of the previous paragraph.
20	;
21
22	;%define DEBUG_STUFF 1
23	;%define STRICT_IF 1
24
25	;*******************************************************************************
26	;* Defined Constants And Macros *
27	;*******************************************************************************
28	;; Prefix all names.
29	%define NAME_OVERLOAD(name) vmmR3SwitcherAMD64ToPAE_ %+ name
30
31
32	;*******************************************************************************
33	;* Header Files *
34	;*******************************************************************************
35	%include "VBox/asmdefs.mac"
36	%include "VBox/x86.mac"
37	%include "VBox/cpum.mac"
38	%include "VBox/stam.mac"
39	%include "VBox/vm.mac"
40	%include "CPUMInternal.mac"
41	%include "VMMSwitcher/VMMSwitcher.mac"
42
43
44	;
45	; Start the fixup records
46	; We collect the fixups in the .data section as we go along
47	; It is therefore VITAL that no-one is using the .data section
48	; for anything else between 'Start' and 'End'.
49	;
50	BEGINDATA
51	GLOBALNAME Fixups
52
53
54
55	BEGINCODE
56	GLOBALNAME Start
57
58	%ifndef VBOX_WITH_HYBIRD_32BIT_KERNEL
59	BITS 64
60
61	;;
62	; The C interface.
63	;
64	; @param pVM GCC: rdi MSC:rcx The VM handle.
65	;
66	BEGINPROC vmmR0HostToGuest
67	%ifdef DEBUG_STUFF
68	COM64_S_NEWLINE
69	COM64_S_CHAR '^'
70	%endif
71	;
72	; The ordinary version of the code.
73	;
74
75	%ifdef STRICT_IF
76	pushf
77	pop rax
78	test eax, X86_EFL_IF
79	jz .if_clear_in
80	mov eax, 0c0ffee00h
81	ret
82	.if_clear_in:
83	%endif
84
85	;
86	; make r9 = pVM and rdx = pCpum.
87	; rax, rcx and r8 are scratch here after.
88	%ifdef __WIN64__
89	mov r9, rcx
90	%else
91	mov r9, rdi
92	%endif
93	lea rdx, [r9 + VM.cpum]
94
95	%ifdef VBOX_WITH_STATISTICS
96	;
97	; Switcher stats.
98	;
99	lea r8, [r9 + VM.StatSwitcherToGC]
100	STAM64_PROFILE_ADV_START r8
101	%endif
102
103	;
104	; Call worker (far return).
105	;
106	mov eax, cs
107	push rax
108	call NAME(vmmR0HostToGuestAsm)
109
110	%ifdef VBOX_WITH_STATISTICS
111	;
112	; Switcher stats.
113	;
114	lea r8, [r9 + VM.StatSwitcherToGC]
115	STAM64_PROFILE_ADV_STOP r8
116	%endif
117
118	ret
119	ENDPROC vmmR0HostToGuest
120
121
122	%else ; VBOX_WITH_HYBIRD_32BIT_KERNEL
123
124
125	BITS 32
126
127	;;
128	; The C interface.
129	;
130	BEGINPROC vmmR0HostToGuest
131	%ifdef DEBUG_STUFF
132	COM32_S_NEWLINE
133	COM32_S_CHAR '^'
134	%endif
135
136	%ifdef VBOX_WITH_STATISTICS
137	;
138	; Switcher stats.
139	;
140	FIXUP FIX_HC_VM_OFF, 1, VM.StatSwitcherToGC
141	mov edx, 0ffffffffh
142	STAM_PROFILE_ADV_START edx
143	%endif
144
145	; Thunk to/from 64 bit when invoking the worker routine.
146	;
147	FIXUP FIX_HC_VM_OFF, 1, VM.cpum
148	mov edx, 0ffffffffh
149
150	push 0
151	push cs
152	push 0
153	FIXUP FIX_HC_32BIT, 1, .vmmR0HostToGuestReturn - NAME(Start)
154	push 0ffffffffh
155
156	FIXUP FIX_HC_64BIT_CS, 1
157	push 0ffffh
158	FIXUP FIX_HC_32BIT, 1, NAME(vmmR0HostToGuestAsm) - NAME(Start)
159	push NAME(vmmR0HostToGuestAsm)
160	retf
161	.vmmR0HostToGuestReturn:
162
163	;
164	; This selector reloading is probably not necessary, but we do it anyway to be quite sure
165	; the CPU has the right idea about the selectors.
166	;
167	mov edx, ds
168	mov ds, edx
169	mov ecx, es
170	mov es, ecx
171	mov edx, ss
172	mov ss, edx
173
174	%ifdef VBOX_WITH_STATISTICS
175	;
176	; Switcher stats.
177	;
178	FIXUP FIX_HC_VM_OFF, 1, VM.StatSwitcherToHC
179	mov edx, 0ffffffffh
180	STAM_PROFILE_ADV_STOP edx
181	%endif
182
183	ret
184	ENDPROC vmmR0HostToGuest
185
186	BITS 64
187	%endif ;!VBOX_WITH_HYBIRD_32BIT_KERNEL
188
189
190
191	; *****************************************************************************
192	; vmmR0HostToGuestAsm
193	;
194	; Phase one of the switch from host to guest context (host MMU context)
195	;
196	; INPUT:
197	; - edx virtual address of CPUM structure (valid in host context)
198	;
199	; USES/DESTROYS:
200	; - eax, ecx, edx
201	;
202	; ASSUMPTION:
203	; - current CS and DS selectors are wide open
204	;
205	; *****************************************************************************
206	ALIGNCODE(16)
207	BEGINPROC vmmR0HostToGuestAsm
208	;;
209	;; Save CPU host context
210	;; Skip eax, edx and ecx as these are not preserved over calls.
211	;;
212	; general registers.
213	; mov [rdx + CPUM.Host.rax], rax - scratch
214	mov [rdx + CPUM.Host.rbx], rbx
215	; mov [rdx + CPUM.Host.rcx], rcx - scratch
216	; mov [rdx + CPUM.Host.rdx], rdx - scratch
217	mov [rdx + CPUM.Host.rdi], rdi
218	mov [rdx + CPUM.Host.rsi], rsi
219	mov [rdx + CPUM.Host.rsp], rsp
220	mov [rdx + CPUM.Host.rbp], rbp
221	; mov [rdx + CPUM.Host.r8 ], r8 - scratch
222	; mov [rdx + CPUM.Host.r9 ], r9 - scratch
223	mov [rdx + CPUM.Host.r10], r10
224	mov [rdx + CPUM.Host.r11], r11
225	mov [rdx + CPUM.Host.r12], r12
226	mov [rdx + CPUM.Host.r13], r13
227	mov [rdx + CPUM.Host.r14], r14
228	mov [rdx + CPUM.Host.r15], r15
229	; selectors.
230	mov [rdx + CPUM.Host.ds], ds
231	mov [rdx + CPUM.Host.es], es
232	mov [rdx + CPUM.Host.fs], fs
233	mov [rdx + CPUM.Host.gs], gs
234	mov [rdx + CPUM.Host.ss], ss
235	; MSRs
236	mov rbx, rdx
237	mov ecx, MSR_K8_FS_BASE
238	rdmsr
239	mov [rbx + CPUM.Host.FSbase], eax
240	mov [rbx + CPUM.Host.FSbase + 4], edx
241	mov ecx, MSR_K8_GS_BASE
242	rdmsr
243	mov [rbx + CPUM.Host.GSbase], eax
244	mov [rbx + CPUM.Host.GSbase + 4], edx
245	mov ecx, MSR_K6_EFER
246	rdmsr
247	mov [rbx + CPUM.Host.efer], eax
248	mov [rbx + CPUM.Host.efer + 4], edx
249	mov ecx, MSR_K6_EFER
250	mov rdx, rbx
251	; special registers.
252	sldt [rdx + CPUM.Host.ldtr]
253	sidt [rdx + CPUM.Host.idtr]
254	sgdt [rdx + CPUM.Host.gdtr]
255	str [rdx + CPUM.Host.tr] ; yasm BUG, generates sldt. YASMCHECK!
256	; flags
257	pushf
258	pop qword [rdx + CPUM.Host.rflags]
259
260	FIXUP FIX_NO_SYSENTER_JMP, 0, htg_no_sysenter - NAME(Start) ; this will insert a jmp htg_no_sysenter if host doesn't use sysenter.
261	; save MSR_IA32_SYSENTER_CS register.
262	mov ecx, MSR_IA32_SYSENTER_CS
263	mov rbx, rdx ; save edx
264	rdmsr ; edx:eax <- MSR[ecx]
265	mov [rbx + CPUM.Host.SysEnter.cs], rax
266	mov [rbx + CPUM.Host.SysEnter.cs + 4], rdx
267	xor rax, rax ; load 0:0 to cause #GP upon sysenter
268	xor rdx, rdx
269	wrmsr
270	mov rdx, rbx ; restore edx
271	jmp short htg_no_sysenter
272
273	ALIGNCODE(16)
274	htg_no_sysenter:
275
276	;; handle use flags.
277	mov esi, [rdx + CPUM.fUseFlags] ; esi == use flags.
278	and esi, ~CPUM_USED_FPU ; Clear CPUM_USED_* flags. ;;@todo FPU check can be optimized to use cr0 flags!
279	mov [rdx + CPUM.fUseFlags], esi
280
281	; debug registers.
282	test esi, CPUM_USE_DEBUG_REGS \| CPUM_USE_DEBUG_REGS_HOST
283	jz htg_debug_regs_no
284	jmp htg_debug_regs_save
285	htg_debug_regs_no:
286	DEBUG_CHAR('a') ; trashes esi
287
288	; control registers.
289	mov rax, cr0
290	mov [rdx + CPUM.Host.cr0], rax
291	;mov rax, cr2 ; assume host os don't suff things in cr2. (safe)
292	;mov [rdx + CPUM.Host.cr2], rax
293	mov rax, cr3
294	mov [rdx + CPUM.Host.cr3], rax
295	mov rax, cr4
296	mov [rdx + CPUM.Host.cr4], rax
297
298	;;
299	;; Start switching to VMM context.
300	;;
301
302	;
303	; Change CR0 and CR4 so we can correctly emulate FPU/MMX/SSE[23] exceptions
304	; Also disable WP. (eax==cr4 now)
305	; Note! X86_CR4_PSE and X86_CR4_PAE are important if the host thinks so :-)
306	;
307	and rax, X86_CR4_MCE \| X86_CR4_PSE \| X86_CR4_PAE
308	mov ecx, [rdx + CPUM.Guest.cr4]
309	DEBUG_CHAR('b') ; trashes esi
310	;; @todo Switcher cleanup: Determin base CR4 during CPUMR0Init / VMMR3SelectSwitcher putting it
311	; in CPUM.Hyper.cr4 (which isn't currently being used). That should
312	; simplify this operation a bit (and improve locality of the data).
313
314	;
315	; CR4.AndMask and CR4.OrMask are set in CPUMR3Init based on the presence of
316	; FXSAVE support on the host CPU
317	;
318	and ecx, [rdx + CPUM.CR4.AndMask]
319	or eax, ecx
320	or eax, [rdx + CPUM.CR4.OrMask]
321	mov cr4, rax
322	DEBUG_CHAR('c') ; trashes esi
323
324	mov eax, [rdx + CPUM.Guest.cr0]
325	and eax, X86_CR0_EM
326	or eax, X86_CR0_PE \| X86_CR0_PG \| X86_CR0_TS \| X86_CR0_ET \| X86_CR0_NE \| X86_CR0_MP
327	mov cr0, rax
328	DEBUG_CHAR('0') ; trashes esi
329
330
331	; Load new gdt so we can do far jump to guest code after cr3 reload.
332	lgdt [rdx + CPUM.Hyper.gdtr]
333	DEBUG_CHAR('1') ; trashes esi
334
335	;;
336	;; Load Intermediate memory context.
337	;;
338	FIXUP FIX_INTER_AMD64_CR3, 1
339	mov eax, 0ffffffffh
340	mov cr3, rax
341	DEBUG_CHAR('2') ; trashes esi
342
343	;;
344	;; 1. Switch to compatibility mode, placing ourselves in identity mapped code.
345	;;
346	jmp far [NAME(fpIDEnterTarget) wrt rip]
347
348	; 16:32 Pointer to IDEnterTarget.
349	NAME(fpIDEnterTarget):
350	FIXUP FIX_ID_32BIT, 0, NAME(IDEnterTarget) - NAME(Start)
351	dd 0
352	FIXUP FIX_HYPER_CS, 0
353	dd 0
354
355
356	;;
357	; Detour for saving the host DR7 and DR6.
358	; esi and rdx must be preserved.
359	htg_debug_regs_save:
360	DEBUG_S_CHAR('s');
361	mov rax, dr7 ; not sure, but if I read the docs right this will trap if GD is set. FIXME!!!
362	mov [rdx + CPUM.Host.dr7], rax
363	xor eax, eax ; clear everything. (bit 12? is read as 1...)
364	mov dr7, rax
365	mov rax, dr6 ; just in case we save the state register too.
366	mov [rdx + CPUM.Host.dr6], rax
367	; save host DR0-3?
368	test esi, CPUM_USE_DEBUG_REGS
369	jz near htg_debug_regs_no
370	DEBUG_S_CHAR('S');
371	mov rax, dr0
372	mov [rdx + CPUM.Host.dr0], rax
373	mov rbx, dr1
374	mov [rdx + CPUM.Host.dr1], rbx
375	mov rcx, dr2
376	mov [rdx + CPUM.Host.dr2], rcx
377	mov rax, dr3
378	mov [rdx + CPUM.Host.dr3], rax
379	jmp htg_debug_regs_no
380
381
382	; We're now on an identity mapped pages! in 32-bit compatability mode.
383	BITS 32
384	ALIGNCODE(16)
385	GLOBALNAME IDEnterTarget
386	DEBUG_CHAR('3')
387
388	; 2. Deactivate long mode by turning off paging.
389	mov ebx, cr0
390	and ebx, ~X86_CR0_PG
391	mov cr0, ebx
392	DEBUG_CHAR('4')
393
394	; 3. Load 32-bit intermediate page table.
395	FIXUP FIX_INTER_PAE_CR3, 1
396	mov edx, 0ffffffffh
397	mov cr3, edx
398
399	; 4. Disable long mode.
400	; We also use the chance to disable syscall/sysret and fast fxsave/fxrstor.
401	mov ecx, MSR_K6_EFER
402	rdmsr
403	DEBUG_CHAR('5')
404	and eax, ~(MSR_K6_EFER_LME \| MSR_K6_EFER_SCE \| MSR_K6_EFER_FFXSR)
405	wrmsr
406	DEBUG_CHAR('6')
407
408	; 5. Enable paging.
409	or ebx, X86_CR0_PG
410	mov cr0, ebx
411	jmp short just_a_jump
412	just_a_jump:
413	DEBUG_CHAR('7')
414
415	;;
416	;; 6. Jump to guest code mapping of the code and load the Hypervisor CS.
417	;;
418	FIXUP FIX_ID_2_GC_NEAR_REL, 1, NAME(JmpGCTarget) - NAME(Start)
419	jmp near NAME(JmpGCTarget)
420
421
422	;;
423	;; When we arrive at this label we're at the
424	;; guest code mapping of the switching code.
425	;;
426	ALIGNCODE(16)
427	GLOBALNAME JmpGCTarget
428	DEBUG_CHAR('-')
429	; load final cr3 and do far jump to load cs.
430	FIXUP FIX_HYPER_PAE_CR3, 1
431	mov eax, 0ffffffffh
432	mov cr3, eax
433	DEBUG_CHAR('0')
434
435	;;
436	;; We're in VMM MMU context and VMM CS is loaded.
437	;; Setup the rest of the VMM state.
438	;;
439	; Load selectors
440	DEBUG_CHAR('1')
441	FIXUP FIX_HYPER_DS, 1
442	mov eax, 0ffffh
443	mov ds, eax
444	mov es, eax
445	xor eax, eax
446	mov gs, eax
447	mov fs, eax
448	; Load pCpum into EDX
449	FIXUP FIX_GC_CPUM_OFF, 1, 0
450	mov edx, 0ffffffffh
451	; Activate guest IDT
452	DEBUG_CHAR('2')
453	lidt [edx + CPUM.Hyper.idtr]
454
455	; Setup stack
456	DEBUG_CHAR('3')
457	lss esp, [edx + CPUM.Hyper.esp]
458
459	; Restore TSS selector; must mark it as not busy before using ltr (!)
460	DEBUG_CHAR('4')
461	FIXUP FIX_GC_TSS_GDTE_DW2, 2
462	and dword [0ffffffffh], ~0200h ; clear busy flag (2nd type2 bit)
463	DEBUG_CHAR('5')
464	ltr word [edx + CPUM.Hyper.tr]
465	DEBUG_CHAR('6')
466
467	; Activate the ldt (now we can safely crash).
468	lldt [edx + CPUM.Hyper.ldtr]
469	DEBUG_CHAR('7')
470
471	;; use flags.
472	mov esi, [edx + CPUM.fUseFlags]
473
474	; debug registers
475	test esi, CPUM_USE_DEBUG_REGS
476	jz htg_debug_regs_guest_no
477	jmp htg_debug_regs_guest
478	htg_debug_regs_guest_no:
479	DEBUG_CHAR('9')
480
481	; General registers.
482	mov ebx, [edx + CPUM.Hyper.ebx]
483	mov ebp, [edx + CPUM.Hyper.ebp]
484	mov esi, [edx + CPUM.Hyper.esi]
485	mov edi, [edx + CPUM.Hyper.edi]
486	push dword [edx + CPUM.Hyper.eflags]
487	popfd
488	DEBUG_CHAR('!')
489
490	;;
491	;; Return to the VMM code which either called the switcher or
492	;; the code set up to run by HC.
493	;;
494	%ifdef DEBUG_STUFF
495	COM32_S_PRINT ';eip='
496	mov eax, [edx + CPUM.Hyper.eip]
497	COM32_S_DWORD_REG eax
498	COM32_S_CHAR ';'
499	%endif
500	mov eax, [edx + CPUM.Hyper.eip]
501	%ifdef VBOX_WITH_STATISTICS
502	FIXUP FIX_GC_VM_OFF, 1, VM.StatSwitcherToGC
503	mov edx, 0ffffffffh
504	STAM32_PROFILE_ADV_STOP edx
505	FIXUP FIX_GC_CPUM_OFF, 1, 0
506	mov edx, 0ffffffffh
507	%endif
508	jmp eax
509
510	;;
511	; Detour for saving host DR0-3 and loading hypervisor debug registers.
512	; esi and edx must be preserved.
513	htg_debug_regs_guest:
514	DEBUG_S_CHAR('D')
515	DEBUG_S_CHAR('R')
516	DEBUG_S_CHAR('x')
517	; load hyper DR0-7
518	mov ebx, [edx + CPUM.Hyper.dr0]
519	mov dr0, ebx
520	mov ecx, [edx + CPUM.Hyper.dr1]
521	mov dr1, ecx
522	mov eax, [edx + CPUM.Hyper.dr2]
523	mov dr2, eax
524	mov ebx, [edx + CPUM.Hyper.dr3]
525	mov dr3, ebx
526	;mov eax, [edx + CPUM.Hyper.dr6]
527	mov ecx, 0ffff0ff0h
528	mov dr6, ecx
529	mov eax, [edx + CPUM.Hyper.dr7]
530	mov dr7, eax
531	jmp htg_debug_regs_guest_no
532
533	ENDPROC vmmR0HostToGuestAsm
534
535
536	;;
537	; Trampoline for doing a call when starting the hyper visor execution.
538	;
539	; Push any arguments to the routine.
540	; Push the argument frame size (cArg * 4).
541	; Push the call target (_cdecl convention).
542	; Push the address of this routine.
543	;
544	;
545	ALIGNCODE(16)
546	BEGINPROC vmmGCCallTrampoline
547	%ifdef DEBUG_STUFF
548	COM32_S_CHAR 'c'
549	COM32_S_CHAR 't'
550	COM32_S_CHAR '!'
551	%endif
552
553	; call routine
554	pop eax ; call address
555	mov esi, edx ; save edx
556	pop edi ; argument count.
557	%ifdef DEBUG_STUFF
558	COM32_S_PRINT ';eax='
559	COM32_S_DWORD_REG eax
560	COM32_S_CHAR ';'
561	%endif
562	call eax ; do call
563	add esp, edi ; cleanup stack
564
565	; return to the host context.
566	push byte 0 ; eip
567	mov edx, esi ; CPUM pointer
568
569	%ifdef DEBUG_STUFF
570	COM32_S_CHAR '`'
571	%endif
572	jmp NAME(VMMGCGuestToHostAsm) ; eax = returncode.
573	ENDPROC vmmGCCallTrampoline
574
575
576
577	;;
578	; The C interface.
579	;
580	ALIGNCODE(16)
581	BEGINPROC vmmGCGuestToHost
582	%ifdef DEBUG_STUFF
583	push esi
584	COM_NEWLINE
585	DEBUG_CHAR('b')
586	DEBUG_CHAR('a')
587	DEBUG_CHAR('c')
588	DEBUG_CHAR('k')
589	DEBUG_CHAR('!')
590	COM_NEWLINE
591	pop esi
592	%endif
593	mov eax, [esp + 4]
594	jmp NAME(VMMGCGuestToHostAsm)
595	ENDPROC vmmGCGuestToHost
596
597
598	;;
599	; VMMGCGuestToHostAsmGuestCtx
600	;
601	; Switches from Guest Context to Host Context.
602	; Of course it's only called from within the GC.
603	;
604	; @param eax Return code.
605	; @param esp + 4 Pointer to CPUMCTXCORE.
606	;
607	; @remark ASSUMES interrupts disabled.
608	;
609	ALIGNCODE(16)
610	BEGINPROC VMMGCGuestToHostAsmGuestCtx
611	DEBUG_CHAR('~')
612
613	%ifdef VBOX_WITH_STATISTICS
614	FIXUP FIX_GC_VM_OFF, 1, VM.StatTotalInGC
615	mov edx, 0ffffffffh
616	STAM32_PROFILE_ADV_STOP edx
617
618	FIXUP FIX_GC_VM_OFF, 1, VM.StatTotalGCToQemu
619	mov edx, 0ffffffffh
620	STAM32_PROFILE_ADV_START edx
621
622	FIXUP FIX_GC_VM_OFF, 1, VM.StatSwitcherToHC
623	mov edx, 0ffffffffh
624	STAM32_PROFILE_ADV_START edx
625	%endif
626
627	;
628	; Load the CPUM pointer.
629	;
630	FIXUP FIX_GC_CPUM_OFF, 1, 0
631	mov edx, 0ffffffffh
632
633	; Skip return address (assumes called!)
634	lea esp, [esp + 4]
635
636	;
637	; Guest Context (assumes CPUMCTXCORE layout).
638	;
639	; general purpose registers (layout is pushad)
640	pop dword [edx + CPUM.Guest.edi]
641	pop dword [edx + CPUM.Guest.esi]
642	pop dword [edx + CPUM.Guest.ebp]
643	pop dword [edx + CPUM.Guest.eax]
644	pop dword [edx + CPUM.Guest.ebx]
645	pop dword [edx + CPUM.Guest.edx]
646	pop dword [edx + CPUM.Guest.ecx]
647	pop dword [edx + CPUM.Guest.esp]
648	pop dword [edx + CPUM.Guest.ss]
649	pop dword [edx + CPUM.Guest.gs]
650	pop dword [edx + CPUM.Guest.fs]
651	pop dword [edx + CPUM.Guest.es]
652	pop dword [edx + CPUM.Guest.ds]
653	pop dword [edx + CPUM.Guest.cs]
654	; flags
655	pop dword [edx + CPUM.Guest.eflags]
656	; eip
657	pop dword [edx + CPUM.Guest.eip]
658	jmp vmmGCGuestToHostAsm_EIPDone
659	ENDPROC VMMGCGuestToHostAsmGuestCtx
660
661
662	;;
663	; VMMGCGuestToHostAsmHyperCtx
664	;
665	; This is an alternative entry point which we'll be using
666	; when the we have the hypervisor context and need to save
667	; that before going to the host.
668	;
669	; This is typically useful when abandoning the hypervisor
670	; because of a trap and want the trap state to be saved.
671	;
672	; @param eax Return code.
673	; @param ecx Points to CPUMCTXCORE.
674	; @uses eax,edx,ecx
675	ALIGNCODE(16)
676	BEGINPROC VMMGCGuestToHostAsmHyperCtx
677	DEBUG_CHAR('#')
678
679	%ifdef VBOX_WITH_STATISTICS
680	FIXUP FIX_GC_VM_OFF, 1, VM.StatTotalInGC
681	mov edx, 0ffffffffh
682	STAM32_PROFILE_ADV_STOP edx
683
684	FIXUP FIX_GC_VM_OFF, 1, VM.StatTotalGCToQemu
685	mov edx, 0ffffffffh
686	STAM32_PROFILE_ADV_START edx
687
688	FIXUP FIX_GC_VM_OFF, 1, VM.StatSwitcherToHC
689	mov edx, 0ffffffffh
690	STAM32_PROFILE_ADV_START edx
691	%endif
692
693	;
694	; Load the CPUM pointer.
695	;
696	FIXUP FIX_GC_CPUM_OFF, 1, 0
697	mov edx, 0ffffffffh
698
699	push eax ; save return code.
700	; general purpose registers
701	mov eax, [ecx + CPUMCTXCORE.edi]
702	mov [edx + CPUM.Hyper.edi], eax
703	mov eax, [ecx + CPUMCTXCORE.esi]
704	mov [edx + CPUM.Hyper.esi], eax
705	mov eax, [ecx + CPUMCTXCORE.ebp]
706	mov [edx + CPUM.Hyper.ebp], eax
707	mov eax, [ecx + CPUMCTXCORE.eax]
708	mov [edx + CPUM.Hyper.eax], eax
709	mov eax, [ecx + CPUMCTXCORE.ebx]
710	mov [edx + CPUM.Hyper.ebx], eax
711	mov eax, [ecx + CPUMCTXCORE.edx]
712	mov [edx + CPUM.Hyper.edx], eax
713	mov eax, [ecx + CPUMCTXCORE.ecx]
714	mov [edx + CPUM.Hyper.ecx], eax
715	mov eax, [ecx + CPUMCTXCORE.esp]
716	mov [edx + CPUM.Hyper.esp], eax
717	; selectors
718	mov eax, [ecx + CPUMCTXCORE.ss]
719	mov [edx + CPUM.Hyper.ss], eax
720	mov eax, [ecx + CPUMCTXCORE.gs]
721	mov [edx + CPUM.Hyper.gs], eax
722	mov eax, [ecx + CPUMCTXCORE.fs]
723	mov [edx + CPUM.Hyper.fs], eax
724	mov eax, [ecx + CPUMCTXCORE.es]
725	mov [edx + CPUM.Hyper.es], eax
726	mov eax, [ecx + CPUMCTXCORE.ds]
727	mov [edx + CPUM.Hyper.ds], eax
728	mov eax, [ecx + CPUMCTXCORE.cs]
729	mov [edx + CPUM.Hyper.cs], eax
730	; flags
731	mov eax, [ecx + CPUMCTXCORE.eflags]
732	mov [edx + CPUM.Hyper.eflags], eax
733	; eip
734	mov eax, [ecx + CPUMCTXCORE.eip]
735	mov [edx + CPUM.Hyper.eip], eax
736	; jump to common worker code.
737	pop eax ; restore return code.
738	jmp vmmGCGuestToHostAsm_SkipHyperRegs
739
740	ENDPROC VMMGCGuestToHostAsmHyperCtx
741
742
743	;;
744	; VMMGCGuestToHostAsm
745	;
746	; This is an alternative entry point which we'll be using
747	; when the we have saved the guest state already or we haven't
748	; been messing with the guest at all.
749	;
750	; @param eax Return code.
751	; @uses eax, edx, ecx (or it may use them in the future)
752	;
753	ALIGNCODE(16)
754	BEGINPROC VMMGCGuestToHostAsm
755	DEBUG_CHAR('%')
756
757	%ifdef VBOX_WITH_STATISTICS
758	FIXUP FIX_GC_VM_OFF, 1, VM.StatTotalInGC
759	mov edx, 0ffffffffh
760	STAM32_PROFILE_ADV_STOP edx
761
762	FIXUP FIX_GC_VM_OFF, 1, VM.StatTotalGCToQemu
763	mov edx, 0ffffffffh
764	STAM32_PROFILE_ADV_START edx
765
766	FIXUP FIX_GC_VM_OFF, 1, VM.StatSwitcherToHC
767	mov edx, 0ffffffffh
768	STAM32_PROFILE_ADV_START edx
769	%endif
770
771	;
772	; Load the CPUM pointer.
773	;
774	FIXUP FIX_GC_CPUM_OFF, 1, 0
775	mov edx, 0ffffffffh
776
777	pop dword [edx + CPUM.Hyper.eip] ; call return from stack
778	jmp short vmmGCGuestToHostAsm_EIPDone
779
780	ALIGNCODE(16)
781	vmmGCGuestToHostAsm_EIPDone:
782	; general registers which we care about.
783	mov dword [edx + CPUM.Hyper.ebx], ebx
784	mov dword [edx + CPUM.Hyper.esi], esi
785	mov dword [edx + CPUM.Hyper.edi], edi
786	mov dword [edx + CPUM.Hyper.ebp], ebp
787	mov dword [edx + CPUM.Hyper.esp], esp
788
789	; special registers which may change.
790	vmmGCGuestToHostAsm_SkipHyperRegs:
791	%ifdef STRICT_IF
792	pushf
793	pop ecx
794	test ecx, X86_EFL_IF
795	jz .if_clear_out
796	mov eax, 0c0ffee01h
797	cli
798	.if_clear_out:
799	%endif
800	; str [edx + CPUM.Hyper.tr] - double fault only, and it won't be right then either.
801	sldt [edx + CPUM.Hyper.ldtr]
802
803	; No need to save CRx here. They are set dynamically according to Guest/Host requirements.
804	; FPU context is saved before restore of host saving (another) branch.
805
806
807	;;
808	;; Load Intermediate memory context.
809	;;
810	mov edi, eax ; save return code in EDI (careful with COM_DWORD_REG from here on!)
811	FIXUP FIX_INTER_PAE_CR3, 1
812	mov eax, 0ffffffffh
813	mov cr3, eax
814	DEBUG_CHAR('?')
815
816	;; We're now in intermediate memory context!
817
818	;;
819	;; 0. Jump to identity mapped location
820	;;
821	FIXUP FIX_GC_2_ID_NEAR_REL, 1, NAME(IDExitTarget) - NAME(Start)
822	jmp near NAME(IDExitTarget)
823
824	; We're now on identity mapped pages!
825	ALIGNCODE(16)
826	GLOBALNAME IDExitTarget
827	DEBUG_CHAR('1')
828
829	; 1. Disable paging.
830	mov ebx, cr0
831	and ebx, ~X86_CR0_PG
832	mov cr0, ebx
833	DEBUG_CHAR('2')
834
835	; 2. Enable PAE - already enabled.
836
837	; 3. Load long mode intermediate CR3.
838	FIXUP FIX_INTER_AMD64_CR3, 1
839	mov ecx, 0ffffffffh
840	mov cr3, ecx
841	DEBUG_CHAR('3')
842
843	; 4. Enable long mode.
844	mov ebp, edx
845	mov ecx, MSR_K6_EFER
846	rdmsr
847	or eax, MSR_K6_EFER_LME
848	wrmsr
849	mov edx, ebp
850	DEBUG_CHAR('4')
851
852	; 5. Enable paging.
853	or ebx, X86_CR0_PG
854	mov cr0, ebx
855	DEBUG_CHAR('5')
856
857	; Jump from compatability mode to 64-bit mode.
858	FIXUP FIX_ID_FAR32_TO_64BIT_MODE, 1, NAME(IDExit64Mode) - NAME(Start)
859	jmp 0ffffh:0fffffffeh
860
861	;
862	; We're in 64-bit mode (ds, ss, es, fs, gs are all bogus).
863	; Move on to the HC mapping.
864	;
865	BITS 64
866	ALIGNCODE(16)
867	NAME(IDExit64Mode):
868	DEBUG_CHAR('6')
869	jmp [NAME(pHCExitTarget) wrt rip]
870
871	; 64-bit jump target
872	NAME(pHCExitTarget):
873	FIXUP FIX_HC_64BIT, 0, NAME(HCExitTarget) - NAME(Start)
874	dq 0ffffffffffffffffh
875
876	; 64-bit pCpum address.
877	NAME(pCpumHC):
878	FIXUP FIX_HC_64BIT_CPUM, 0
879	dq 0ffffffffffffffffh
880
881	;
882	; When we arrive here we're at the host context
883	; mapping of the switcher code.
884	;
885	ALIGNCODE(16)
886	GLOBALNAME HCExitTarget
887	DEBUG_CHAR('9')
888
889	; load final cr3
890	mov rsi, [rdx + CPUM.Host.cr3]
891	mov cr3, rsi
892	DEBUG_CHAR('@')
893
894	;;
895	;; Restore Host context.
896	;;
897	; Load CPUM pointer into edx
898	mov rdx, [NAME(pCpumHC) wrt rip]
899	; activate host gdt and idt
900	lgdt [rdx + CPUM.Host.gdtr]
901	DEBUG_CHAR('0')
902	lidt [rdx + CPUM.Host.idtr]
903	DEBUG_CHAR('1')
904	; Restore TSS selector; must mark it as not busy before using ltr (!)
905	%if 1 ; ASSUME that this is supposed to be 'BUSY'. (saves 20-30 ticks on the T42p)
906	movzx eax, word [rdx + CPUM.Host.tr] ; eax <- TR
907	and al, 0F8h ; mask away TI and RPL bits, get descriptor offset.
908	add rax, [rdx + CPUM.Host.gdtr + 2] ; eax <- GDTR.address + descriptor offset.
909	and dword [rax + 4], ~0200h ; clear busy flag (2nd type2 bit)
910	ltr word [rdx + CPUM.Host.tr]
911	%else
912	movzx eax, word [rdx + CPUM.Host.tr] ; eax <- TR
913	and al, 0F8h ; mask away TI and RPL bits, get descriptor offset.
914	add rax, [rdx + CPUM.Host.gdtr + 2] ; eax <- GDTR.address + descriptor offset.
915	mov ecx, [rax + 4] ; ecx <- 2nd descriptor dword
916	mov ebx, ecx ; save orginal value
917	and ecx, ~0200h ; clear busy flag (2nd type2 bit)
918	mov [rax + 4], ccx ; not using xchg here is paranoia..
919	ltr word [rdx + CPUM.Host.tr]
920	xchg [rax + 4], ebx ; using xchg is paranoia too...
921	%endif
922	; activate ldt
923	DEBUG_CHAR('2')
924	lldt [rdx + CPUM.Host.ldtr]
925	; Restore segment registers
926	mov eax, [rdx + CPUM.Host.ds]
927	mov ds, eax
928	mov eax, [rdx + CPUM.Host.es]
929	mov es, eax
930	mov eax, [rdx + CPUM.Host.fs]
931	mov fs, eax
932	mov eax, [rdx + CPUM.Host.gs]
933	mov gs, eax
934	; restore stack
935	mov eax, [rdx + CPUM.Host.ss]
936	mov ss, eax
937	mov rsp, [rdx + CPUM.Host.rsp]
938
939	FIXUP FIX_NO_SYSENTER_JMP, 0, gth_sysenter_no - NAME(Start) ; this will insert a jmp gth_sysenter_no if host doesn't use sysenter.
940	; restore MSR_IA32_SYSENTER_CS register.
941	mov ecx, MSR_IA32_SYSENTER_CS
942	mov eax, [rdx + CPUM.Host.SysEnter.cs]
943	mov ebx, [rdx + CPUM.Host.SysEnter.cs + 4]
944	mov rbx, rdx ; save/load edx
945	wrmsr ; MSR[ecx] <- edx:eax
946	mov rdx, rbx ; restore edx
947	jmp short gth_sysenter_no
948
949	ALIGNCODE(16)
950	gth_sysenter_no:
951
952	;; @todo AMD syscall
953
954	; Restore FPU if guest has used it.
955	; Using fxrstor should ensure that we're not causing unwanted exception on the host.
956	mov esi, [rdx + CPUM.fUseFlags] ; esi == use flags.
957	test esi, CPUM_USED_FPU
958	jz short gth_fpu_no
959	mov rcx, cr0
960	and rcx, ~(X86_CR0_TS \| X86_CR0_EM)
961	mov cr0, rcx
962
963	fxsave [rdx + CPUM.Guest.fpu]
964	fxrstor [rdx + CPUM.Host.fpu]
965	jmp short gth_fpu_no
966
967	ALIGNCODE(16)
968	gth_fpu_no:
969
970	; Control registers.
971	; Would've liked to have these highere up in case of crashes, but
972	; the fpu stuff must be done before we restore cr0.
973	mov rcx, [rdx + CPUM.Host.cr4]
974	mov cr4, rcx
975	mov rcx, [rdx + CPUM.Host.cr0]
976	mov cr0, rcx
977	;mov rcx, [rdx + CPUM.Host.cr2] ; assumes this is waste of time.
978	;mov cr2, rcx
979
980	; restore debug registers (if modified) (esi must still be fUseFlags!)
981	; (must be done after cr4 reload because of the debug extension.)
982	test esi, CPUM_USE_DEBUG_REGS \| CPUM_USE_DEBUG_REGS_HOST
983	jz short gth_debug_regs_no
984	jmp gth_debug_regs_restore
985	gth_debug_regs_no:
986
987	; Restore MSRs
988	mov rbx, rdx
989	mov ecx, MSR_K8_FS_BASE
990	mov eax, [rbx + CPUM.Host.FSbase]
991	mov edx, [rbx + CPUM.Host.FSbase + 4]
992	wrmsr
993	mov ecx, MSR_K8_GS_BASE
994	mov eax, [rbx + CPUM.Host.GSbase]
995	mov edx, [rbx + CPUM.Host.GSbase + 4]
996	wrmsr
997	mov ecx, MSR_K6_EFER
998	mov eax, [rbx + CPUM.Host.efer]
999	mov edx, [rbx + CPUM.Host.efer + 4]
1000	wrmsr
1001	mov rdx, rbx
1002
1003
1004	; restore general registers.
1005	mov eax, edi ; restore return code. eax = return code !!
1006	; mov rax, [rdx + CPUM.Host.rax] - scratch + return code
1007	mov rbx, [rdx + CPUM.Host.rbx]
1008	; mov rcx, [rdx + CPUM.Host.rcx] - scratch
1009	; mov rdx, [rdx + CPUM.Host.rdx] - scratch
1010	mov rdi, [rdx + CPUM.Host.rdi]
1011	mov rsi, [rdx + CPUM.Host.rsi]
1012	mov rsp, [rdx + CPUM.Host.rsp]
1013	mov rbp, [rdx + CPUM.Host.rbp]
1014	; mov r8, [rdx + CPUM.Host.r8 ] - scratch
1015	; mov r9, [rdx + CPUM.Host.r9 ] - scratch
1016	mov r10, [rdx + CPUM.Host.r10]
1017	mov r11, [rdx + CPUM.Host.r11]
1018	mov r12, [rdx + CPUM.Host.r12]
1019	mov r13, [rdx + CPUM.Host.r13]
1020	mov r14, [rdx + CPUM.Host.r14]
1021	mov r15, [rdx + CPUM.Host.r15]
1022
1023	; finally restore flags. (probably not required)
1024	push qword [rdx + CPUM.Host.rflags]
1025	popf
1026
1027
1028	%ifdef DEBUG_STUFF
1029	COM64_S_CHAR '4'
1030	%endif
1031	db 048h
1032	retf
1033
1034	;;
1035	; Detour for restoring the host debug registers.
1036	; edx and edi must be preserved.
1037	gth_debug_regs_restore:
1038	DEBUG_S_CHAR('d')
1039	xor eax, eax
1040	mov dr7, rax ; paranoia or not?
1041	test esi, CPUM_USE_DEBUG_REGS
1042	jz short gth_debug_regs_dr7
1043	DEBUG_S_CHAR('r')
1044	mov rax, [rdx + CPUM.Host.dr0]
1045	mov dr0, rax
1046	mov rbx, [rdx + CPUM.Host.dr1]
1047	mov dr1, rbx
1048	mov rcx, [rdx + CPUM.Host.dr2]
1049	mov dr2, rcx
1050	mov rax, [rdx + CPUM.Host.dr3]
1051	mov dr3, rax
1052	gth_debug_regs_dr7:
1053	mov rbx, [rdx + CPUM.Host.dr6]
1054	mov dr6, rbx
1055	mov rcx, [rdx + CPUM.Host.dr7]
1056	mov dr7, rcx
1057	jmp gth_debug_regs_no
1058
1059	ENDPROC VMMGCGuestToHostAsm
1060
1061
1062	GLOBALNAME End
1063	;
1064	; The description string (in the text section).
1065	;
1066	NAME(Description):
1067	db "AMD64 to/from PAE", 0
1068
1069	extern NAME(Relocate)
1070
1071	;
1072	; End the fixup records.
1073	;
1074	BEGINDATA
1075	db FIX_THE_END ; final entry.
1076	GLOBALNAME FixupsEnd
1077
1078	;;
1079	; The switcher definition structure.
1080	ALIGNDATA(16)
1081	GLOBALNAME Def
1082	istruc VMMSWITCHERDEF
1083	at VMMSWITCHERDEF.pvCode, RTCCPTR_DEF NAME(Start)
1084	at VMMSWITCHERDEF.pvFixups, RTCCPTR_DEF NAME(Fixups)
1085	at VMMSWITCHERDEF.pszDesc, RTCCPTR_DEF NAME(Description)
1086	at VMMSWITCHERDEF.pfnRelocate, RTCCPTR_DEF NAME(Relocate)
1087	at VMMSWITCHERDEF.enmType, dd VMMSWITCHER_AMD64_TO_PAE
1088	at VMMSWITCHERDEF.cbCode, dd NAME(End) - NAME(Start)
1089	at VMMSWITCHERDEF.offR0HostToGuest, dd NAME(vmmR0HostToGuest) - NAME(Start)
1090	at VMMSWITCHERDEF.offGCGuestToHost, dd NAME(vmmGCGuestToHost) - NAME(Start)
1091	at VMMSWITCHERDEF.offGCCallTrampoline, dd NAME(vmmGCCallTrampoline) - NAME(Start)
1092	at VMMSWITCHERDEF.offGCGuestToHostAsm, dd NAME(VMMGCGuestToHostAsm) - NAME(Start)
1093	at VMMSWITCHERDEF.offGCGuestToHostAsmHyperCtx, dd NAME(VMMGCGuestToHostAsmHyperCtx)- NAME(Start)
1094	at VMMSWITCHERDEF.offGCGuestToHostAsmGuestCtx, dd NAME(VMMGCGuestToHostAsmGuestCtx)- NAME(Start)
1095	; disasm help
1096	at VMMSWITCHERDEF.offHCCode0, dd 0
1097	at VMMSWITCHERDEF.cbHCCode0, dd NAME(IDEnterTarget) - NAME(Start)
1098	at VMMSWITCHERDEF.offHCCode1, dd NAME(HCExitTarget) - NAME(Start)
1099	at VMMSWITCHERDEF.cbHCCode1, dd NAME(End) - NAME(HCExitTarget)
1100	at VMMSWITCHERDEF.offIDCode0, dd NAME(IDEnterTarget) - NAME(Start)
1101	at VMMSWITCHERDEF.cbIDCode0, dd NAME(JmpGCTarget) - NAME(IDEnterTarget)
1102	at VMMSWITCHERDEF.offIDCode1, dd NAME(IDExitTarget) - NAME(Start)
1103	at VMMSWITCHERDEF.cbIDCode1, dd NAME(HCExitTarget) - NAME(IDExitTarget)
1104	at VMMSWITCHERDEF.offGCCode, dd NAME(JmpGCTarget) - NAME(Start)
1105	at VMMSWITCHERDEF.cbGCCode, dd NAME(IDExitTarget) - NAME(JmpGCTarget)
1106
1107	iend
1108

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source: vbox/trunk/src/VBox/VMM/VMMSwitcher/AMD64ToPAE.asm@ 2705

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