| 1 | ; VMM - World Switchers, 32Bit to AMD64.
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| 2 | ;
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| 3 |
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| 4 | ;
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| 5 | ; Copyright (C) 2006-2012 Oracle Corporation
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| 6 | ;
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| 7 | ; This file is part of VirtualBox Open Source Edition (OSE), as
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| 8 | ; available from http://www.virtualbox.org. This file is free software;
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| 9 | ; you can redistribute it and/or modify it under the terms of the GNU
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| 10 | ; General Public License (GPL) as published by the Free Software
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| 11 | ; Foundation, in version 2 as it comes in the "COPYING" file of the
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| 12 | ; VirtualBox OSE distribution. VirtualBox OSE is distributed in the
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| 13 | ; hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
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| 14 | ;
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| 15 |
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| 16 | ;%define DEBUG_STUFF 1
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| 17 | ;%define STRICT_IF 1
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| 18 |
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| 19 | ;*******************************************************************************
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| 20 | ;* Defined Constants And Macros *
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| 21 | ;*******************************************************************************
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| 22 |
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| 23 |
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| 24 | ;*******************************************************************************
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| 25 | ;* Header Files *
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| 26 | ;*******************************************************************************
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| 27 | %include "VBox/asmdefs.mac"
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| 28 | %include "VBox/apic.mac"
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| 29 | %include "iprt/x86.mac"
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| 30 | %include "VBox/vmm/cpum.mac"
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| 31 | %include "VBox/vmm/stam.mac"
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| 32 | %include "VBox/vmm/vm.mac"
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| 33 | %include "CPUMInternal.mac"
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| 34 | %include "VMMSwitcher.mac"
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| 35 |
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| 36 |
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| 37 | ;
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| 38 | ; Start the fixup records
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| 39 | ; We collect the fixups in the .data section as we go along
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| 40 | ; It is therefore VITAL that no-one is using the .data section
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| 41 | ; for anything else between 'Start' and 'End'.
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| 42 | ;
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| 43 | BEGINDATA
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| 44 | GLOBALNAME Fixups
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| 45 |
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| 46 |
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| 47 |
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| 48 | BEGINCODE
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| 49 | GLOBALNAME Start
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| 50 |
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| 51 | BITS 32
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| 52 |
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| 53 | ;;
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| 54 | ; The C interface.
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| 55 | ; @param [esp + 04h] Param 1 - VM handle
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| 56 | ; @param [esp + 08h] Param 2 - VMCPU offset
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| 57 | ;
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| 58 | BEGINPROC vmmR0ToRawMode
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| 59 | %ifdef DEBUG_STUFF
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| 60 | COM32_S_NEWLINE
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| 61 | COM32_S_CHAR '^'
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| 62 | %endif
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| 63 |
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| 64 | %ifdef VBOX_WITH_STATISTICS
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| 65 | ;
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| 66 | ; Switcher stats.
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| 67 | ;
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| 68 | FIXUP FIX_HC_VM_OFF, 1, VM.StatSwitcherToGC
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| 69 | mov edx, 0ffffffffh
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| 70 | STAM_PROFILE_ADV_START edx
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| 71 | %endif
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| 72 |
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| 73 | push ebp
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| 74 | mov ebp, [esp + 12] ; VMCPU offset
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| 75 |
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| 76 | ; turn off interrupts
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| 77 | pushf
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| 78 | cli
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| 79 |
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| 80 | ;
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| 81 | ; Call worker.
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| 82 | ;
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| 83 | FIXUP FIX_HC_CPUM_OFF, 1, 0
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| 84 | mov edx, 0ffffffffh
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| 85 | push cs ; allow for far return and restore cs correctly.
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| 86 | call NAME(vmmR0ToRawModeAsm)
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| 87 |
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| 88 | %ifdef VBOX_WITH_VMMR0_DISABLE_LAPIC_NMI
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| 89 | CPUM_FROM_CPUMCPU(edx)
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| 90 | ; Restore blocked Local APIC NMI vectors
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| 91 | mov ecx, [edx + CPUM.fApicDisVectors]
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| 92 | mov edx, [edx + CPUM.pvApicBase]
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| 93 | shr ecx, 1
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| 94 | jnc gth_nolint0
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| 95 | and dword [edx + APIC_REG_LVT_LINT0], ~APIC_REG_LVT_MASKED
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| 96 | gth_nolint0:
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| 97 | shr ecx, 1
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| 98 | jnc gth_nolint1
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| 99 | and dword [edx + APIC_REG_LVT_LINT1], ~APIC_REG_LVT_MASKED
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| 100 | gth_nolint1:
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| 101 | shr ecx, 1
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| 102 | jnc gth_nopc
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| 103 | and dword [edx + APIC_REG_LVT_PC], ~APIC_REG_LVT_MASKED
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| 104 | gth_nopc:
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| 105 | shr ecx, 1
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| 106 | jnc gth_notherm
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| 107 | and dword [edx + APIC_REG_LVT_THMR], ~APIC_REG_LVT_MASKED
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| 108 | gth_notherm:
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| 109 | %endif
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| 110 |
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| 111 | ; restore original flags
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| 112 | popf
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| 113 | pop ebp
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| 114 |
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| 115 | %ifdef VBOX_WITH_STATISTICS
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| 116 | ;
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| 117 | ; Switcher stats.
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| 118 | ;
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| 119 | FIXUP FIX_HC_VM_OFF, 1, VM.StatSwitcherToHC
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| 120 | mov edx, 0ffffffffh
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| 121 | STAM_PROFILE_ADV_STOP edx
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| 122 | %endif
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| 123 |
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| 124 | ret
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| 125 |
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| 126 | ENDPROC vmmR0ToRawMode
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| 127 |
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| 128 | ; *****************************************************************************
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| 129 | ; vmmR0ToRawModeAsm
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| 130 | ;
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| 131 | ; Phase one of the switch from host to guest context (host MMU context)
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| 132 | ;
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| 133 | ; INPUT:
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| 134 | ; - edx virtual address of CPUM structure (valid in host context)
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| 135 | ; - ebp offset of the CPUMCPU structure
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| 136 | ;
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| 137 | ; USES/DESTROYS:
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| 138 | ; - eax, ecx, edx, esi
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| 139 | ;
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| 140 | ; ASSUMPTION:
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| 141 | ; - current CS and DS selectors are wide open
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| 142 | ;
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| 143 | ; *****************************************************************************
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| 144 | ALIGNCODE(16)
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| 145 | BEGINPROC vmmR0ToRawModeAsm
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| 146 | ;;
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| 147 | ;; Save CPU host context
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| 148 | ;; Skip eax, edx and ecx as these are not preserved over calls.
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| 149 | ;;
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| 150 | CPUMCPU_FROM_CPUM_WITH_OFFSET edx, ebp
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| 151 | %ifdef VBOX_WITH_CRASHDUMP_MAGIC
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| 152 | ; phys address of scratch page
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| 153 | mov eax, dword [edx + CPUMCPU.Guest.dr + 4*8]
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| 154 | mov cr2, eax
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| 155 |
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| 156 | mov dword [edx + CPUMCPU.Guest.dr + 4*8], 1
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| 157 | %endif
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| 158 |
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| 159 | ; general registers.
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| 160 | mov [edx + CPUMCPU.Host.ebx], ebx
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| 161 | mov [edx + CPUMCPU.Host.edi], edi
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| 162 | mov [edx + CPUMCPU.Host.esi], esi
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| 163 | mov [edx + CPUMCPU.Host.esp], esp
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| 164 | mov [edx + CPUMCPU.Host.ebp], ebp
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| 165 | ; selectors.
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| 166 | mov [edx + CPUMCPU.Host.ds], ds
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| 167 | mov [edx + CPUMCPU.Host.es], es
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| 168 | mov [edx + CPUMCPU.Host.fs], fs
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| 169 | mov [edx + CPUMCPU.Host.gs], gs
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| 170 | mov [edx + CPUMCPU.Host.ss], ss
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| 171 | ; special registers.
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| 172 | sldt [edx + CPUMCPU.Host.ldtr]
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| 173 | sidt [edx + CPUMCPU.Host.idtr]
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| 174 | sgdt [edx + CPUMCPU.Host.gdtr]
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| 175 | str [edx + CPUMCPU.Host.tr]
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| 176 |
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| 177 | %ifdef VBOX_WITH_CRASHDUMP_MAGIC
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| 178 | mov dword [edx + CPUMCPU.Guest.dr + 4*8], 2
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| 179 | %endif
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| 180 |
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| 181 | %ifdef VBOX_WITH_VMMR0_DISABLE_LAPIC_NMI
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| 182 | CPUM_FROM_CPUMCPU_WITH_OFFSET edx, ebp
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| 183 | mov ebx, [edx + CPUM.pvApicBase]
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| 184 | or ebx, ebx
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| 185 | jz htg_noapic
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| 186 | mov eax, [ebx + APIC_REG_LVT_LINT0]
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| 187 | mov ecx, eax
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| 188 | and ecx, (APIC_REG_LVT_MASKED | APIC_REG_LVT_MODE_MASK)
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| 189 | cmp ecx, APIC_REG_LVT_MODE_NMI
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| 190 | jne htg_nolint0
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| 191 | or edi, 0x01
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| 192 | or eax, APIC_REG_LVT_MASKED
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| 193 | mov [ebx + APIC_REG_LVT_LINT0], eax
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| 194 | mov eax, [ebx + APIC_REG_LVT_LINT0] ; write completion
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| 195 | htg_nolint0:
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| 196 | mov eax, [ebx + APIC_REG_LVT_LINT1]
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| 197 | mov ecx, eax
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| 198 | and ecx, (APIC_REG_LVT_MASKED | APIC_REG_LVT_MODE_MASK)
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| 199 | cmp ecx, APIC_REG_LVT_MODE_NMI
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| 200 | jne htg_nolint1
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| 201 | or edi, 0x02
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| 202 | or eax, APIC_REG_LVT_MASKED
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| 203 | mov [ebx + APIC_REG_LVT_LINT1], eax
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| 204 | mov eax, [ebx + APIC_REG_LVT_LINT1] ; write completion
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| 205 | htg_nolint1:
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| 206 | mov eax, [ebx + APIC_REG_LVT_PC]
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| 207 | mov ecx, eax
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| 208 | and ecx, (APIC_REG_LVT_MASKED | APIC_REG_LVT_MODE_MASK)
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| 209 | cmp ecx, APIC_REG_LVT_MODE_NMI
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| 210 | jne htg_nopc
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| 211 | or edi, 0x04
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| 212 | or eax, APIC_REG_LVT_MASKED
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| 213 | mov [ebx + APIC_REG_LVT_PC], eax
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| 214 | mov eax, [ebx + APIC_REG_LVT_PC] ; write completion
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| 215 | htg_nopc:
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| 216 | mov eax, [ebx + APIC_REG_VERSION]
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| 217 | shr eax, 16
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| 218 | cmp al, 5
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| 219 | jb htg_notherm
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| 220 | mov eax, [ebx + APIC_REG_LVT_THMR]
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| 221 | mov ecx, eax
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| 222 | and ecx, (APIC_REG_LVT_MASKED | APIC_REG_LVT_MODE_MASK)
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| 223 | cmp ecx, APIC_REG_LVT_MODE_NMI
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| 224 | jne htg_notherm
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| 225 | or edi, 0x08
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| 226 | or eax, APIC_REG_LVT_MASKED
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| 227 | mov [ebx + APIC_REG_LVT_THMR], eax
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| 228 | mov eax, [ebx + APIC_REG_LVT_THMR] ; write completion
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| 229 | htg_notherm:
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| 230 | mov [edx + CPUM.fApicDisVectors], edi
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| 231 | htg_noapic:
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| 232 | CPUMCPU_FROM_CPUM_WITH_OFFSET edx, ebp
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| 233 | %endif
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| 234 |
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| 235 | ; control registers.
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| 236 | mov eax, cr0
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| 237 | mov [edx + CPUMCPU.Host.cr0], eax
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| 238 | ;Skip cr2; assume host os don't stuff things in cr2. (safe)
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| 239 | mov eax, cr3
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| 240 | mov [edx + CPUMCPU.Host.cr3], eax
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| 241 | mov eax, cr4
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| 242 | mov [edx + CPUMCPU.Host.cr4], eax
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| 243 |
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| 244 | ; save the host EFER msr
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| 245 | mov ebx, edx
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| 246 | mov ecx, MSR_K6_EFER
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| 247 | rdmsr
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| 248 | mov [ebx + CPUMCPU.Host.efer], eax
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| 249 | mov [ebx + CPUMCPU.Host.efer + 4], edx
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| 250 | mov edx, ebx
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| 251 |
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| 252 | %ifdef VBOX_WITH_CRASHDUMP_MAGIC
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| 253 | mov dword [edx + CPUMCPU.Guest.dr + 4*8], 3
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| 254 | %endif
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| 255 |
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| 256 | ; Load new gdt so we can do a far jump after going into 64 bits mode
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| 257 | lgdt [edx + CPUMCPU.Hyper.gdtr]
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| 258 |
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| 259 | %ifdef VBOX_WITH_CRASHDUMP_MAGIC
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| 260 | mov dword [edx + CPUMCPU.Guest.dr + 4*8], 4
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| 261 | %endif
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| 262 |
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| 263 | ;;
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| 264 | ;; Load Intermediate memory context.
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| 265 | ;;
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| 266 | FIXUP SWITCHER_FIX_INTER_CR3_HC, 1
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| 267 | mov eax, 0ffffffffh
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| 268 | mov cr3, eax
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| 269 | DEBUG_CHAR('?')
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| 270 |
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| 271 | ;;
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| 272 | ;; Jump to identity mapped location
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| 273 | ;;
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| 274 | FIXUP FIX_HC_2_ID_NEAR_REL, 1, NAME(IDEnterTarget) - NAME(Start)
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| 275 | jmp near NAME(IDEnterTarget)
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| 276 |
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| 277 |
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| 278 | ; We're now on identity mapped pages!
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| 279 | ALIGNCODE(16)
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| 280 | GLOBALNAME IDEnterTarget
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| 281 | DEBUG_CHAR('2')
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| 282 |
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| 283 | ; 1. Disable paging.
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| 284 | mov ebx, cr0
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| 285 | and ebx, ~X86_CR0_PG
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| 286 | mov cr0, ebx
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| 287 | DEBUG_CHAR('2')
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| 288 |
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| 289 | %ifdef VBOX_WITH_CRASHDUMP_MAGIC
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| 290 | mov eax, cr2
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| 291 | mov dword [eax], 3
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| 292 | %endif
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| 293 |
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| 294 | ; 2. Enable PAE.
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| 295 | mov ecx, cr4
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| 296 | or ecx, X86_CR4_PAE
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| 297 | mov cr4, ecx
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| 298 |
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| 299 | ; 3. Load long mode intermediate CR3.
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| 300 | FIXUP FIX_INTER_AMD64_CR3, 1
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| 301 | mov ecx, 0ffffffffh
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| 302 | mov cr3, ecx
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| 303 | DEBUG_CHAR('3')
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| 304 |
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| 305 | %ifdef VBOX_WITH_CRASHDUMP_MAGIC
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| 306 | mov eax, cr2
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| 307 | mov dword [eax], 4
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| 308 | %endif
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| 309 |
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| 310 | ; 4. Enable long mode.
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| 311 | mov esi, edx
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| 312 | mov ecx, MSR_K6_EFER
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| 313 | rdmsr
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| 314 | FIXUP FIX_EFER_OR_MASK, 1
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| 315 | or eax, 0ffffffffh
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| 316 | and eax, ~(MSR_K6_EFER_FFXSR) ; turn off fast fxsave/fxrstor (skipping xmm regs)
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| 317 | wrmsr
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| 318 | mov edx, esi
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| 319 | DEBUG_CHAR('4')
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| 320 |
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| 321 | %ifdef VBOX_WITH_CRASHDUMP_MAGIC
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| 322 | mov eax, cr2
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| 323 | mov dword [eax], 5
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| 324 | %endif
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| 325 |
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| 326 | ; 5. Enable paging.
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| 327 | or ebx, X86_CR0_PG
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| 328 | ; Disable ring 0 write protection too
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| 329 | and ebx, ~X86_CR0_WRITE_PROTECT
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| 330 | mov cr0, ebx
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| 331 | DEBUG_CHAR('5')
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| 332 |
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| 333 | ; Jump from compatibility mode to 64-bit mode.
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| 334 | FIXUP FIX_ID_FAR32_TO_64BIT_MODE, 1, NAME(IDEnter64Mode) - NAME(Start)
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| 335 | jmp 0ffffh:0fffffffeh
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| 336 |
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| 337 | ;
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| 338 | ; We're in 64-bit mode (ds, ss, es, fs, gs are all bogus).
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| 339 | BITS 64
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| 340 | ALIGNCODE(16)
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| 341 | NAME(IDEnter64Mode):
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| 342 | DEBUG_CHAR('6')
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| 343 | jmp [NAME(pICEnterTarget) wrt rip]
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| 344 |
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| 345 | ; 64-bit jump target
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| 346 | NAME(pICEnterTarget):
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| 347 | FIXUP FIX_HC_64BIT_NOCHECK, 0, NAME(ICEnterTarget) - NAME(Start)
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| 348 | dq 0ffffffffffffffffh
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| 349 |
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| 350 | ; 64-bit pCpum address.
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| 351 | NAME(pCpumIC):
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| 352 | FIXUP FIX_GC_64_BIT_CPUM_OFF, 0, 0
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| 353 | dq 0ffffffffffffffffh
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| 354 |
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| 355 | %ifdef VBOX_WITH_CRASHDUMP_MAGIC
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| 356 | NAME(pMarker):
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| 357 | db 'Switch_marker'
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| 358 | %endif
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| 359 |
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| 360 | ;
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| 361 | ; When we arrive here we're in 64 bits mode in the intermediate context
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| 362 | ;
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| 363 | ALIGNCODE(16)
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| 364 | GLOBALNAME ICEnterTarget
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| 365 | ; Load CPUM pointer into rdx
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| 366 | mov rdx, [NAME(pCpumIC) wrt rip]
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| 367 | CPUMCPU_FROM_CPUM_WITH_OFFSET edx, ebp
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| 368 |
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| 369 | mov rax, cs
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| 370 | mov ds, rax
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| 371 | mov es, rax
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| 372 |
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| 373 | ; Invalidate fs & gs
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| 374 | mov rax, 0
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| 375 | mov fs, rax
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| 376 | mov gs, rax
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| 377 |
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| 378 | %ifdef VBOX_WITH_CRASHDUMP_MAGIC
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| 379 | mov dword [rdx + CPUMCPU.Guest.dr + 4*8], 5
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| 380 | %endif
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| 381 |
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| 382 | ; Setup stack.
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| 383 | DEBUG_CHAR('7')
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| 384 | mov rsp, 0
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| 385 | mov eax, [rdx + CPUMCPU.Hyper.ss.Sel]
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| 386 | mov ss, ax
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| 387 | mov esp, [rdx + CPUMCPU.Hyper.esp]
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| 388 |
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| 389 | %ifdef VBOX_WITH_CRASHDUMP_MAGIC
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| 390 | mov dword [rdx + CPUMCPU.Guest.dr + 4*8], 6
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| 391 | %endif
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| 392 |
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| 393 |
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| 394 | ; load the hypervisor function address
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| 395 | mov r9, [rdx + CPUMCPU.Hyper.eip]
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| 396 |
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| 397 | ; Check if we need to restore the guest FPU state
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| 398 | mov esi, [rdx + CPUMCPU.fUseFlags] ; esi == use flags.
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| 399 | test esi, CPUM_SYNC_FPU_STATE
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| 400 | jz near gth_fpu_no
|
|---|
| 401 |
|
|---|
| 402 | %ifdef VBOX_WITH_CRASHDUMP_MAGIC
|
|---|
| 403 | mov dword [rdx + CPUMCPU.Guest.dr + 4*8], 7
|
|---|
| 404 | %endif
|
|---|
| 405 |
|
|---|
| 406 | mov rax, cr0
|
|---|
| 407 | mov rcx, rax ; save old CR0
|
|---|
| 408 | and rax, ~(X86_CR0_TS | X86_CR0_EM)
|
|---|
| 409 | mov cr0, rax
|
|---|
| 410 | fxrstor [rdx + CPUMCPU.Guest.fpu]
|
|---|
| 411 | mov cr0, rcx ; and restore old CR0 again
|
|---|
| 412 |
|
|---|
| 413 | and dword [rdx + CPUMCPU.fUseFlags], ~CPUM_SYNC_FPU_STATE
|
|---|
| 414 |
|
|---|
| 415 | gth_fpu_no:
|
|---|
| 416 | ; Check if we need to restore the guest debug state
|
|---|
| 417 | test esi, CPUM_SYNC_DEBUG_STATE
|
|---|
| 418 | jz near gth_debug_no
|
|---|
| 419 |
|
|---|
| 420 | %ifdef VBOX_WITH_CRASHDUMP_MAGIC
|
|---|
| 421 | mov dword [rdx + CPUMCPU.Guest.dr + 4*8], 8
|
|---|
| 422 | %endif
|
|---|
| 423 |
|
|---|
| 424 | mov rax, qword [rdx + CPUMCPU.Guest.dr + 0*8]
|
|---|
| 425 | mov dr0, rax
|
|---|
| 426 | mov rax, qword [rdx + CPUMCPU.Guest.dr + 1*8]
|
|---|
| 427 | mov dr1, rax
|
|---|
| 428 | mov rax, qword [rdx + CPUMCPU.Guest.dr + 2*8]
|
|---|
| 429 | mov dr2, rax
|
|---|
| 430 | mov rax, qword [rdx + CPUMCPU.Guest.dr + 3*8]
|
|---|
| 431 | mov dr3, rax
|
|---|
| 432 | mov rax, qword [rdx + CPUMCPU.Guest.dr + 6*8]
|
|---|
| 433 | mov dr6, rax ; not required for AMD-V
|
|---|
| 434 |
|
|---|
| 435 | and dword [rdx + CPUMCPU.fUseFlags], ~CPUM_SYNC_DEBUG_STATE
|
|---|
| 436 |
|
|---|
| 437 | gth_debug_no:
|
|---|
| 438 |
|
|---|
| 439 | %ifdef VBOX_WITH_CRASHDUMP_MAGIC
|
|---|
| 440 | mov dword [rdx + CPUMCPU.Guest.dr + 4*8], 9
|
|---|
| 441 | %endif
|
|---|
| 442 |
|
|---|
| 443 | ; parameter for all helper functions (pCtx)
|
|---|
| 444 | lea rsi, [rdx + CPUMCPU.Guest.fpu]
|
|---|
| 445 | call r9
|
|---|
| 446 |
|
|---|
| 447 | ; Load CPUM pointer into rdx
|
|---|
| 448 | mov rdx, [NAME(pCpumIC) wrt rip]
|
|---|
| 449 | CPUMCPU_FROM_CPUM_WITH_OFFSET edx, ebp
|
|---|
| 450 |
|
|---|
| 451 | %ifdef VBOX_WITH_CRASHDUMP_MAGIC
|
|---|
| 452 | mov dword [rdx + CPUMCPU.Guest.dr + 4*8], 10
|
|---|
| 453 | %endif
|
|---|
| 454 |
|
|---|
| 455 | ; Save the return code
|
|---|
| 456 | mov dword [rdx + CPUMCPU.u32RetCode], eax
|
|---|
| 457 |
|
|---|
| 458 | ; now let's switch back
|
|---|
| 459 | jmp NAME(vmmRCToHostAsm) ; rax = returncode.
|
|---|
| 460 |
|
|---|
| 461 | ENDPROC vmmR0ToRawModeAsm
|
|---|
| 462 |
|
|---|
| 463 |
|
|---|
| 464 | ;;
|
|---|
| 465 | ; Trampoline for doing a call when starting the hyper visor execution.
|
|---|
| 466 | ;
|
|---|
| 467 | ; Push any arguments to the routine.
|
|---|
| 468 | ; Push the argument frame size (cArg * 4).
|
|---|
| 469 | ; Push the call target (_cdecl convention).
|
|---|
| 470 | ; Push the address of this routine.
|
|---|
| 471 | ;
|
|---|
| 472 | ;
|
|---|
| 473 | BITS 64
|
|---|
| 474 | ALIGNCODE(16)
|
|---|
| 475 | BEGINPROC vmmRCCallTrampoline
|
|---|
| 476 | %ifdef DEBUG_STUFF
|
|---|
| 477 | COM64_S_CHAR 'c'
|
|---|
| 478 | COM64_S_CHAR 't'
|
|---|
| 479 | COM64_S_CHAR '!'
|
|---|
| 480 | %endif
|
|---|
| 481 | int3
|
|---|
| 482 | ENDPROC vmmRCCallTrampoline
|
|---|
| 483 |
|
|---|
| 484 |
|
|---|
| 485 | ;;
|
|---|
| 486 | ; The C interface.
|
|---|
| 487 | ;
|
|---|
| 488 | BITS 64
|
|---|
| 489 | ALIGNCODE(16)
|
|---|
| 490 | BEGINPROC vmmRCToHost
|
|---|
| 491 | %ifdef DEBUG_STUFF
|
|---|
| 492 | push rsi
|
|---|
| 493 | COM_NEWLINE
|
|---|
| 494 | DEBUG_CHAR('b')
|
|---|
| 495 | DEBUG_CHAR('a')
|
|---|
| 496 | DEBUG_CHAR('c')
|
|---|
| 497 | DEBUG_CHAR('k')
|
|---|
| 498 | DEBUG_CHAR('!')
|
|---|
| 499 | COM_NEWLINE
|
|---|
| 500 | pop rsi
|
|---|
| 501 | %endif
|
|---|
| 502 | int3
|
|---|
| 503 | ENDPROC vmmRCToHost
|
|---|
| 504 |
|
|---|
| 505 | ;;
|
|---|
| 506 | ; vmmRCToHostAsm
|
|---|
| 507 | ;
|
|---|
| 508 | ; This is an alternative entry point which we'll be using
|
|---|
| 509 | ; when the we have saved the guest state already or we haven't
|
|---|
| 510 | ; been messing with the guest at all.
|
|---|
| 511 | ;
|
|---|
| 512 | ; @param eax Return code.
|
|---|
| 513 | ; @uses eax, edx, ecx (or it may use them in the future)
|
|---|
| 514 | ;
|
|---|
| 515 | BITS 64
|
|---|
| 516 | ALIGNCODE(16)
|
|---|
| 517 | BEGINPROC vmmRCToHostAsm
|
|---|
| 518 | NAME(vmmRCToHostAsmNoReturn):
|
|---|
| 519 | ;; We're still in the intermediate memory context!
|
|---|
| 520 |
|
|---|
| 521 | ;;
|
|---|
| 522 | ;; Switch to compatibility mode, placing ourselves in identity mapped code.
|
|---|
| 523 | ;;
|
|---|
| 524 | jmp far [NAME(fpIDEnterTarget) wrt rip]
|
|---|
| 525 |
|
|---|
| 526 | ; 16:32 Pointer to IDEnterTarget.
|
|---|
| 527 | NAME(fpIDEnterTarget):
|
|---|
| 528 | FIXUP FIX_ID_32BIT, 0, NAME(IDExitTarget) - NAME(Start)
|
|---|
| 529 | dd 0
|
|---|
| 530 | FIXUP FIX_HYPER_CS, 0
|
|---|
| 531 | dd 0
|
|---|
| 532 |
|
|---|
| 533 | ; We're now on identity mapped pages!
|
|---|
| 534 | ALIGNCODE(16)
|
|---|
| 535 | GLOBALNAME IDExitTarget
|
|---|
| 536 | BITS 32
|
|---|
| 537 | DEBUG_CHAR('1')
|
|---|
| 538 |
|
|---|
| 539 | ; 1. Deactivate long mode by turning off paging.
|
|---|
| 540 | mov ebx, cr0
|
|---|
| 541 | and ebx, ~X86_CR0_PG
|
|---|
| 542 | mov cr0, ebx
|
|---|
| 543 | DEBUG_CHAR('2')
|
|---|
| 544 |
|
|---|
| 545 | ; 2. Load intermediate page table.
|
|---|
| 546 | FIXUP SWITCHER_FIX_INTER_CR3_HC, 1
|
|---|
| 547 | mov edx, 0ffffffffh
|
|---|
| 548 | mov cr3, edx
|
|---|
| 549 | DEBUG_CHAR('3')
|
|---|
| 550 |
|
|---|
| 551 | ; 3. Disable long mode.
|
|---|
| 552 | mov ecx, MSR_K6_EFER
|
|---|
| 553 | rdmsr
|
|---|
| 554 | DEBUG_CHAR('5')
|
|---|
| 555 | and eax, ~(MSR_K6_EFER_LME)
|
|---|
| 556 | wrmsr
|
|---|
| 557 | DEBUG_CHAR('6')
|
|---|
| 558 |
|
|---|
| 559 | %ifndef NEED_PAE_ON_HOST
|
|---|
| 560 | ; 3b. Disable PAE.
|
|---|
| 561 | mov eax, cr4
|
|---|
| 562 | and eax, ~X86_CR4_PAE
|
|---|
| 563 | mov cr4, eax
|
|---|
| 564 | DEBUG_CHAR('7')
|
|---|
| 565 | %endif
|
|---|
| 566 |
|
|---|
| 567 | ; 4. Enable paging.
|
|---|
| 568 | or ebx, X86_CR0_PG
|
|---|
| 569 | mov cr0, ebx
|
|---|
| 570 | jmp short just_a_jump
|
|---|
| 571 | just_a_jump:
|
|---|
| 572 | DEBUG_CHAR('8')
|
|---|
| 573 |
|
|---|
| 574 | ;;
|
|---|
| 575 | ;; 5. Jump to guest code mapping of the code and load the Hypervisor CS.
|
|---|
| 576 | ;;
|
|---|
| 577 | FIXUP FIX_ID_2_HC_NEAR_REL, 1, NAME(ICExitTarget) - NAME(Start)
|
|---|
| 578 | jmp near NAME(ICExitTarget)
|
|---|
| 579 |
|
|---|
| 580 | ;;
|
|---|
| 581 | ;; When we arrive at this label we're at the
|
|---|
| 582 | ;; intermediate mapping of the switching code.
|
|---|
| 583 | ;;
|
|---|
| 584 | BITS 32
|
|---|
| 585 | ALIGNCODE(16)
|
|---|
| 586 | GLOBALNAME ICExitTarget
|
|---|
| 587 | DEBUG_CHAR('8')
|
|---|
| 588 |
|
|---|
| 589 | ; load the hypervisor data selector into ds & es
|
|---|
| 590 | FIXUP FIX_HYPER_DS, 1
|
|---|
| 591 | mov eax, 0ffffh
|
|---|
| 592 | mov ds, eax
|
|---|
| 593 | mov es, eax
|
|---|
| 594 |
|
|---|
| 595 | FIXUP FIX_GC_CPUM_OFF, 1, 0
|
|---|
| 596 | mov edx, 0ffffffffh
|
|---|
| 597 | CPUMCPU_FROM_CPUM_WITH_OFFSET edx, ebp
|
|---|
| 598 | mov esi, [edx + CPUMCPU.Host.cr3]
|
|---|
| 599 | mov cr3, esi
|
|---|
| 600 |
|
|---|
| 601 | ;; now we're in host memory context, let's restore regs
|
|---|
| 602 | FIXUP FIX_HC_CPUM_OFF, 1, 0
|
|---|
| 603 | mov edx, 0ffffffffh
|
|---|
| 604 | CPUMCPU_FROM_CPUM_WITH_OFFSET edx, ebp
|
|---|
| 605 |
|
|---|
| 606 | ; restore the host EFER
|
|---|
| 607 | mov ebx, edx
|
|---|
| 608 | mov ecx, MSR_K6_EFER
|
|---|
| 609 | mov eax, [ebx + CPUMCPU.Host.efer]
|
|---|
| 610 | mov edx, [ebx + CPUMCPU.Host.efer + 4]
|
|---|
| 611 | wrmsr
|
|---|
| 612 | mov edx, ebx
|
|---|
| 613 |
|
|---|
| 614 | ; activate host gdt and idt
|
|---|
| 615 | lgdt [edx + CPUMCPU.Host.gdtr]
|
|---|
| 616 | DEBUG_CHAR('0')
|
|---|
| 617 | lidt [edx + CPUMCPU.Host.idtr]
|
|---|
| 618 | DEBUG_CHAR('1')
|
|---|
| 619 |
|
|---|
| 620 | ; Restore TSS selector; must mark it as not busy before using ltr (!)
|
|---|
| 621 | ; ASSUME that this is supposed to be 'BUSY'. (saves 20-30 ticks on the T42p)
|
|---|
| 622 | movzx eax, word [edx + CPUMCPU.Host.tr] ; eax <- TR
|
|---|
| 623 | and al, 0F8h ; mask away TI and RPL bits, get descriptor offset.
|
|---|
| 624 | add eax, [edx + CPUMCPU.Host.gdtr + 2] ; eax <- GDTR.address + descriptor offset.
|
|---|
| 625 | and dword [eax + 4], ~0200h ; clear busy flag (2nd type2 bit)
|
|---|
| 626 | ltr word [edx + CPUMCPU.Host.tr]
|
|---|
| 627 |
|
|---|
| 628 | ; activate ldt
|
|---|
| 629 | DEBUG_CHAR('2')
|
|---|
| 630 | lldt [edx + CPUMCPU.Host.ldtr]
|
|---|
| 631 |
|
|---|
| 632 | ; Restore segment registers
|
|---|
| 633 | mov eax, [edx + CPUMCPU.Host.ds]
|
|---|
| 634 | mov ds, eax
|
|---|
| 635 | mov eax, [edx + CPUMCPU.Host.es]
|
|---|
| 636 | mov es, eax
|
|---|
| 637 | mov eax, [edx + CPUMCPU.Host.fs]
|
|---|
| 638 | mov fs, eax
|
|---|
| 639 | mov eax, [edx + CPUMCPU.Host.gs]
|
|---|
| 640 | mov gs, eax
|
|---|
| 641 | ; restore stack
|
|---|
| 642 | lss esp, [edx + CPUMCPU.Host.esp]
|
|---|
| 643 |
|
|---|
| 644 | ; Control registers.
|
|---|
| 645 | mov ecx, [edx + CPUMCPU.Host.cr4]
|
|---|
| 646 | mov cr4, ecx
|
|---|
| 647 | mov ecx, [edx + CPUMCPU.Host.cr0]
|
|---|
| 648 | mov cr0, ecx
|
|---|
| 649 | ;mov ecx, [edx + CPUMCPU.Host.cr2] ; assumes this is waste of time.
|
|---|
| 650 | ;mov cr2, ecx
|
|---|
| 651 |
|
|---|
| 652 | ; restore general registers.
|
|---|
| 653 | mov edi, [edx + CPUMCPU.Host.edi]
|
|---|
| 654 | mov esi, [edx + CPUMCPU.Host.esi]
|
|---|
| 655 | mov ebx, [edx + CPUMCPU.Host.ebx]
|
|---|
| 656 | mov ebp, [edx + CPUMCPU.Host.ebp]
|
|---|
| 657 |
|
|---|
| 658 | ; store the return code in eax
|
|---|
| 659 | mov eax, [edx + CPUMCPU.u32RetCode]
|
|---|
| 660 | retf
|
|---|
| 661 | ENDPROC vmmRCToHostAsm
|
|---|
| 662 |
|
|---|
| 663 |
|
|---|
| 664 | GLOBALNAME End
|
|---|
| 665 | ;
|
|---|
| 666 | ; The description string (in the text section).
|
|---|
| 667 | ;
|
|---|
| 668 | NAME(Description):
|
|---|
| 669 | db SWITCHER_DESCRIPTION
|
|---|
| 670 | db 0
|
|---|
| 671 |
|
|---|
| 672 | extern NAME(Relocate)
|
|---|
| 673 |
|
|---|
| 674 | ;
|
|---|
| 675 | ; End the fixup records.
|
|---|
| 676 | ;
|
|---|
| 677 | BEGINDATA
|
|---|
| 678 | db FIX_THE_END ; final entry.
|
|---|
| 679 | GLOBALNAME FixupsEnd
|
|---|
| 680 |
|
|---|
| 681 | ;;
|
|---|
| 682 | ; The switcher definition structure.
|
|---|
| 683 | ALIGNDATA(16)
|
|---|
| 684 | GLOBALNAME Def
|
|---|
| 685 | istruc VMMSWITCHERDEF
|
|---|
| 686 | at VMMSWITCHERDEF.pvCode, RTCCPTR_DEF NAME(Start)
|
|---|
| 687 | at VMMSWITCHERDEF.pvFixups, RTCCPTR_DEF NAME(Fixups)
|
|---|
| 688 | at VMMSWITCHERDEF.pszDesc, RTCCPTR_DEF NAME(Description)
|
|---|
| 689 | at VMMSWITCHERDEF.pfnRelocate, RTCCPTR_DEF NAME(Relocate)
|
|---|
| 690 | at VMMSWITCHERDEF.enmType, dd SWITCHER_TYPE
|
|---|
| 691 | at VMMSWITCHERDEF.cbCode, dd NAME(End) - NAME(Start)
|
|---|
| 692 | at VMMSWITCHERDEF.offR0ToRawMode, dd NAME(vmmR0ToRawMode) - NAME(Start)
|
|---|
| 693 | at VMMSWITCHERDEF.offRCToHost, dd NAME(vmmRCToHost) - NAME(Start)
|
|---|
| 694 | at VMMSWITCHERDEF.offRCCallTrampoline, dd NAME(vmmRCCallTrampoline) - NAME(Start)
|
|---|
| 695 | at VMMSWITCHERDEF.offRCToHostAsm, dd NAME(vmmRCToHostAsm) - NAME(Start)
|
|---|
| 696 | at VMMSWITCHERDEF.offRCToHostAsmNoReturn, dd NAME(vmmRCToHostAsmNoReturn) - NAME(Start)
|
|---|
| 697 | ; disasm help
|
|---|
| 698 | at VMMSWITCHERDEF.offHCCode0, dd 0
|
|---|
| 699 | at VMMSWITCHERDEF.cbHCCode0, dd NAME(IDEnterTarget) - NAME(Start)
|
|---|
| 700 | at VMMSWITCHERDEF.offHCCode1, dd NAME(ICExitTarget) - NAME(Start)
|
|---|
| 701 | at VMMSWITCHERDEF.cbHCCode1, dd NAME(End) - NAME(ICExitTarget)
|
|---|
| 702 | at VMMSWITCHERDEF.offIDCode0, dd NAME(IDEnterTarget) - NAME(Start)
|
|---|
| 703 | at VMMSWITCHERDEF.cbIDCode0, dd NAME(ICEnterTarget) - NAME(IDEnterTarget)
|
|---|
| 704 | at VMMSWITCHERDEF.offIDCode1, dd NAME(IDExitTarget) - NAME(Start)
|
|---|
| 705 | at VMMSWITCHERDEF.cbIDCode1, dd NAME(ICExitTarget) - NAME(Start)
|
|---|
| 706 | at VMMSWITCHERDEF.offGCCode, dd 0
|
|---|
| 707 | at VMMSWITCHERDEF.cbGCCode, dd 0
|
|---|
| 708 |
|
|---|
| 709 | iend
|
|---|
| 710 |
|
|---|
