VirtualBox

source: vbox/trunk/src/VBox/VMM/VMMTests.cpp@ 27866

Last change on this file since 27866 was 26152, checked in by vboxsync, 15 years ago

VMM: pdm.h and @copydoc cleanups.

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1/* $Id: VMMTests.cpp 26152 2010-02-02 16:00:35Z vboxsync $ */
2/** @file
3 * VMM - The Virtual Machine Monitor Core, Tests.
4 */
5
6/*
7 * Copyright (C) 2006-2007 Sun Microsystems, Inc.
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 *
17 * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
18 * Clara, CA 95054 USA or visit http://www.sun.com if you need
19 * additional information or have any questions.
20 */
21
22//#define NO_SUPCALLR0VMM
23
24/*******************************************************************************
25* Header Files *
26*******************************************************************************/
27#define LOG_GROUP LOG_GROUP_VMM
28#include <VBox/vmm.h>
29#include <VBox/pdmapi.h>
30#include <VBox/cpum.h>
31#include <VBox/dbg.h>
32#include <VBox/mm.h>
33#include <VBox/trpm.h>
34#include <VBox/selm.h>
35#include "VMMInternal.h"
36#include <VBox/vm.h>
37#include <VBox/err.h>
38#include <VBox/param.h>
39#include <VBox/x86.h>
40#include <VBox/hwaccm.h>
41
42#include <iprt/assert.h>
43#include <iprt/asm.h>
44#include <iprt/time.h>
45#include <iprt/stream.h>
46#include <iprt/string.h>
47
48
49/**
50 * Performs a testcase.
51 *
52 * @returns return value from the test.
53 * @param pVM The VM handle.
54 * @param enmTestcase The testcase operation to perform.
55 * @param uVariation The testcase variation id.
56 */
57static int vmmR3DoGCTest(PVM pVM, VMMGCOPERATION enmTestcase, unsigned uVariation)
58{
59 PVMCPU pVCpu = &pVM->aCpus[0];
60
61 RTRCPTR RCPtrEP;
62 int rc = PDMR3LdrGetSymbolRC(pVM, VMMGC_MAIN_MODULE_NAME, "VMMGCEntry", &RCPtrEP);
63 if (RT_FAILURE(rc))
64 return rc;
65
66 CPUMHyperSetCtxCore(pVCpu, NULL);
67 memset(pVCpu->vmm.s.pbEMTStackR3, 0xaa, VMM_STACK_SIZE);
68 CPUMSetHyperESP(pVCpu, pVCpu->vmm.s.pbEMTStackBottomRC); /* Clear the stack. */
69 CPUMPushHyper(pVCpu, uVariation);
70 CPUMPushHyper(pVCpu, enmTestcase);
71 CPUMPushHyper(pVCpu, pVM->pVMRC);
72 CPUMPushHyper(pVCpu, 3 * sizeof(RTRCPTR)); /* stack frame size */
73 CPUMPushHyper(pVCpu, RCPtrEP); /* what to call */
74 CPUMSetHyperEIP(pVCpu, pVM->vmm.s.pfnCallTrampolineRC);
75 Assert(CPUMGetHyperCR3(pVCpu) && CPUMGetHyperCR3(pVCpu) == PGMGetHyperCR3(pVCpu));
76 rc = SUPR3CallVMMR0Fast(pVM->pVMR0, VMMR0_DO_RAW_RUN, 0);
77 if (RT_LIKELY(rc == VINF_SUCCESS))
78 rc = pVCpu->vmm.s.iLastGZRc;
79 return rc;
80}
81
82
83/**
84 * Performs a trap test.
85 *
86 * @returns Return value from the trap test.
87 * @param pVM The VM handle.
88 * @param u8Trap The trap number to test.
89 * @param uVariation The testcase variation.
90 * @param rcExpect The expected result.
91 * @param u32Eax The expected eax value.
92 * @param pszFaultEIP The fault address. Pass NULL if this isn't available or doesn't apply.
93 * @param pszDesc The test description.
94 */
95static int vmmR3DoTrapTest(PVM pVM, uint8_t u8Trap, unsigned uVariation, int rcExpect, uint32_t u32Eax, const char *pszFaultEIP, const char *pszDesc)
96{
97 PVMCPU pVCpu = &pVM->aCpus[0];
98
99 RTPrintf("VMM: testing 0%x / %d - %s\n", u8Trap, uVariation, pszDesc);
100
101 RTRCPTR RCPtrEP;
102 int rc = PDMR3LdrGetSymbolRC(pVM, VMMGC_MAIN_MODULE_NAME, "VMMGCEntry", &RCPtrEP);
103 if (RT_FAILURE(rc))
104 return rc;
105
106 CPUMHyperSetCtxCore(pVCpu, NULL);
107 memset(pVCpu->vmm.s.pbEMTStackR3, 0xaa, VMM_STACK_SIZE);
108 CPUMSetHyperESP(pVCpu, pVCpu->vmm.s.pbEMTStackBottomRC); /* Clear the stack. */
109 CPUMPushHyper(pVCpu, uVariation);
110 CPUMPushHyper(pVCpu, u8Trap + VMMGC_DO_TESTCASE_TRAP_FIRST);
111 CPUMPushHyper(pVCpu, pVM->pVMRC);
112 CPUMPushHyper(pVCpu, 3 * sizeof(RTRCPTR)); /* stack frame size */
113 CPUMPushHyper(pVCpu, RCPtrEP); /* what to call */
114 CPUMSetHyperEIP(pVCpu, pVM->vmm.s.pfnCallTrampolineRC);
115 Assert(CPUMGetHyperCR3(pVCpu) && CPUMGetHyperCR3(pVCpu) == PGMGetHyperCR3(pVCpu));
116 rc = SUPR3CallVMMR0Fast(pVM->pVMR0, VMMR0_DO_RAW_RUN, 0);
117 if (RT_LIKELY(rc == VINF_SUCCESS))
118 rc = pVCpu->vmm.s.iLastGZRc;
119 bool fDump = false;
120 if (rc != rcExpect)
121 {
122 RTPrintf("VMM: FAILURE - rc=%Rrc expected %Rrc\n", rc, rcExpect);
123 if (rc != VERR_NOT_IMPLEMENTED)
124 fDump = true;
125 }
126 else if ( rcExpect != VINF_SUCCESS
127 && u8Trap != 8 /* double fault doesn't dare set TrapNo. */
128 && u8Trap != 3 /* guest only, we're not in guest. */
129 && u8Trap != 1 /* guest only, we're not in guest. */
130 && u8Trap != TRPMGetTrapNo(pVCpu))
131 {
132 RTPrintf("VMM: FAILURE - Trap %#x expected %#x\n", TRPMGetTrapNo(pVCpu), u8Trap);
133 fDump = true;
134 }
135 else if (pszFaultEIP)
136 {
137 RTRCPTR RCPtrFault;
138 int rc2 = PDMR3LdrGetSymbolRC(pVM, VMMGC_MAIN_MODULE_NAME, pszFaultEIP, &RCPtrFault);
139 if (RT_FAILURE(rc2))
140 RTPrintf("VMM: FAILURE - Failed to resolve symbol '%s', %Rrc!\n", pszFaultEIP, rc);
141 else if (RCPtrFault != CPUMGetHyperEIP(pVCpu))
142 {
143 RTPrintf("VMM: FAILURE - EIP=%08RX32 expected %RRv (%s)\n", CPUMGetHyperEIP(pVCpu), RCPtrFault, pszFaultEIP);
144 fDump = true;
145 }
146 }
147 else if (rcExpect != VINF_SUCCESS)
148 {
149 if (CPUMGetHyperSS(pVCpu) == SELMGetHyperDS(pVM))
150 RTPrintf("VMM: FAILURE - ss=%x expected %x\n", CPUMGetHyperSS(pVCpu), SELMGetHyperDS(pVM));
151 if (CPUMGetHyperES(pVCpu) == SELMGetHyperDS(pVM))
152 RTPrintf("VMM: FAILURE - es=%x expected %x\n", CPUMGetHyperES(pVCpu), SELMGetHyperDS(pVM));
153 if (CPUMGetHyperDS(pVCpu) == SELMGetHyperDS(pVM))
154 RTPrintf("VMM: FAILURE - ds=%x expected %x\n", CPUMGetHyperDS(pVCpu), SELMGetHyperDS(pVM));
155 if (CPUMGetHyperFS(pVCpu) == SELMGetHyperDS(pVM))
156 RTPrintf("VMM: FAILURE - fs=%x expected %x\n", CPUMGetHyperFS(pVCpu), SELMGetHyperDS(pVM));
157 if (CPUMGetHyperGS(pVCpu) == SELMGetHyperDS(pVM))
158 RTPrintf("VMM: FAILURE - gs=%x expected %x\n", CPUMGetHyperGS(pVCpu), SELMGetHyperDS(pVM));
159 if (CPUMGetHyperEDI(pVCpu) == 0x01234567)
160 RTPrintf("VMM: FAILURE - edi=%x expected %x\n", CPUMGetHyperEDI(pVCpu), 0x01234567);
161 if (CPUMGetHyperESI(pVCpu) == 0x42000042)
162 RTPrintf("VMM: FAILURE - esi=%x expected %x\n", CPUMGetHyperESI(pVCpu), 0x42000042);
163 if (CPUMGetHyperEBP(pVCpu) == 0xffeeddcc)
164 RTPrintf("VMM: FAILURE - ebp=%x expected %x\n", CPUMGetHyperEBP(pVCpu), 0xffeeddcc);
165 if (CPUMGetHyperEBX(pVCpu) == 0x89abcdef)
166 RTPrintf("VMM: FAILURE - ebx=%x expected %x\n", CPUMGetHyperEBX(pVCpu), 0x89abcdef);
167 if (CPUMGetHyperECX(pVCpu) == 0xffffaaaa)
168 RTPrintf("VMM: FAILURE - ecx=%x expected %x\n", CPUMGetHyperECX(pVCpu), 0xffffaaaa);
169 if (CPUMGetHyperEDX(pVCpu) == 0x77778888)
170 RTPrintf("VMM: FAILURE - edx=%x expected %x\n", CPUMGetHyperEDX(pVCpu), 0x77778888);
171 if (CPUMGetHyperEAX(pVCpu) == u32Eax)
172 RTPrintf("VMM: FAILURE - eax=%x expected %x\n", CPUMGetHyperEAX(pVCpu), u32Eax);
173 }
174 if (fDump)
175 VMMR3FatalDump(pVM, pVCpu, rc);
176 return rc;
177}
178
179
180/* execute the switch. */
181VMMR3DECL(int) VMMDoTest(PVM pVM)
182{
183#if 1
184 PVMCPU pVCpu = &pVM->aCpus[0];
185
186#ifdef NO_SUPCALLR0VMM
187 RTPrintf("NO_SUPCALLR0VMM\n");
188 return VINF_SUCCESS;
189#endif
190
191 /*
192 * Setup stack for calling VMMGCEntry().
193 */
194 RTRCPTR RCPtrEP;
195 int rc = PDMR3LdrGetSymbolRC(pVM, VMMGC_MAIN_MODULE_NAME, "VMMGCEntry", &RCPtrEP);
196 if (RT_SUCCESS(rc))
197 {
198 RTPrintf("VMM: VMMGCEntry=%RRv\n", RCPtrEP);
199
200 /*
201 * Test various crashes which we must be able to recover from.
202 */
203 vmmR3DoTrapTest(pVM, 0x3, 0, VINF_EM_DBG_HYPER_ASSERTION, 0xf0f0f0f0, "vmmGCTestTrap3_FaultEIP", "int3");
204 vmmR3DoTrapTest(pVM, 0x3, 1, VINF_EM_DBG_HYPER_ASSERTION, 0xf0f0f0f0, "vmmGCTestTrap3_FaultEIP", "int3 WP");
205
206#if defined(DEBUG_bird) /* guess most people would like to skip these since they write to com1. */
207 vmmR3DoTrapTest(pVM, 0x8, 0, VERR_TRPM_PANIC, 0x00000000, "vmmGCTestTrap8_FaultEIP", "#DF [#PG]");
208 SELMR3Relocate(pVM); /* this resets the busy flag of the Trap 08 TSS */
209 bool f;
210 rc = CFGMR3QueryBool(CFGMR3GetRoot(pVM), "DoubleFault", &f);
211#if !defined(DEBUG_bird)
212 if (RT_SUCCESS(rc) && f)
213#endif
214 {
215 /* see tripple fault warnings in SELM and VMMGC.cpp. */
216 vmmR3DoTrapTest(pVM, 0x8, 1, VERR_TRPM_PANIC, 0x00000000, "vmmGCTestTrap8_FaultEIP", "#DF [#PG] WP");
217 SELMR3Relocate(pVM); /* this resets the busy flag of the Trap 08 TSS */
218 }
219#endif
220
221 vmmR3DoTrapTest(pVM, 0xd, 0, VERR_TRPM_DONT_PANIC, 0xf0f0f0f0, "vmmGCTestTrap0d_FaultEIP", "ltr #GP");
222 ///@todo find a better \#GP case, on intel ltr will \#PF (busy update?) and not \#GP.
223 //vmmR3DoTrapTest(pVM, 0xd, 1, VERR_TRPM_DONT_PANIC, 0xf0f0f0f0, "vmmGCTestTrap0d_FaultEIP", "ltr #GP WP");
224
225 vmmR3DoTrapTest(pVM, 0xe, 0, VERR_TRPM_DONT_PANIC, 0x00000000, "vmmGCTestTrap0e_FaultEIP", "#PF (NULL)");
226 vmmR3DoTrapTest(pVM, 0xe, 1, VERR_TRPM_DONT_PANIC, 0x00000000, "vmmGCTestTrap0e_FaultEIP", "#PF (NULL) WP");
227 vmmR3DoTrapTest(pVM, 0xe, 2, VINF_SUCCESS, 0x00000000, NULL, "#PF w/Tmp Handler");
228 vmmR3DoTrapTest(pVM, 0xe, 4, VINF_SUCCESS, 0x00000000, NULL, "#PF w/Tmp Handler and bad fs");
229
230 /*
231 * Set a debug register and perform a context switch.
232 */
233 rc = vmmR3DoGCTest(pVM, VMMGC_DO_TESTCASE_NOP, 0);
234 if (rc != VINF_SUCCESS)
235 {
236 RTPrintf("VMM: Nop test failed, rc=%Rrc not VINF_SUCCESS\n", rc);
237 return rc;
238 }
239
240 /* a harmless breakpoint */
241 RTPrintf("VMM: testing hardware bp at 0x10000 (not hit)\n");
242 DBGFADDRESS Addr;
243 DBGFR3AddrFromFlat(pVM, &Addr, 0x10000);
244 RTUINT iBp0;
245 rc = DBGFR3BpSetReg(pVM, &Addr, 0, ~(uint64_t)0, X86_DR7_RW_EO, 1, &iBp0);
246 AssertReleaseRC(rc);
247 rc = vmmR3DoGCTest(pVM, VMMGC_DO_TESTCASE_NOP, 0);
248 if (rc != VINF_SUCCESS)
249 {
250 RTPrintf("VMM: DR0=0x10000 test failed with rc=%Rrc!\n", rc);
251 return rc;
252 }
253
254 /* a bad one at VMMGCEntry */
255 RTPrintf("VMM: testing hardware bp at VMMGCEntry (hit)\n");
256 DBGFR3AddrFromFlat(pVM, &Addr, RCPtrEP);
257 RTUINT iBp1;
258 rc = DBGFR3BpSetReg(pVM, &Addr, 0, ~(uint64_t)0, X86_DR7_RW_EO, 1, &iBp1);
259 AssertReleaseRC(rc);
260 rc = vmmR3DoGCTest(pVM, VMMGC_DO_TESTCASE_NOP, 0);
261 if (rc != VINF_EM_DBG_HYPER_BREAKPOINT)
262 {
263 RTPrintf("VMM: DR1=VMMGCEntry test failed with rc=%Rrc! expected VINF_EM_RAW_BREAKPOINT_HYPER\n", rc);
264 return rc;
265 }
266
267 /* resume the breakpoint */
268 RTPrintf("VMM: resuming hyper after breakpoint\n");
269 CPUMSetHyperEFlags(pVCpu, CPUMGetHyperEFlags(pVCpu) | X86_EFL_RF);
270 rc = VMMR3ResumeHyper(pVM, pVCpu);
271 if (rc != VINF_SUCCESS)
272 {
273 RTPrintf("VMM: failed to resume on hyper breakpoint, rc=%Rrc\n", rc);
274 return rc;
275 }
276
277 /* engage the breakpoint again and try single stepping. */
278 RTPrintf("VMM: testing hardware bp at VMMGCEntry + stepping\n");
279 rc = vmmR3DoGCTest(pVM, VMMGC_DO_TESTCASE_NOP, 0);
280 if (rc != VINF_EM_DBG_HYPER_BREAKPOINT)
281 {
282 RTPrintf("VMM: DR1=VMMGCEntry test failed with rc=%Rrc! expected VINF_EM_RAW_BREAKPOINT_HYPER\n", rc);
283 return rc;
284 }
285
286 RTGCUINTREG OldPc = CPUMGetHyperEIP(pVCpu);
287 RTPrintf("%RGr=>", OldPc);
288 unsigned i;
289 for (i = 0; i < 8; i++)
290 {
291 CPUMSetHyperEFlags(pVCpu, CPUMGetHyperEFlags(pVCpu) | X86_EFL_TF | X86_EFL_RF);
292 rc = VMMR3ResumeHyper(pVM, pVCpu);
293 if (rc != VINF_EM_DBG_HYPER_STEPPED)
294 {
295 RTPrintf("\nVMM: failed to step on hyper breakpoint, rc=%Rrc\n", rc);
296 return rc;
297 }
298 RTGCUINTREG Pc = CPUMGetHyperEIP(pVCpu);
299 RTPrintf("%RGr=>", Pc);
300 if (Pc == OldPc)
301 {
302 RTPrintf("\nVMM: step failed, PC: %RGr -> %RGr\n", OldPc, Pc);
303 return VERR_GENERAL_FAILURE;
304 }
305 OldPc = Pc;
306 }
307 RTPrintf("ok\n");
308
309 /* done, clear it */
310 if ( RT_FAILURE(DBGFR3BpClear(pVM, iBp0))
311 || RT_FAILURE(DBGFR3BpClear(pVM, iBp1)))
312 {
313 RTPrintf("VMM: Failed to clear breakpoints!\n");
314 return VERR_GENERAL_FAILURE;
315 }
316 rc = vmmR3DoGCTest(pVM, VMMGC_DO_TESTCASE_NOP, 0);
317 if (rc != VINF_SUCCESS)
318 {
319 RTPrintf("VMM: NOP failed, rc=%Rrc\n", rc);
320 return rc;
321 }
322
323 /*
324 * Interrupt masking.
325 */
326 RTPrintf("VMM: interrupt masking...\n"); RTStrmFlush(g_pStdOut); RTThreadSleep(250);
327 for (i = 0; i < 10000; i++)
328 {
329 uint64_t StartTick = ASMReadTSC();
330 rc = vmmR3DoGCTest(pVM, VMMGC_DO_TESTCASE_INTERRUPT_MASKING, 0);
331 if (rc != VINF_SUCCESS)
332 {
333 RTPrintf("VMM: Interrupt masking failed: rc=%Rrc\n", rc);
334 return rc;
335 }
336 uint64_t Ticks = ASMReadTSC() - StartTick;
337 if (Ticks < (SUPGetCpuHzFromGIP(g_pSUPGlobalInfoPage) / 10000))
338 RTPrintf("Warning: Ticks=%RU64 (< %RU64)\n", Ticks, SUPGetCpuHzFromGIP(g_pSUPGlobalInfoPage) / 10000);
339 }
340
341 /*
342 * Interrupt forwarding.
343 */
344 CPUMHyperSetCtxCore(pVCpu, NULL);
345 CPUMSetHyperESP(pVCpu, pVCpu->vmm.s.pbEMTStackBottomRC); /* Clear the stack. */
346 CPUMPushHyper(pVCpu, 0);
347 CPUMPushHyper(pVCpu, VMMGC_DO_TESTCASE_HYPER_INTERRUPT);
348 CPUMPushHyper(pVCpu, pVM->pVMRC);
349 CPUMPushHyper(pVCpu, 3 * sizeof(RTRCPTR)); /* stack frame size */
350 CPUMPushHyper(pVCpu, RCPtrEP); /* what to call */
351 CPUMSetHyperEIP(pVCpu, pVM->vmm.s.pfnCallTrampolineRC);
352 Log(("trampoline=%x\n", pVM->vmm.s.pfnCallTrampolineRC));
353
354 /*
355 * Switch and do da thing.
356 */
357 RTPrintf("VMM: interrupt forwarding...\n"); RTStrmFlush(g_pStdOut); RTThreadSleep(250);
358 i = 0;
359 uint64_t tsBegin = RTTimeNanoTS();
360 uint64_t TickStart = ASMReadTSC();
361 Assert(CPUMGetHyperCR3(pVCpu) && CPUMGetHyperCR3(pVCpu) == PGMGetHyperCR3(pVCpu));
362 do
363 {
364 rc = SUPR3CallVMMR0Fast(pVM->pVMR0, VMMR0_DO_RAW_RUN, 0);
365 if (RT_LIKELY(rc == VINF_SUCCESS))
366 rc = pVCpu->vmm.s.iLastGZRc;
367 if (RT_FAILURE(rc))
368 {
369 Log(("VMM: GC returned fatal %Rra in iteration %d\n", rc, i));
370 VMMR3FatalDump(pVM, pVCpu, rc);
371 return rc;
372 }
373 i++;
374 if (!(i % 32))
375 Log(("VMM: iteration %d, esi=%08x edi=%08x ebx=%08x\n",
376 i, CPUMGetHyperESI(pVCpu), CPUMGetHyperEDI(pVCpu), CPUMGetHyperEBX(pVCpu)));
377 } while (rc == VINF_EM_RAW_INTERRUPT_HYPER);
378 uint64_t TickEnd = ASMReadTSC();
379 uint64_t tsEnd = RTTimeNanoTS();
380
381 uint64_t Elapsed = tsEnd - tsBegin;
382 uint64_t PerIteration = Elapsed / (uint64_t)i;
383 uint64_t cTicksElapsed = TickEnd - TickStart;
384 uint64_t cTicksPerIteration = cTicksElapsed / (uint64_t)i;
385
386 RTPrintf("VMM: %8d interrupts in %11llu ns (%11llu ticks), %10llu ns/iteration (%11llu ticks)\n",
387 i, Elapsed, cTicksElapsed, PerIteration, cTicksPerIteration);
388 Log(("VMM: %8d interrupts in %11llu ns (%11llu ticks), %10llu ns/iteration (%11llu ticks)\n",
389 i, Elapsed, cTicksElapsed, PerIteration, cTicksPerIteration));
390
391 /*
392 * These forced actions are not necessary for the test and trigger breakpoints too.
393 */
394 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_TRPM_SYNC_IDT);
395 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_SELM_SYNC_TSS);
396
397 /*
398 * Profile switching.
399 */
400 RTPrintf("VMM: profiling switcher...\n");
401 Log(("VMM: profiling switcher...\n"));
402 uint64_t TickMin = ~0;
403 tsBegin = RTTimeNanoTS();
404 TickStart = ASMReadTSC();
405 Assert(CPUMGetHyperCR3(pVCpu) && CPUMGetHyperCR3(pVCpu) == PGMGetHyperCR3(pVCpu));
406 for (i = 0; i < 1000000; i++)
407 {
408 CPUMHyperSetCtxCore(pVCpu, NULL);
409 CPUMSetHyperESP(pVCpu, pVCpu->vmm.s.pbEMTStackBottomRC); /* Clear the stack. */
410 CPUMPushHyper(pVCpu, 0);
411 CPUMPushHyper(pVCpu, VMMGC_DO_TESTCASE_NOP);
412 CPUMPushHyper(pVCpu, pVM->pVMRC);
413 CPUMPushHyper(pVCpu, 3 * sizeof(RTRCPTR)); /* stack frame size */
414 CPUMPushHyper(pVCpu, RCPtrEP); /* what to call */
415 CPUMSetHyperEIP(pVCpu, pVM->vmm.s.pfnCallTrampolineRC);
416
417 uint64_t TickThisStart = ASMReadTSC();
418 rc = SUPR3CallVMMR0Fast(pVM->pVMR0, VMMR0_DO_RAW_RUN, 0);
419 if (RT_LIKELY(rc == VINF_SUCCESS))
420 rc = pVCpu->vmm.s.iLastGZRc;
421 uint64_t TickThisElapsed = ASMReadTSC() - TickThisStart;
422 if (RT_FAILURE(rc))
423 {
424 Log(("VMM: GC returned fatal %Rra in iteration %d\n", rc, i));
425 VMMR3FatalDump(pVM, pVCpu, rc);
426 return rc;
427 }
428 if (TickThisElapsed < TickMin)
429 TickMin = TickThisElapsed;
430 }
431 TickEnd = ASMReadTSC();
432 tsEnd = RTTimeNanoTS();
433
434 Elapsed = tsEnd - tsBegin;
435 PerIteration = Elapsed / (uint64_t)i;
436 cTicksElapsed = TickEnd - TickStart;
437 cTicksPerIteration = cTicksElapsed / (uint64_t)i;
438
439 RTPrintf("VMM: %8d cycles in %11llu ns (%11lld ticks), %10llu ns/iteration (%11lld ticks) Min %11lld ticks\n",
440 i, Elapsed, cTicksElapsed, PerIteration, cTicksPerIteration, TickMin);
441 Log(("VMM: %8d cycles in %11llu ns (%11lld ticks), %10llu ns/iteration (%11lld ticks) Min %11lld ticks\n",
442 i, Elapsed, cTicksElapsed, PerIteration, cTicksPerIteration, TickMin));
443
444 rc = VINF_SUCCESS;
445 }
446 else
447 AssertMsgFailed(("Failed to resolved VMMGC.gc::VMMGCEntry(), rc=%Rrc\n", rc));
448#endif
449 return rc;
450}
451
452#define SYNC_SEL(pHyperCtx, reg) \
453 if (pHyperCtx->reg) \
454 { \
455 DBGFSELINFO selInfo; \
456 int rc2 = SELMR3GetShadowSelectorInfo(pVM, pHyperCtx->reg, &selInfo); \
457 AssertRC(rc2); \
458 \
459 pHyperCtx->reg##Hid.u64Base = selInfo.GCPtrBase; \
460 pHyperCtx->reg##Hid.u32Limit = selInfo.cbLimit; \
461 pHyperCtx->reg##Hid.Attr.n.u1Present = selInfo.u.Raw.Gen.u1Present; \
462 pHyperCtx->reg##Hid.Attr.n.u1DefBig = selInfo.u.Raw.Gen.u1DefBig; \
463 pHyperCtx->reg##Hid.Attr.n.u1Granularity = selInfo.u.Raw.Gen.u1Granularity; \
464 pHyperCtx->reg##Hid.Attr.n.u4Type = selInfo.u.Raw.Gen.u4Type; \
465 pHyperCtx->reg##Hid.Attr.n.u2Dpl = selInfo.u.Raw.Gen.u2Dpl; \
466 pHyperCtx->reg##Hid.Attr.n.u1DescType = selInfo.u.Raw.Gen.u1DescType; \
467 pHyperCtx->reg##Hid.Attr.n.u1Long = selInfo.u.Raw.Gen.u1Long; \
468 }
469
470/* execute the switch. */
471VMMR3DECL(int) VMMDoHwAccmTest(PVM pVM)
472{
473 uint32_t i;
474 int rc;
475 PCPUMCTX pHyperCtx, pGuestCtx;
476 RTGCPHYS CR3Phys = 0x0; /* fake address */
477 PVMCPU pVCpu = &pVM->aCpus[0];
478
479 if (!HWACCMR3IsAllowed(pVM))
480 {
481 RTPrintf("VMM: Hardware accelerated test not available!\n");
482 return VERR_ACCESS_DENIED;
483 }
484
485 /*
486 * These forced actions are not necessary for the test and trigger breakpoints too.
487 */
488 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_TRPM_SYNC_IDT);
489 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_SELM_SYNC_TSS);
490
491 /* Enable mapping of the hypervisor into the shadow page table. */
492 uint32_t cb;
493 rc = PGMR3MappingsSize(pVM, &cb);
494 AssertRCReturn(rc, rc);
495
496 /* Pretend the mappings are now fixed; to force a refresh of the reserved PDEs. */
497 rc = PGMR3MappingsFix(pVM, MM_HYPER_AREA_ADDRESS, cb);
498 AssertRCReturn(rc, rc);
499
500 CPUMQueryHyperCtxPtr(pVCpu, &pHyperCtx);
501
502 pHyperCtx->cr0 = X86_CR0_PE | X86_CR0_WP | X86_CR0_PG | X86_CR0_TS | X86_CR0_ET | X86_CR0_NE | X86_CR0_MP;
503 pHyperCtx->cr4 = X86_CR4_PGE | X86_CR4_OSFSXR | X86_CR4_OSXMMEEXCPT;
504 PGMChangeMode(pVCpu, pHyperCtx->cr0, pHyperCtx->cr4, pHyperCtx->msrEFER);
505 PGMSyncCR3(pVCpu, pHyperCtx->cr0, CR3Phys, pHyperCtx->cr4, true);
506
507 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_TO_R3);
508 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_TIMER);
509 VM_FF_CLEAR(pVM, VM_FF_TM_VIRTUAL_SYNC);
510 VM_FF_CLEAR(pVM, VM_FF_REQUEST);
511
512 /*
513 * Setup stack for calling VMMGCEntry().
514 */
515 RTRCPTR RCPtrEP;
516 rc = PDMR3LdrGetSymbolRC(pVM, VMMGC_MAIN_MODULE_NAME, "VMMGCEntry", &RCPtrEP);
517 if (RT_SUCCESS(rc))
518 {
519 RTPrintf("VMM: VMMGCEntry=%RRv\n", RCPtrEP);
520
521 CPUMQueryHyperCtxPtr(pVCpu, &pHyperCtx);
522
523 /* Fill in hidden selector registers for the hypervisor state. */
524 SYNC_SEL(pHyperCtx, cs);
525 SYNC_SEL(pHyperCtx, ds);
526 SYNC_SEL(pHyperCtx, es);
527 SYNC_SEL(pHyperCtx, fs);
528 SYNC_SEL(pHyperCtx, gs);
529 SYNC_SEL(pHyperCtx, ss);
530 SYNC_SEL(pHyperCtx, tr);
531
532 /*
533 * Profile switching.
534 */
535 RTPrintf("VMM: profiling switcher...\n");
536 Log(("VMM: profiling switcher...\n"));
537 uint64_t TickMin = ~0;
538 uint64_t tsBegin = RTTimeNanoTS();
539 uint64_t TickStart = ASMReadTSC();
540 for (i = 0; i < 1000000; i++)
541 {
542 CPUMHyperSetCtxCore(pVCpu, NULL);
543
544 CPUMSetHyperESP(pVCpu, pVCpu->vmm.s.pbEMTStackBottomRC); /* Clear the stack. */
545 CPUMPushHyper(pVCpu, 0);
546 CPUMPushHyper(pVCpu, VMMGC_DO_TESTCASE_HWACCM_NOP);
547 CPUMPushHyper(pVCpu, pVM->pVMRC);
548 CPUMPushHyper(pVCpu, 3 * sizeof(RTRCPTR)); /* stack frame size */
549 CPUMPushHyper(pVCpu, RCPtrEP); /* what to call */
550 CPUMSetHyperEIP(pVCpu, pVM->vmm.s.pfnCallTrampolineRC);
551
552 CPUMQueryHyperCtxPtr(pVCpu, &pHyperCtx);
553 pGuestCtx = CPUMQueryGuestCtxPtr(pVCpu);
554
555 /* Copy the hypervisor context to make sure we have a valid guest context. */
556 *pGuestCtx = *pHyperCtx;
557 pGuestCtx->cr3 = CR3Phys;
558
559 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_TO_R3);
560 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_TIMER);
561 VM_FF_CLEAR(pVM, VM_FF_TM_VIRTUAL_SYNC);
562
563 uint64_t TickThisStart = ASMReadTSC();
564 rc = SUPR3CallVMMR0Fast(pVM->pVMR0, VMMR0_DO_HWACC_RUN, 0);
565 uint64_t TickThisElapsed = ASMReadTSC() - TickThisStart;
566 if (RT_FAILURE(rc))
567 {
568 Log(("VMM: R0 returned fatal %Rrc in iteration %d\n", rc, i));
569 VMMR3FatalDump(pVM, pVCpu, rc);
570 return rc;
571 }
572 if (TickThisElapsed < TickMin)
573 TickMin = TickThisElapsed;
574 }
575 uint64_t TickEnd = ASMReadTSC();
576 uint64_t tsEnd = RTTimeNanoTS();
577
578 uint64_t Elapsed = tsEnd - tsBegin;
579 uint64_t PerIteration = Elapsed / (uint64_t)i;
580 uint64_t cTicksElapsed = TickEnd - TickStart;
581 uint64_t cTicksPerIteration = cTicksElapsed / (uint64_t)i;
582
583 RTPrintf("VMM: %8d cycles in %11llu ns (%11lld ticks), %10llu ns/iteration (%11lld ticks) Min %11lld ticks\n",
584 i, Elapsed, cTicksElapsed, PerIteration, cTicksPerIteration, TickMin);
585 Log(("VMM: %8d cycles in %11llu ns (%11lld ticks), %10llu ns/iteration (%11lld ticks) Min %11lld ticks\n",
586 i, Elapsed, cTicksElapsed, PerIteration, cTicksPerIteration, TickMin));
587
588 rc = VINF_SUCCESS;
589 }
590 else
591 AssertMsgFailed(("Failed to resolved VMMGC.gc::VMMGCEntry(), rc=%Rrc\n", rc));
592
593 return rc;
594}
595
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