CPUMInternal.h@ 49591

Last change on this file since 49591 was 49019, checked in by vboxsync, 11 years ago
VMM: FPU cleanup.
Property svn:eol-style set to `native` Property svn:keywords set to `Id`
File size: 13.5 KB

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1	/* $Id: CPUMInternal.h 49019 2013-10-10 08:45:11Z vboxsync $ */
2	/** @file
3	* CPUM - Internal header file.
4	*/
5
6	/*
7	* Copyright (C) 2006-2012 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*/
17
18	#ifndef ___CPUMInternal_h
19	#define ___CPUMInternal_h
20
21	#ifndef VBOX_FOR_DTRACE_LIB
22	# include <VBox/cdefs.h>
23	# include <VBox/types.h>
24	# include <iprt/x86.h>
25	#else
26	# pragma D depends_on library x86.d
27	# pragma D depends_on library cpumctx.d
28	#endif
29
30
31
32
33	/** @defgroup grp_cpum_int Internals
34	* @ingroup grp_cpum
35	* @internal
36	* @{
37	*/
38
39	/** Flags and types for CPUM fault handlers
40	* @{ */
41	/** Type: Load DS */
42	#define CPUM_HANDLER_DS 1
43	/** Type: Load ES */
44	#define CPUM_HANDLER_ES 2
45	/** Type: Load FS */
46	#define CPUM_HANDLER_FS 3
47	/** Type: Load GS */
48	#define CPUM_HANDLER_GS 4
49	/** Type: IRET */
50	#define CPUM_HANDLER_IRET 5
51	/** Type mask. */
52	#define CPUM_HANDLER_TYPEMASK 0xff
53	/** If set EBP points to the CPUMCTXCORE that's being used. */
54	#define CPUM_HANDLER_CTXCORE_IN_EBP RT_BIT(31)
55	/** @} */
56
57
58	/** Use flags (CPUM::fUseFlags).
59	* (Don't forget to sync this with CPUMInternal.mac !)
60	* @{ */
61	/** Used the FPU, SSE or such stuff. */
62	#define CPUM_USED_FPU RT_BIT(0)
63	/** Used the FPU, SSE or such stuff since last we were in REM.
64	* REM syncing is clearing this, lazy FPU is setting it. */
65	#define CPUM_USED_FPU_SINCE_REM RT_BIT(1)
66	/** The XMM state was manually restored. (AMD only) */
67	#define CPUM_USED_MANUAL_XMM_RESTORE RT_BIT(2)
68
69	/** Host OS is using SYSENTER and we must NULL the CS. */
70	#define CPUM_USE_SYSENTER RT_BIT(3)
71	/** Host OS is using SYSENTER and we must NULL the CS. */
72	#define CPUM_USE_SYSCALL RT_BIT(4)
73
74	/** Debug registers are used by host and that DR7 and DR6 must be saved and
75	* disabled when switching to raw-mode. */
76	#define CPUM_USE_DEBUG_REGS_HOST RT_BIT(5)
77	/** Records that we've saved the host DRx registers.
78	* In ring-0 this means all (DR0-7), while in raw-mode context this means DR0-3
79	* since DR6 and DR7 are covered by CPUM_USE_DEBUG_REGS_HOST. */
80	#define CPUM_USED_DEBUG_REGS_HOST RT_BIT(6)
81	/** Set to indicate that we should save host DR0-7 and load the hypervisor debug
82	* registers in the raw-mode world switchers. (See CPUMRecalcHyperDRx.) */
83	#define CPUM_USE_DEBUG_REGS_HYPER RT_BIT(7)
84	/** Used in ring-0 to indicate that we have loaded the hypervisor debug
85	* registers. */
86	#define CPUM_USED_DEBUG_REGS_HYPER RT_BIT(8)
87	/** Used in ring-0 to indicate that we have loaded the guest debug
88	* registers (DR0-3 and maybe DR6) for direct use by the guest.
89	* DR7 (and AMD-V DR6) are handled via the VMCB. */
90	#define CPUM_USED_DEBUG_REGS_GUEST RT_BIT(9)
91
92
93	/** Sync the FPU state on next entry (32->64 switcher only). */
94	#define CPUM_SYNC_FPU_STATE RT_BIT(16)
95	/** Sync the debug state on next entry (32->64 switcher only). */
96	#define CPUM_SYNC_DEBUG_REGS_GUEST RT_BIT(17)
97	/** Sync the debug state on next entry (32->64 switcher only).
98	* Almost the same as CPUM_USE_DEBUG_REGS_HYPER in the raw-mode switchers. */
99	#define CPUM_SYNC_DEBUG_REGS_HYPER RT_BIT(18)
100	/** Host CPU requires fxsave/fxrstor leaky bit handling. */
101	#define CPUM_USE_FFXSR_LEAKY RT_BIT(19)
102	/** @} */
103
104	/* Sanity check. */
105	#ifndef VBOX_FOR_DTRACE_LIB
106	#if defined(VBOX_WITH_HYBRID_32BIT_KERNEL) && (HC_ARCH_BITS != 32 \|\| R0_ARCH_BITS != 32)
107	# error "VBOX_WITH_HYBRID_32BIT_KERNEL is only for 32 bit builds."
108	#endif
109	#endif
110
111
112	/**
113	* The saved host CPU state.
114	*
115	* @remark The special VBOX_WITH_HYBRID_32BIT_KERNEL checks here are for the 10.4.x series
116	* of Mac OS X where the OS is essentially 32-bit but the cpu mode can be 64-bit.
117	*/
118	typedef struct CPUMHOSTCTX
119	{
120	/** FPU state. (16-byte alignment)
121	* @remark On x86, the format isn't necessarily X86FXSTATE (not important). */
122	X86FXSTATE fpu;
123
124	/** General purpose register, selectors, flags and more
125	* @{ */
126	#if HC_ARCH_BITS == 64 \|\| defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
127	/** General purpose register ++
128	* { */
129	/uint64_t rax; - scratch/
130	uint64_t rbx;
131	/uint64_t rcx; - scratch/
132	/uint64_t rdx; - scratch/
133	uint64_t rdi;
134	uint64_t rsi;
135	uint64_t rbp;
136	uint64_t rsp;
137	/uint64_t r8; - scratch/
138	/uint64_t r9; - scratch/
139	uint64_t r10;
140	uint64_t r11;
141	uint64_t r12;
142	uint64_t r13;
143	uint64_t r14;
144	uint64_t r15;
145	/uint64_t rip; - scratch/
146	uint64_t rflags;
147	#endif
148
149	#if HC_ARCH_BITS == 32
150	/uint32_t eax; - scratch/
151	uint32_t ebx;
152	/uint32_t ecx; - scratch/
153	/uint32_t edx; - scratch/
154	uint32_t edi;
155	uint32_t esi;
156	uint32_t ebp;
157	X86EFLAGS eflags;
158	/uint32_t eip; - scratch/
159	/* lss pair! */
160	uint32_t esp;
161	#endif
162	/** @} */
163
164	/** Selector registers
165	* @{ */
166	RTSEL ss;
167	RTSEL ssPadding;
168	RTSEL gs;
169	RTSEL gsPadding;
170	RTSEL fs;
171	RTSEL fsPadding;
172	RTSEL es;
173	RTSEL esPadding;
174	RTSEL ds;
175	RTSEL dsPadding;
176	RTSEL cs;
177	RTSEL csPadding;
178	/** @} */
179
180	#if HC_ARCH_BITS == 32 && !defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
181	/** Control registers.
182	* @{ */
183	uint32_t cr0;
184	/uint32_t cr2; - scratch/
185	uint32_t cr3;
186	uint32_t cr4;
187	/** @} */
188
189	/** Debug registers.
190	* @{ */
191	uint32_t dr0;
192	uint32_t dr1;
193	uint32_t dr2;
194	uint32_t dr3;
195	uint32_t dr6;
196	uint32_t dr7;
197	/** @} */
198
199	/** Global Descriptor Table register. */
200	X86XDTR32 gdtr;
201	uint16_t gdtrPadding;
202	/** Interrupt Descriptor Table register. */
203	X86XDTR32 idtr;
204	uint16_t idtrPadding;
205	/** The task register. */
206	RTSEL ldtr;
207	RTSEL ldtrPadding;
208	/** The task register. */
209	RTSEL tr;
210	RTSEL trPadding;
211	uint32_t SysEnterPadding;
212
213	/** The sysenter msr registers.
214	* This member is not used by the hypervisor context. */
215	CPUMSYSENTER SysEnter;
216
217	/** MSRs
218	* @{ */
219	uint64_t efer;
220	/** @} */
221
222	/* padding to get 64byte aligned size */
223	uint8_t auPadding[16+32];
224
225	#elif HC_ARCH_BITS == 64 \|\| defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
226
227	/** Control registers.
228	* @{ */
229	uint64_t cr0;
230	/uint64_t cr2; - scratch/
231	uint64_t cr3;
232	uint64_t cr4;
233	uint64_t cr8;
234	/** @} */
235
236	/** Debug registers.
237	* @{ */
238	uint64_t dr0;
239	uint64_t dr1;
240	uint64_t dr2;
241	uint64_t dr3;
242	uint64_t dr6;
243	uint64_t dr7;
244	/** @} */
245
246	/** Global Descriptor Table register. */
247	X86XDTR64 gdtr;
248	uint16_t gdtrPadding;
249	/** Interrupt Descriptor Table register. */
250	X86XDTR64 idtr;
251	uint16_t idtrPadding;
252	/** The task register. */
253	RTSEL ldtr;
254	RTSEL ldtrPadding;
255	/** The task register. */
256	RTSEL tr;
257	RTSEL trPadding;
258
259	/** MSRs
260	* @{ */
261	CPUMSYSENTER SysEnter;
262	uint64_t FSbase;
263	uint64_t GSbase;
264	uint64_t efer;
265	/** @} */
266
267	/* padding to get 32byte aligned size */
268	# ifdef VBOX_WITH_HYBRID_32BIT_KERNEL
269	uint8_t auPadding[16];
270	# else
271	uint8_t auPadding[8+32];
272	# endif
273
274	#else
275	# error HC_ARCH_BITS not defined
276	#endif
277	} CPUMHOSTCTX;
278	/** Pointer to the saved host CPU state. */
279	typedef CPUMHOSTCTX *PCPUMHOSTCTX;
280
281
282	/**
283	* CPUM Data (part of VM)
284	*/
285	typedef struct CPUM
286	{
287	/** Offset from CPUM to CPUMCPU for the first CPU. */
288	uint32_t offCPUMCPU0;
289
290	/** Use flags.
291	* These flags indicates which CPU features the host uses.
292	*/
293	uint32_t fHostUseFlags;
294
295	/** Host CPU Features - ECX */
296	struct
297	{
298	/** edx part */
299	X86CPUIDFEATEDX edx;
300	/** ecx part */
301	X86CPUIDFEATECX ecx;
302	} CPUFeatures;
303	/** Host extended CPU features. */
304	struct
305	{
306	/** edx part */
307	uint32_t edx;
308	/** ecx part */
309	uint32_t ecx;
310	} CPUFeaturesExt;
311
312	/** Host CPU manufacturer. */
313	CPUMCPUVENDOR enmHostCpuVendor;
314	/** Guest CPU manufacturer. */
315	CPUMCPUVENDOR enmGuestCpuVendor;
316
317	/** CR4 mask */
318	struct
319	{
320	uint32_t AndMask; /*< @todo Move these to the per-CPU structure and fix the switchers. Saves a register! /
321	uint32_t OrMask;
322	} CR4;
323
324	/** Synthetic CPU type? */
325	bool fSyntheticCpu;
326	/** The (more) portable CPUID level. */
327	uint8_t u8PortableCpuIdLevel;
328	/** Indicates that a state restore is pending.
329	* This is used to verify load order dependencies (PGM). */
330	bool fPendingRestore;
331	uint8_t abPadding[HC_ARCH_BITS == 64 ? 5 : 1];
332
333	/** The standard set of CpuId leaves. */
334	CPUMCPUID aGuestCpuIdStd[6];
335	/** The extended set of CpuId leaves. */
336	CPUMCPUID aGuestCpuIdExt[10];
337	/** The centaur set of CpuId leaves. */
338	CPUMCPUID aGuestCpuIdCentaur[4];
339	/** The hypervisor specific set of CpuId leaves. */
340	CPUMCPUID aGuestCpuIdHyper[4];
341	/** The default set of CpuId leaves. */
342	CPUMCPUID GuestCpuIdDef;
343
344	#if HC_ARCH_BITS == 32
345	uint8_t abPadding2[4];
346	#endif
347	} CPUM;
348	/** Pointer to the CPUM instance data residing in the shared VM structure. */
349	typedef CPUM *PCPUM;
350
351	/**
352	* CPUM Data (part of VMCPU)
353	*/
354	typedef struct CPUMCPU
355	{
356	/**
357	* Hypervisor context.
358	* Aligned on a 64-byte boundary.
359	*/
360	CPUMCTX Hyper;
361
362	/**
363	* Saved host context. Only valid while inside GC.
364	* Aligned on a 64-byte boundary.
365	*/
366	CPUMHOSTCTX Host;
367
368	#ifdef VBOX_WITH_CRASHDUMP_MAGIC
369	uint8_t aMagic[56];
370	uint64_t uMagic;
371	#endif
372
373	/**
374	* Guest context.
375	* Aligned on a 64-byte boundary.
376	*/
377	CPUMCTX Guest;
378
379	/**
380	* Guest context - misc MSRs
381	* Aligned on a 64-byte boundary.
382	*/
383	CPUMCTXMSRS GuestMsrs;
384
385	/** Use flags.
386	* These flags indicates both what is to be used and what has been used.
387	*/
388	uint32_t fUseFlags;
389
390	/** Changed flags.
391	* These flags indicates to REM (and others) which important guest
392	* registers which has been changed since last time the flags were cleared.
393	* See the CPUM_CHANGED_* defines for what we keep track of.
394	*/
395	uint32_t fChanged;
396
397	/** Offset from CPUM to CPUMCPU. */
398	uint32_t offCPUM;
399
400	/** Temporary storage for the return code of the function called in the
401	* 32-64 switcher. */
402	uint32_t u32RetCode;
403
404	#ifdef VBOX_WITH_VMMR0_DISABLE_LAPIC_NMI
405	/** The address of the APIC mapping, NULL if no APIC.
406	* Call CPUMR0SetLApic to update this before doing a world switch. */
407	RTHCPTR pvApicBase;
408	/** Used by the world switcher code to store which vectors needs restoring on
409	* the way back. */
410	uint32_t fApicDisVectors;
411	/** Set if the CPU has the X2APIC mode enabled.
412	* Call CPUMR0SetLApic to update this before doing a world switch. */
413	bool fX2Apic;
414	#else
415	uint8_t abPadding3[(HC_ARCH_BITS == 64 ? 8 : 4) + 4 + 1];
416	#endif
417
418	/** Have we entered raw-mode? */
419	bool fRawEntered;
420	/** Have we entered the recompiler? */
421	bool fRemEntered;
422
423	/** Align the structure on a 64-byte boundary. */
424	uint8_t abPadding2[64 - 16 - (HC_ARCH_BITS == 64 ? 8 : 4) - 4 - 1 - 2];
425	} CPUMCPU;
426	/** Pointer to the CPUMCPU instance data residing in the shared VMCPU structure. */
427	typedef CPUMCPU *PCPUMCPU;
428
429	#ifndef VBOX_FOR_DTRACE_LIB
430	RT_C_DECLS_BEGIN
431
432	#ifdef IN_RING3
433	int cpumR3DbgInit(PVM pVM);
434	#endif
435
436	#ifdef IN_RC
437	DECLASM(int) cpumHandleLazyFPUAsm(PCPUMCPU pCPUM);
438	#endif
439
440	#ifdef IN_RING0
441	DECLASM(int) cpumR0SaveHostRestoreGuestFPUState(PCPUMCPU pCPUM);
442	DECLASM(int) cpumR0SaveGuestRestoreHostFPUState(PCPUMCPU pCPUM);
443	DECLASM(int) cpumR0SaveHostFPUState(PCPUMCPU pCPUM);
444	DECLASM(int) cpumR0RestoreHostFPUState(PCPUMCPU pCPUM);
445	DECLASM(void) cpumR0LoadFPU(PCPUMCTX pCtx);
446	DECLASM(void) cpumR0SaveFPU(PCPUMCTX pCtx);
447	DECLASM(void) cpumR0LoadXMM(PCPUMCTX pCtx);
448	DECLASM(void) cpumR0SaveXMM(PCPUMCTX pCtx);
449	DECLASM(void) cpumR0SetFCW(uint16_t u16FCW);
450	DECLASM(uint16_t) cpumR0GetFCW(void);
451	DECLASM(void) cpumR0SetMXCSR(uint32_t u32MXCSR);
452	DECLASM(uint32_t) cpumR0GetMXCSR(void);
453	DECLASM(void) cpumR0LoadDRx(uint64_t const *pa4Regs);
454	DECLASM(void) cpumR0SaveDRx(uint64_t *pa4Regs);
455	#endif
456
457	RT_C_DECLS_END
458	#endif /* !VBOX_FOR_DTRACE_LIB */
459
460	/** @} */
461
462	#endif
463

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source: vbox/trunk/src/VBox/VMM/include/CPUMInternal.h@ 49591

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