CPUMInternal.h@ 55384

Last change on this file since 55384 was 55229, checked in by vboxsync, 10 years ago
CPUM,IEM: Expose GuestFeatures and HostFeatures (exploded CPUID), making IEM use it. Early XSAVE/AVX guest support preps.
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File size: 18.9 KB

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1	/* $Id: CPUMInternal.h 55229 2015-04-14 06:35:43Z vboxsync $ */
2	/** @file
3	* CPUM - Internal header file.
4	*/
5
6	/*
7	* Copyright (C) 2006-2015 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*/
17
18	#ifndef ___CPUMInternal_h
19	#define ___CPUMInternal_h
20
21	#ifndef VBOX_FOR_DTRACE_LIB
22	# include <VBox/cdefs.h>
23	# include <VBox/types.h>
24	# include <VBox/vmm/stam.h>
25	# include <iprt/x86.h>
26	#else
27	# pragma D depends_on library x86.d
28	# pragma D depends_on library cpumctx.d
29
30	/* Some fudging. */
31	typedef uint32_t CPUMMICROARCH;
32	typedef uint32_t CPUMUNKNOWNCPUID;
33	typedef struct CPUMCPUIDLEAF *PCPUMCPUIDLEAF;
34	typedef struct CPUMMSRRANGE *PCPUMMSRRANGE;
35	typedef uint64_t STAMCOUNTER;
36	#endif
37
38
39
40
41	/** @defgroup grp_cpum_int Internals
42	* @ingroup grp_cpum
43	* @internal
44	* @{
45	*/
46
47	/** Flags and types for CPUM fault handlers
48	* @{ */
49	/** Type: Load DS */
50	#define CPUM_HANDLER_DS 1
51	/** Type: Load ES */
52	#define CPUM_HANDLER_ES 2
53	/** Type: Load FS */
54	#define CPUM_HANDLER_FS 3
55	/** Type: Load GS */
56	#define CPUM_HANDLER_GS 4
57	/** Type: IRET */
58	#define CPUM_HANDLER_IRET 5
59	/** Type mask. */
60	#define CPUM_HANDLER_TYPEMASK 0xff
61	/** If set EBP points to the CPUMCTXCORE that's being used. */
62	#define CPUM_HANDLER_CTXCORE_IN_EBP RT_BIT(31)
63	/** @} */
64
65
66	/** Use flags (CPUM::fUseFlags).
67	* (Don't forget to sync this with CPUMInternal.mac !)
68	* @{ */
69	/** Used the FPU, SSE or such stuff. */
70	#define CPUM_USED_FPU RT_BIT(0)
71	/** Used the FPU, SSE or such stuff since last we were in REM.
72	* REM syncing is clearing this, lazy FPU is setting it. */
73	#define CPUM_USED_FPU_SINCE_REM RT_BIT(1)
74	/** The XMM state was manually restored. (AMD only) */
75	#define CPUM_USED_MANUAL_XMM_RESTORE RT_BIT(2)
76
77	/** Host OS is using SYSENTER and we must NULL the CS. */
78	#define CPUM_USE_SYSENTER RT_BIT(3)
79	/** Host OS is using SYSENTER and we must NULL the CS. */
80	#define CPUM_USE_SYSCALL RT_BIT(4)
81
82	/** Debug registers are used by host and that DR7 and DR6 must be saved and
83	* disabled when switching to raw-mode. */
84	#define CPUM_USE_DEBUG_REGS_HOST RT_BIT(5)
85	/** Records that we've saved the host DRx registers.
86	* In ring-0 this means all (DR0-7), while in raw-mode context this means DR0-3
87	* since DR6 and DR7 are covered by CPUM_USE_DEBUG_REGS_HOST. */
88	#define CPUM_USED_DEBUG_REGS_HOST RT_BIT(6)
89	/** Set to indicate that we should save host DR0-7 and load the hypervisor debug
90	* registers in the raw-mode world switchers. (See CPUMRecalcHyperDRx.) */
91	#define CPUM_USE_DEBUG_REGS_HYPER RT_BIT(7)
92	/** Used in ring-0 to indicate that we have loaded the hypervisor debug
93	* registers. */
94	#define CPUM_USED_DEBUG_REGS_HYPER RT_BIT(8)
95	/** Used in ring-0 to indicate that we have loaded the guest debug
96	* registers (DR0-3 and maybe DR6) for direct use by the guest.
97	* DR7 (and AMD-V DR6) are handled via the VMCB. */
98	#define CPUM_USED_DEBUG_REGS_GUEST RT_BIT(9)
99
100
101	/** Sync the FPU state on next entry (32->64 switcher only). */
102	#define CPUM_SYNC_FPU_STATE RT_BIT(16)
103	/** Sync the debug state on next entry (32->64 switcher only). */
104	#define CPUM_SYNC_DEBUG_REGS_GUEST RT_BIT(17)
105	/** Sync the debug state on next entry (32->64 switcher only).
106	* Almost the same as CPUM_USE_DEBUG_REGS_HYPER in the raw-mode switchers. */
107	#define CPUM_SYNC_DEBUG_REGS_HYPER RT_BIT(18)
108	/** Host CPU requires fxsave/fxrstor leaky bit handling. */
109	#define CPUM_USE_FFXSR_LEAKY RT_BIT(19)
110	/** Set if the VM supports long-mode. */
111	#define CPUM_USE_SUPPORTS_LONGMODE RT_BIT(20)
112	/** @} */
113
114	/* Sanity check. */
115	#ifndef VBOX_FOR_DTRACE_LIB
116	#if defined(VBOX_WITH_HYBRID_32BIT_KERNEL) && (HC_ARCH_BITS != 32 \|\| R0_ARCH_BITS != 32)
117	# error "VBOX_WITH_HYBRID_32BIT_KERNEL is only for 32 bit builds."
118	#endif
119	#endif
120
121
122	/** @name CPUM Saved State Version.
123	* @{ */
124	/** The current saved state version. */
125	#define CPUM_SAVED_STATE_VERSION 16
126	/** CPUID changes with explode forgetting to update the leaf count on
127	* restore, resulting in garbage being saved restoring+saving old states). */
128	#define CPUM_SAVED_STATE_VERSION_BAD_CPUID_COUNT 15
129	/** The saved state version before the CPUIDs changes. */
130	#define CPUM_SAVED_STATE_VERSION_PUT_STRUCT 14
131	/** The saved state version before using SSMR3PutStruct. */
132	#define CPUM_SAVED_STATE_VERSION_MEM 13
133	/** The saved state version before introducing the MSR size field. */
134	#define CPUM_SAVED_STATE_VERSION_NO_MSR_SIZE 12
135	/** The saved state version of 3.2, 3.1 and 3.3 trunk before the hidden
136	* selector register change (CPUM_CHANGED_HIDDEN_SEL_REGS_INVALID). */
137	#define CPUM_SAVED_STATE_VERSION_VER3_2 11
138	/** The saved state version of 3.0 and 3.1 trunk before the teleportation
139	* changes. */
140	#define CPUM_SAVED_STATE_VERSION_VER3_0 10
141	/** The saved state version for the 2.1 trunk before the MSR changes. */
142	#define CPUM_SAVED_STATE_VERSION_VER2_1_NOMSR 9
143	/** The saved state version of 2.0, used for backwards compatibility. */
144	#define CPUM_SAVED_STATE_VERSION_VER2_0 8
145	/** The saved state version of 1.6, used for backwards compatibility. */
146	#define CPUM_SAVED_STATE_VERSION_VER1_6 6
147	/** @} */
148
149
150	/**
151	* CPU info
152	*/
153	typedef struct CPUMINFO
154	{
155	/** The number of MSR ranges (CPUMMSRRANGE) in the array pointed to below. */
156	uint32_t cMsrRanges;
157	/** Mask applied to ECX before looking up the MSR for a RDMSR/WRMSR
158	* instruction. Older hardware has been observed to ignore higher bits. */
159	uint32_t fMsrMask;
160
161	/** The number of CPUID leaves (CPUMCPUIDLEAF) in the array pointed to below. */
162	uint32_t cCpuIdLeaves;
163	/** The index of the first extended CPUID leaf in the array.
164	* Set to cCpuIdLeaves if none present. */
165	uint32_t iFirstExtCpuIdLeaf;
166	/** Alignment padding. */
167	uint32_t uPadding;
168	/** How to handle unknown CPUID leaves. */
169	CPUMUNKNOWNCPUID enmUnknownCpuIdMethod;
170	/** For use with CPUMUNKNOWNCPUID_DEFAULTS (DB & VM),
171	* CPUMUNKNOWNCPUID_LAST_STD_LEAF (VM) and CPUMUNKNOWNCPUID_LAST_STD_LEAF_WITH_ECX (VM). */
172	CPUMCPUID DefCpuId;
173
174	/** Scalable bus frequency used for reporting other frequencies. */
175	uint64_t uScalableBusFreq;
176
177	/** Pointer to the MSR ranges (ring-0 pointer). */
178	R0PTRTYPE(PCPUMMSRRANGE) paMsrRangesR0;
179	/** Pointer to the CPUID leaves (ring-0 pointer). */
180	R0PTRTYPE(PCPUMCPUIDLEAF) paCpuIdLeavesR0;
181
182	/** Pointer to the MSR ranges (ring-3 pointer). */
183	R3PTRTYPE(PCPUMMSRRANGE) paMsrRangesR3;
184	/** Pointer to the CPUID leaves (ring-3 pointer). */
185	R3PTRTYPE(PCPUMCPUIDLEAF) paCpuIdLeavesR3;
186
187	/** Pointer to the MSR ranges (raw-mode context pointer). */
188	RCPTRTYPE(PCPUMMSRRANGE) paMsrRangesRC;
189	/** Pointer to the CPUID leaves (raw-mode context pointer). */
190	RCPTRTYPE(PCPUMCPUIDLEAF) paCpuIdLeavesRC;
191	} CPUMINFO;
192	/** Pointer to a CPU info structure. */
193	typedef CPUMINFO *PCPUMINFO;
194	/** Pointer to a const CPU info structure. */
195	typedef CPUMINFO const *CPCPUMINFO;
196
197
198	/**
199	* The saved host CPU state.
200	*
201	* @remark The special VBOX_WITH_HYBRID_32BIT_KERNEL checks here are for the 10.4.x series
202	* of Mac OS X where the OS is essentially 32-bit but the cpu mode can be 64-bit.
203	*/
204	typedef struct CPUMHOSTCTX
205	{
206	/** General purpose register, selectors, flags and more
207	* @{ */
208	#if HC_ARCH_BITS == 64 \|\| defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
209	/** General purpose register ++
210	* { */
211	/uint64_t rax; - scratch/
212	uint64_t rbx;
213	/uint64_t rcx; - scratch/
214	/uint64_t rdx; - scratch/
215	uint64_t rdi;
216	uint64_t rsi;
217	uint64_t rbp;
218	uint64_t rsp;
219	/uint64_t r8; - scratch/
220	/uint64_t r9; - scratch/
221	uint64_t r10;
222	uint64_t r11;
223	uint64_t r12;
224	uint64_t r13;
225	uint64_t r14;
226	uint64_t r15;
227	/uint64_t rip; - scratch/
228	uint64_t rflags;
229	#endif
230
231	#if HC_ARCH_BITS == 32
232	/uint32_t eax; - scratch/
233	uint32_t ebx;
234	/uint32_t ecx; - scratch/
235	/uint32_t edx; - scratch/
236	uint32_t edi;
237	uint32_t esi;
238	uint32_t ebp;
239	X86EFLAGS eflags;
240	/uint32_t eip; - scratch/
241	/* lss pair! */
242	uint32_t esp;
243	#endif
244	/** @} */
245
246	/** Selector registers
247	* @{ */
248	RTSEL ss;
249	RTSEL ssPadding;
250	RTSEL gs;
251	RTSEL gsPadding;
252	RTSEL fs;
253	RTSEL fsPadding;
254	RTSEL es;
255	RTSEL esPadding;
256	RTSEL ds;
257	RTSEL dsPadding;
258	RTSEL cs;
259	RTSEL csPadding;
260	/** @} */
261
262	#if HC_ARCH_BITS == 32 && !defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
263	/** Control registers.
264	* @{ */
265	uint32_t cr0;
266	/uint32_t cr2; - scratch/
267	uint32_t cr3;
268	uint32_t cr4;
269	/** @} */
270
271	/** Debug registers.
272	* @{ */
273	uint32_t dr0;
274	uint32_t dr1;
275	uint32_t dr2;
276	uint32_t dr3;
277	uint32_t dr6;
278	uint32_t dr7;
279	/** @} */
280
281	/** Global Descriptor Table register. */
282	X86XDTR32 gdtr;
283	uint16_t gdtrPadding;
284	/** Interrupt Descriptor Table register. */
285	X86XDTR32 idtr;
286	uint16_t idtrPadding;
287	/** The task register. */
288	RTSEL ldtr;
289	RTSEL ldtrPadding;
290	/** The task register. */
291	RTSEL tr;
292	RTSEL trPadding;
293	uint32_t SysEnterPadding;
294
295	/** The sysenter msr registers.
296	* This member is not used by the hypervisor context. */
297	CPUMSYSENTER SysEnter;
298
299	/** MSRs
300	* @{ */
301	uint64_t efer;
302	/** @} */
303
304	/* padding to get 64byte aligned size */
305	uint8_t auPadding[20];
306
307	#elif HC_ARCH_BITS == 64 \|\| defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
308
309	/** Control registers.
310	* @{ */
311	uint64_t cr0;
312	/uint64_t cr2; - scratch/
313	uint64_t cr3;
314	uint64_t cr4;
315	uint64_t cr8;
316	/** @} */
317
318	/** Debug registers.
319	* @{ */
320	uint64_t dr0;
321	uint64_t dr1;
322	uint64_t dr2;
323	uint64_t dr3;
324	uint64_t dr6;
325	uint64_t dr7;
326	/** @} */
327
328	/** Global Descriptor Table register. */
329	X86XDTR64 gdtr;
330	uint16_t gdtrPadding;
331	/** Interrupt Descriptor Table register. */
332	X86XDTR64 idtr;
333	uint16_t idtrPadding;
334	/** The task register. */
335	RTSEL ldtr;
336	RTSEL ldtrPadding;
337	/** The task register. */
338	RTSEL tr;
339	RTSEL trPadding;
340
341	/** MSRs
342	* @{ */
343	CPUMSYSENTER SysEnter;
344	uint64_t FSbase;
345	uint64_t GSbase;
346	uint64_t efer;
347	/** @} */
348
349	/* padding to get 32byte aligned size */
350	# ifdef VBOX_WITH_HYBRID_32BIT_KERNEL
351	uint8_t auPadding[52];
352	# else
353	uint8_t auPadding[4];
354	# endif
355
356	#else
357	# error HC_ARCH_BITS not defined
358	#endif
359
360	/** Pointer to the FPU/SSE/AVX/XXXX state raw-mode mapping. */
361	RCPTRTYPE(PX86XSAVEAREA) pXStateRC;
362	/** Pointer to the FPU/SSE/AVX/XXXX state ring-0 mapping. */
363	R0PTRTYPE(PX86XSAVEAREA) pXStateR0;
364	/** Pointer to the FPU/SSE/AVX/XXXX state ring-3 mapping. */
365	R3PTRTYPE(PX86XSAVEAREA) pXStateR3;
366	/** The XCR0 register. */
367	uint64_t xcr0;
368	/** The mask to pass to XSAVE/XRSTOR in EDX:EAX. If zero we use
369	* FXSAVE/FXRSTOR (since bit 0 will always be set, we only need to test it). */
370	uint64_t fXStateMask;
371	} CPUMHOSTCTX;
372	AssertCompileSizeAlignment(CPUMHOSTCTX, 64);
373	/** Pointer to the saved host CPU state. */
374	typedef CPUMHOSTCTX *PCPUMHOSTCTX;
375
376
377	/**
378	* CPUM Data (part of VM)
379	*/
380	typedef struct CPUM
381	{
382	/** Offset from CPUM to CPUMCPU for the first CPU. */
383	uint32_t offCPUMCPU0;
384
385	/** Use flags.
386	* These flags indicates which CPU features the host uses.
387	*/
388	uint32_t fHostUseFlags;
389
390	/** CR4 mask */
391	struct
392	{
393	uint32_t AndMask; /*< @todo Move these to the per-CPU structure and fix the switchers. Saves a register! /
394	uint32_t OrMask;
395	} CR4;
396
397	/** The (more) portable CPUID level. */
398	uint8_t u8PortableCpuIdLevel;
399	/** Indicates that a state restore is pending.
400	* This is used to verify load order dependencies (PGM). */
401	bool fPendingRestore;
402	uint8_t abPadding0[6];
403
404	/** XSAVE/XRTOR components we can expose to the guest mask. */
405	uint64_t fXStateGuestMask;
406	/** XSAVE/XRSTOR host mask. Only state components in this mask can be exposed
407	* to the guest. This is 0 if no XSAVE/XRSTOR bits can be exposed. */
408	uint64_t fXStateHostMask;
409	uint8_t abPadding1[24];
410
411	/** Host CPU feature information.
412	* Externaly visible via the VM structure, aligned on 64-byte boundrary. */
413	CPUMFEATURES HostFeatures;
414	/** Guest CPU feature information.
415	* Externaly visible via that VM structure, aligned with HostFeatures. */
416	CPUMFEATURES GuestFeatures;
417	/** Guest CPU info. */
418	CPUMINFO GuestInfo;
419
420
421	/** The standard set of CpuId leaves. */
422	CPUMCPUID aGuestCpuIdPatmStd[6];
423	/** The extended set of CpuId leaves. */
424	CPUMCPUID aGuestCpuIdPatmExt[10];
425	/** The centaur set of CpuId leaves. */
426	CPUMCPUID aGuestCpuIdPatmCentaur[4];
427
428	/** @name MSR statistics.
429	* @{ */
430	STAMCOUNTER cMsrWrites;
431	STAMCOUNTER cMsrWritesToIgnoredBits;
432	STAMCOUNTER cMsrWritesRaiseGp;
433	STAMCOUNTER cMsrWritesUnknown;
434	STAMCOUNTER cMsrReads;
435	STAMCOUNTER cMsrReadsRaiseGp;
436	STAMCOUNTER cMsrReadsUnknown;
437	/** @} */
438	} CPUM;
439	AssertCompileMemberOffset(CPUM, HostFeatures, 64);
440	AssertCompileMemberOffset(CPUM, GuestFeatures, 96);
441	/** Pointer to the CPUM instance data residing in the shared VM structure. */
442	typedef CPUM *PCPUM;
443
444	/**
445	* CPUM Data (part of VMCPU)
446	*/
447	typedef struct CPUMCPU
448	{
449	/**
450	* Guest context.
451	* Aligned on a 64-byte boundary.
452	*/
453	CPUMCTX Guest;
454
455	/**
456	* Guest context - misc MSRs
457	* Aligned on a 64-byte boundary.
458	*/
459	CPUMCTXMSRS GuestMsrs;
460
461	/** Use flags.
462	* These flags indicates both what is to be used and what has been used.
463	*/
464	uint32_t fUseFlags;
465
466	/** Changed flags.
467	* These flags indicates to REM (and others) which important guest
468	* registers which has been changed since last time the flags were cleared.
469	* See the CPUM_CHANGED_* defines for what we keep track of.
470	*/
471	uint32_t fChanged;
472
473	/** Offset from CPUM to CPUMCPU. */
474	uint32_t offCPUM;
475
476	/** Temporary storage for the return code of the function called in the
477	* 32-64 switcher. */
478	uint32_t u32RetCode;
479
480	#ifdef VBOX_WITH_VMMR0_DISABLE_LAPIC_NMI
481	/** The address of the APIC mapping, NULL if no APIC.
482	* Call CPUMR0SetLApic to update this before doing a world switch. */
483	RTHCPTR pvApicBase;
484	/** Used by the world switcher code to store which vectors needs restoring on
485	* the way back. */
486	uint32_t fApicDisVectors;
487	/** Set if the CPU has the X2APIC mode enabled.
488	* Call CPUMR0SetLApic to update this before doing a world switch. */
489	bool fX2Apic;
490	#else
491	uint8_t abPadding3[(HC_ARCH_BITS == 64 ? 8 : 4) + 4 + 1];
492	#endif
493
494	/** Have we entered raw-mode? */
495	bool fRawEntered;
496	/** Have we entered the recompiler? */
497	bool fRemEntered;
498
499	/** Align the next member on a 64-bit boundrary. */
500	uint8_t abPadding2[64 - 16 - (HC_ARCH_BITS == 64 ? 8 : 4) - 4 - 1 - 2];
501
502	/** Saved host context. Only valid while inside RC or HM contexts.
503	* Must be aligned on a 64-byte boundary. */
504	CPUMHOSTCTX Host;
505	/** Hypervisor context. Must be aligned on a 64-byte boundary. */
506	CPUMCTX Hyper;
507
508	#ifdef VBOX_WITH_CRASHDUMP_MAGIC
509	uint8_t aMagic[56];
510	uint64_t uMagic;
511	#endif
512	} CPUMCPU;
513	/** Pointer to the CPUMCPU instance data residing in the shared VMCPU structure. */
514	typedef CPUMCPU *PCPUMCPU;
515
516	#ifndef VBOX_FOR_DTRACE_LIB
517	RT_C_DECLS_BEGIN
518
519	PCPUMCPUIDLEAF cpumCpuIdGetLeaf(PVM pVM, uint32_t uLeaf);
520	PCPUMCPUIDLEAF cpumCpuIdGetLeafEx(PVM pVM, uint32_t uLeaf, uint32_t uSubLeaf, bool *pfExactSubLeafHit);
521
522	#ifdef IN_RING3
523	int cpumR3DbgInit(PVM pVM);
524	int cpumR3CpuIdExplodeFeatures(PCCPUMCPUIDLEAF paLeaves, uint32_t cLeaves, PCPUMFEATURES pFeatures);
525	int cpumR3InitCpuIdAndMsrs(PVM pVM);
526	void cpumR3SaveCpuId(PVM pVM, PSSMHANDLE pSSM);
527	int cpumR3LoadCpuId(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion);
528	DECLCALLBACK(void) cpumR3CpuIdInfo(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
529
530	int cpumR3DbGetCpuInfo(const char *pszName, PCPUMINFO pInfo);
531	int cpumR3MsrRangesInsert(PVM pVM, PCPUMMSRRANGE ppaMsrRanges, uint32_t pcMsrRanges, PCCPUMMSRRANGE pNewRange);
532	int cpumR3MsrApplyFudge(PVM pVM);
533	int cpumR3MsrRegStats(PVM pVM);
534	int cpumR3MsrStrictInitChecks(void);
535	PCPUMMSRRANGE cpumLookupMsrRange(PVM pVM, uint32_t idMsr);
536	#endif
537
538	#ifdef IN_RC
539	DECLASM(int) cpumHandleLazyFPUAsm(PCPUMCPU pCPUM);
540	#endif
541
542	#ifdef IN_RING0
543	DECLASM(int) cpumR0SaveHostRestoreGuestFPUState(PCPUMCPU pCPUM);
544	DECLASM(int) cpumR0SaveGuestRestoreHostFPUState(PCPUMCPU pCPUM);
545	DECLASM(int) cpumR0SaveHostFPUState(PCPUMCPU pCPUM);
546	DECLASM(int) cpumR0RestoreHostFPUState(PCPUMCPU pCPUM);
547	DECLASM(void) cpumR0LoadFPU(PCPUMCTX pCtx);
548	DECLASM(void) cpumR0SaveFPU(PCPUMCTX pCtx);
549	DECLASM(void) cpumR0LoadXMM(PCPUMCTX pCtx);
550	DECLASM(void) cpumR0SaveXMM(PCPUMCTX pCtx);
551	DECLASM(void) cpumR0SetFCW(uint16_t u16FCW);
552	DECLASM(uint16_t) cpumR0GetFCW(void);
553	DECLASM(void) cpumR0SetMXCSR(uint32_t u32MXCSR);
554	DECLASM(uint32_t) cpumR0GetMXCSR(void);
555	DECLASM(void) cpumR0LoadDRx(uint64_t const *pa4Regs);
556	DECLASM(void) cpumR0SaveDRx(uint64_t *pa4Regs);
557	#endif
558
559	RT_C_DECLS_END
560	#endif /* !VBOX_FOR_DTRACE_LIB */
561
562	/** @} */
563
564	#endif
565

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source: vbox/trunk/src/VBox/VMM/include/CPUMInternal.h@ 55384

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