| 1 | /* $Id: CPUMInternal.h 99163 2023-03-24 06:19:19Z vboxsync $ */
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| 2 | /** @file
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| 3 | * CPUM - Internal header file.
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| 4 | */
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| 5 |
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| 6 | /*
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| 7 | * Copyright (C) 2006-2023 Oracle and/or its affiliates.
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| 8 | *
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| 9 | * This file is part of VirtualBox base platform packages, as
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| 10 | * available from https://www.virtualbox.org.
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| 11 | *
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| 12 | * This program is free software; you can redistribute it and/or
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| 13 | * modify it under the terms of the GNU General Public License
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| 14 | * as published by the Free Software Foundation, in version 3 of the
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| 15 | * License.
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| 16 | *
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| 17 | * This program is distributed in the hope that it will be useful, but
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| 18 | * WITHOUT ANY WARRANTY; without even the implied warranty of
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| 19 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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| 20 | * General Public License for more details.
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| 21 | *
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| 22 | * You should have received a copy of the GNU General Public License
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| 23 | * along with this program; if not, see <https://www.gnu.org/licenses>.
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| 24 | *
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| 25 | * SPDX-License-Identifier: GPL-3.0-only
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| 26 | */
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| 27 |
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| 28 | #ifndef VMM_INCLUDED_SRC_include_CPUMInternal_h
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| 29 | #define VMM_INCLUDED_SRC_include_CPUMInternal_h
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| 30 | #ifndef RT_WITHOUT_PRAGMA_ONCE
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| 31 | # pragma once
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| 32 | #endif
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| 33 |
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| 34 | #ifndef VBOX_FOR_DTRACE_LIB
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| 35 | # include <VBox/cdefs.h>
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| 36 | # include <VBox/types.h>
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| 37 | # include <VBox/vmm/stam.h>
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| 38 | # include <iprt/x86.h>
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| 39 | # include <VBox/vmm/pgm.h>
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| 40 | #else
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| 41 | # pragma D depends_on library x86.d
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| 42 | # pragma D depends_on library cpumctx.d
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| 43 | # pragma D depends_on library cpum.d
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| 44 |
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| 45 | /* Some fudging. */
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| 46 | typedef uint64_t STAMCOUNTER;
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| 47 | #endif
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| 48 |
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| 49 |
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| 50 |
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| 51 |
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| 52 | /** @defgroup grp_cpum_int Internals
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| 53 | * @ingroup grp_cpum
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| 54 | * @internal
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| 55 | * @{
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| 56 | */
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| 57 |
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| 58 | /** Use flags (CPUM::fUseFlags).
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| 59 | * (Don't forget to sync this with CPUMInternal.mac !)
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| 60 | * @note Was part of saved state (6.1 and earlier).
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| 61 | * @{ */
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| 62 | /** Indicates that we've saved the host FPU, SSE, whatever state and that it
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| 63 | * needs to be restored. */
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| 64 | #define CPUM_USED_FPU_HOST RT_BIT(0)
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| 65 | /** Indicates that we've loaded the guest FPU, SSE, whatever state and that it
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| 66 | * needs to be saved.
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| 67 | * @note Mirrored in CPUMCTX::fUsedFpuGuest for the HM switcher code. */
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| 68 | #define CPUM_USED_FPU_GUEST RT_BIT(10)
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| 69 | /** Used the guest FPU, SSE or such stuff since last we were in REM.
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| 70 | * REM syncing is clearing this, lazy FPU is setting it. */
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| 71 | #define CPUM_USED_FPU_SINCE_REM RT_BIT(1)
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| 72 | /** The XMM state was manually restored. (AMD only) */
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| 73 | #define CPUM_USED_MANUAL_XMM_RESTORE RT_BIT(2)
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| 74 |
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| 75 | /** Host OS is using SYSENTER and we must NULL the CS. */
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| 76 | #define CPUM_USE_SYSENTER RT_BIT(3)
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| 77 | /** Host OS is using SYSENTER and we must NULL the CS. */
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| 78 | #define CPUM_USE_SYSCALL RT_BIT(4)
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| 79 |
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| 80 | /** Debug registers are used by host and that DR7 and DR6 must be saved and
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| 81 | * disabled when switching to raw-mode. */
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| 82 | #define CPUM_USE_DEBUG_REGS_HOST RT_BIT(5)
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| 83 | /** Records that we've saved the host DRx registers.
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| 84 | * In ring-0 this means all (DR0-7), while in raw-mode context this means DR0-3
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| 85 | * since DR6 and DR7 are covered by CPUM_USE_DEBUG_REGS_HOST. */
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| 86 | #define CPUM_USED_DEBUG_REGS_HOST RT_BIT(6)
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| 87 | /** Set to indicate that we should save host DR0-7 and load the hypervisor debug
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| 88 | * registers in the raw-mode world switchers. (See CPUMRecalcHyperDRx.) */
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| 89 | #define CPUM_USE_DEBUG_REGS_HYPER RT_BIT(7)
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| 90 | /** Used in ring-0 to indicate that we have loaded the hypervisor debug
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| 91 | * registers. */
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| 92 | #define CPUM_USED_DEBUG_REGS_HYPER RT_BIT(8)
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| 93 | /** Used in ring-0 to indicate that we have loaded the guest debug
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| 94 | * registers (DR0-3 and maybe DR6) for direct use by the guest.
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| 95 | * DR7 (and AMD-V DR6) are handled via the VMCB. */
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| 96 | #define CPUM_USED_DEBUG_REGS_GUEST RT_BIT(9)
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| 97 |
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| 98 | /** Host CPU requires fxsave/fxrstor leaky bit handling. */
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| 99 | #define CPUM_USE_FFXSR_LEAKY RT_BIT(19)
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| 100 | /** Set if the VM supports long-mode. */
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| 101 | #define CPUM_USE_SUPPORTS_LONGMODE RT_BIT(20)
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| 102 | /** @} */
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| 103 |
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| 104 |
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| 105 | /** @name CPUM Saved State Version.
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| 106 | * @{ */
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| 107 | /** The current saved state version. */
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| 108 | #define CPUM_SAVED_STATE_VERSION CPUM_SAVED_STATE_VERSION_HWVIRT_VMX_4
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| 109 | /** The saved state version with u32RestoreProcCtls2 for Nested Microsoft
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| 110 | * Hyper-V. */
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| 111 | #define CPUM_SAVED_STATE_VERSION_HWVIRT_VMX_4 23
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| 112 | /** The saved state version with more virtual VMCS fields (HLAT prefix size,
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| 113 | * PCONFIG-exiting bitmap, HLAT ptr, VM-exit ctls2) and a CPUMCTX field (VM-exit
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| 114 | * ctls2 MSR). */
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| 115 | #define CPUM_SAVED_STATE_VERSION_HWVIRT_VMX_3 22
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| 116 | /** The saved state version with PAE PDPEs added. */
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| 117 | #define CPUM_SAVED_STATE_VERSION_PAE_PDPES 21
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| 118 | /** The saved state version with more virtual VMCS fields and CPUMCTX VMX fields. */
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| 119 | #define CPUM_SAVED_STATE_VERSION_HWVIRT_VMX_2 20
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| 120 | /** The saved state version including VMX hardware virtualization state. */
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| 121 | #define CPUM_SAVED_STATE_VERSION_HWVIRT_VMX 19
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| 122 | /** The saved state version including SVM hardware virtualization state. */
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| 123 | #define CPUM_SAVED_STATE_VERSION_HWVIRT_SVM 18
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| 124 | /** The saved state version including XSAVE state. */
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| 125 | #define CPUM_SAVED_STATE_VERSION_XSAVE 17
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| 126 | /** The saved state version with good CPUID leaf count. */
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| 127 | #define CPUM_SAVED_STATE_VERSION_GOOD_CPUID_COUNT 16
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| 128 | /** CPUID changes with explode forgetting to update the leaf count on
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| 129 | * restore, resulting in garbage being saved restoring+saving old states). */
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| 130 | #define CPUM_SAVED_STATE_VERSION_BAD_CPUID_COUNT 15
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| 131 | /** The saved state version before the CPUIDs changes. */
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| 132 | #define CPUM_SAVED_STATE_VERSION_PUT_STRUCT 14
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| 133 | /** The saved state version before using SSMR3PutStruct. */
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| 134 | #define CPUM_SAVED_STATE_VERSION_MEM 13
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| 135 | /** The saved state version before introducing the MSR size field. */
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| 136 | #define CPUM_SAVED_STATE_VERSION_NO_MSR_SIZE 12
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| 137 | /** The saved state version of 3.2, 3.1 and 3.3 trunk before the hidden
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| 138 | * selector register change (CPUM_CHANGED_HIDDEN_SEL_REGS_INVALID). */
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| 139 | #define CPUM_SAVED_STATE_VERSION_VER3_2 11
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| 140 | /** The saved state version of 3.0 and 3.1 trunk before the teleportation
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| 141 | * changes. */
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| 142 | #define CPUM_SAVED_STATE_VERSION_VER3_0 10
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| 143 | /** The saved state version for the 2.1 trunk before the MSR changes. */
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| 144 | #define CPUM_SAVED_STATE_VERSION_VER2_1_NOMSR 9
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| 145 | /** The saved state version of 2.0, used for backwards compatibility. */
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| 146 | #define CPUM_SAVED_STATE_VERSION_VER2_0 8
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| 147 | /** The saved state version of 1.6, used for backwards compatibility. */
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| 148 | #define CPUM_SAVED_STATE_VERSION_VER1_6 6
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| 149 | /** @} */
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| 150 |
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| 151 |
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| 152 | /** @name XSAVE limits.
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| 153 | * @{ */
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| 154 | /** Max size we accept for the XSAVE area.
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| 155 | * @see CPUMCTX::abXSave */
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| 156 | #define CPUM_MAX_XSAVE_AREA_SIZE (0x4000 - 0x300)
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| 157 | /* Min size we accept for the XSAVE area. */
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| 158 | #define CPUM_MIN_XSAVE_AREA_SIZE 0x240
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| 159 | /** @} */
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| 160 |
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| 161 |
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| 162 | /**
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| 163 | * CPU info
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| 164 | */
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| 165 | typedef struct CPUMINFO
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| 166 | {
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| 167 | /** The number of MSR ranges (CPUMMSRRANGE) in the array pointed to below. */
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| 168 | uint32_t cMsrRanges;
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| 169 | /** Mask applied to ECX before looking up the MSR for a RDMSR/WRMSR
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| 170 | * instruction. Older hardware has been observed to ignore higher bits. */
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| 171 | uint32_t fMsrMask;
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| 172 |
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| 173 | /** MXCSR mask. */
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| 174 | uint32_t fMxCsrMask;
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| 175 |
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| 176 | /** The number of CPUID leaves (CPUMCPUIDLEAF) in the array pointed to below. */
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| 177 | uint32_t cCpuIdLeaves;
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| 178 | /** The index of the first extended CPUID leaf in the array.
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| 179 | * Set to cCpuIdLeaves if none present. */
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| 180 | uint32_t iFirstExtCpuIdLeaf;
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| 181 | /** How to handle unknown CPUID leaves. */
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| 182 | CPUMUNKNOWNCPUID enmUnknownCpuIdMethod;
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| 183 | /** For use with CPUMUNKNOWNCPUID_DEFAULTS (DB & VM),
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| 184 | * CPUMUNKNOWNCPUID_LAST_STD_LEAF (VM) and CPUMUNKNOWNCPUID_LAST_STD_LEAF_WITH_ECX (VM). */
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| 185 | CPUMCPUID DefCpuId;
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| 186 |
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| 187 | /** Scalable bus frequency used for reporting other frequencies. */
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| 188 | uint64_t uScalableBusFreq;
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| 189 |
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| 190 | /** Pointer to the MSR ranges (for compatibility with old hyper heap code). */
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| 191 | R3PTRTYPE(PCPUMMSRRANGE) paMsrRangesR3;
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| 192 | /** Pointer to the CPUID leaves (for compatibility with old hyper heap code). */
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| 193 | R3PTRTYPE(PCPUMCPUIDLEAF) paCpuIdLeavesR3;
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| 194 |
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| 195 | /** CPUID leaves. */
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| 196 | CPUMCPUIDLEAF aCpuIdLeaves[256];
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| 197 | /** MSR ranges.
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| 198 | * @todo This is insane, so might want to move this into a separate
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| 199 | * allocation. The insanity is mainly for more recent AMD CPUs. */
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| 200 | CPUMMSRRANGE aMsrRanges[8192];
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| 201 | } CPUMINFO;
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| 202 | /** Pointer to a CPU info structure. */
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| 203 | typedef CPUMINFO *PCPUMINFO;
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| 204 | /** Pointer to a const CPU info structure. */
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| 205 | typedef CPUMINFO const *CPCPUMINFO;
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| 206 |
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| 207 |
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| 208 | /**
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| 209 | * The saved host CPU state.
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| 210 | */
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| 211 | typedef struct CPUMHOSTCTX
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| 212 | {
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| 213 | /** The extended state (FPU/SSE/AVX/AVX-2/XXXX). Must be aligned on 64 bytes. */
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| 214 | union /* no tag */
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| 215 | {
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| 216 | X86XSAVEAREA XState;
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| 217 | /** Byte view for simple indexing and space allocation.
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| 218 | * @note Must match or exceed the size of CPUMCTX::abXState. */
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| 219 | uint8_t abXState[0x4000 - 0x300];
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| 220 | } CPUM_UNION_NM(u);
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| 221 |
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| 222 | /** General purpose register, selectors, flags and more
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| 223 | * @{ */
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| 224 | /** General purpose register ++
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| 225 | * { */
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| 226 | /*uint64_t rax; - scratch*/
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| 227 | uint64_t rbx;
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| 228 | /*uint64_t rcx; - scratch*/
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| 229 | /*uint64_t rdx; - scratch*/
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| 230 | uint64_t rdi;
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| 231 | uint64_t rsi;
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| 232 | uint64_t rbp;
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| 233 | uint64_t rsp;
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| 234 | /*uint64_t r8; - scratch*/
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| 235 | /*uint64_t r9; - scratch*/
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| 236 | uint64_t r10;
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| 237 | uint64_t r11;
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| 238 | uint64_t r12;
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| 239 | uint64_t r13;
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| 240 | uint64_t r14;
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| 241 | uint64_t r15;
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| 242 | /*uint64_t rip; - scratch*/
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| 243 | uint64_t rflags;
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| 244 | /** @} */
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| 245 |
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| 246 | /** Selector registers
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| 247 | * @{ */
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| 248 | RTSEL ss;
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| 249 | RTSEL ssPadding;
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| 250 | RTSEL gs;
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| 251 | RTSEL gsPadding;
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| 252 | RTSEL fs;
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| 253 | RTSEL fsPadding;
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| 254 | RTSEL es;
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| 255 | RTSEL esPadding;
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| 256 | RTSEL ds;
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| 257 | RTSEL dsPadding;
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| 258 | RTSEL cs;
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| 259 | RTSEL csPadding;
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| 260 | /** @} */
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| 261 |
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| 262 | /** Control registers.
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| 263 | * @{ */
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| 264 | /** The CR0 FPU state in HM mode. */
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| 265 | uint64_t cr0;
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| 266 | /*uint64_t cr2; - scratch*/
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| 267 | uint64_t cr3;
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| 268 | uint64_t cr4;
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| 269 | uint64_t cr8;
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| 270 | /** @} */
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| 271 |
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| 272 | /** Debug registers.
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| 273 | * @{ */
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| 274 | uint64_t dr0;
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| 275 | uint64_t dr1;
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| 276 | uint64_t dr2;
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| 277 | uint64_t dr3;
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| 278 | uint64_t dr6;
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| 279 | uint64_t dr7;
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| 280 | /** @} */
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| 281 |
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| 282 | /** Global Descriptor Table register. */
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| 283 | X86XDTR64 gdtr;
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| 284 | uint16_t gdtrPadding;
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| 285 | /** Interrupt Descriptor Table register. */
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| 286 | X86XDTR64 idtr;
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| 287 | uint16_t idtrPadding;
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| 288 | /** The task register. */
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| 289 | RTSEL ldtr;
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| 290 | RTSEL ldtrPadding;
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| 291 | /** The task register. */
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| 292 | RTSEL tr;
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| 293 | RTSEL trPadding;
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| 294 |
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| 295 | /** MSRs
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| 296 | * @{ */
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| 297 | CPUMSYSENTER SysEnter;
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| 298 | uint64_t FSbase;
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| 299 | uint64_t GSbase;
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| 300 | uint64_t efer;
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| 301 | /** @} */
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| 302 |
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| 303 | /** The XCR0 register. */
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| 304 | uint64_t xcr0;
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| 305 | /** The mask to pass to XSAVE/XRSTOR in EDX:EAX. If zero we use
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| 306 | * FXSAVE/FXRSTOR (since bit 0 will always be set, we only need to test it). */
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| 307 | uint64_t fXStateMask;
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| 308 |
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| 309 | /* padding to get 64byte aligned size */
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| 310 | uint8_t auPadding[24];
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| 311 | #if HC_ARCH_BITS != 64
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| 312 | # error HC_ARCH_BITS not defined or unsupported
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| 313 | #endif
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| 314 | } CPUMHOSTCTX;
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| 315 | #ifndef VBOX_FOR_DTRACE_LIB
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| 316 | AssertCompileSizeAlignment(CPUMHOSTCTX, 64);
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| 317 | #endif
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| 318 | /** Pointer to the saved host CPU state. */
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| 319 | typedef CPUMHOSTCTX *PCPUMHOSTCTX;
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| 320 |
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| 321 |
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| 322 | /**
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| 323 | * The hypervisor context CPU state (just DRx left now).
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| 324 | */
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| 325 | typedef struct CPUMHYPERCTX
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| 326 | {
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| 327 | /** Debug registers.
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| 328 | * @remarks DR4 and DR5 should not be used since they are aliases for
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| 329 | * DR6 and DR7 respectively on both AMD and Intel CPUs.
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| 330 | * @remarks DR8-15 are currently not supported by AMD or Intel, so
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| 331 | * neither do we.
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| 332 | */
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| 333 | uint64_t dr[8];
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| 334 | /** @todo eliminiate the rest. */
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| 335 | uint64_t cr3;
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| 336 | uint64_t au64Padding[7];
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| 337 | } CPUMHYPERCTX;
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| 338 | #ifndef VBOX_FOR_DTRACE_LIB
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| 339 | AssertCompileSizeAlignment(CPUMHYPERCTX, 64);
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| 340 | #endif
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| 341 | /** Pointer to the hypervisor context CPU state. */
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| 342 | typedef CPUMHYPERCTX *PCPUMHYPERCTX;
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| 343 |
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| 344 |
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| 345 | /**
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| 346 | * CPUM Data (part of VM)
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| 347 | */
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| 348 | typedef struct CPUM
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| 349 | {
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| 350 | /** Use flags.
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| 351 | * These flags indicates which CPU features the host uses.
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| 352 | */
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| 353 | uint32_t fHostUseFlags;
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| 354 |
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| 355 | /** CR4 mask
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| 356 | * @todo obsolete? */
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| 357 | struct
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| 358 | {
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| 359 | uint32_t AndMask; /**< @todo Move these to the per-CPU structure and fix the switchers. Saves a register! */
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| 360 | uint32_t OrMask;
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| 361 | } CR4;
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| 362 |
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| 363 | /** The (more) portable CPUID level. */
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| 364 | uint8_t u8PortableCpuIdLevel;
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| 365 | /** Indicates that a state restore is pending.
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| 366 | * This is used to verify load order dependencies (PGM). */
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| 367 | bool fPendingRestore;
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| 368 | uint8_t abPadding0[2];
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| 369 |
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| 370 | /** XSAVE/XRTOR components we can expose to the guest mask. */
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| 371 | uint64_t fXStateGuestMask;
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| 372 | /** XSAVE/XRSTOR host mask. Only state components in this mask can be exposed
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| 373 | * to the guest. This is 0 if no XSAVE/XRSTOR bits can be exposed. */
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| 374 | uint64_t fXStateHostMask;
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| 375 |
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| 376 | #if defined(RT_ARCH_X86) || defined(RT_ARCH_AMD64)
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| 377 | /** The host MXCSR mask (determined at init). */
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| 378 | uint32_t fHostMxCsrMask;
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| 379 | #else
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| 380 | uint32_t u32UnusedOnNonX86;
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| 381 | #endif
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| 382 | uint8_t abPadding1[4];
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| 383 |
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| 384 | /** Random value we store in the reserved RFLAGS bits we don't use ourselves so
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| 385 | * we can detect corruption. */
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| 386 | uint64_t fReservedRFlagsCookie;
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| 387 |
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| 388 | /** Align to 64-byte boundary. */
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| 389 | uint8_t abPadding2[16];
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| 390 |
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| 391 | /** Host CPU feature information.
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| 392 | * Externaly visible via the VM structure, aligned on 64-byte boundrary. */
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| 393 | CPUMFEATURES HostFeatures;
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| 394 | /** Guest CPU feature information.
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| 395 | * Externaly visible via that VM structure, aligned with HostFeatures. */
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| 396 | CPUMFEATURES GuestFeatures;
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| 397 | /** Guest CPU info. */
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| 398 | CPUMINFO GuestInfo;
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| 399 |
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| 400 | /** The standard set of CpuId leaves. */
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| 401 | CPUMCPUID aGuestCpuIdPatmStd[6];
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|---|
| 402 | /** The extended set of CpuId leaves. */
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|---|
| 403 | CPUMCPUID aGuestCpuIdPatmExt[10];
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|---|
| 404 | /** The centaur set of CpuId leaves. */
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|---|
| 405 | CPUMCPUID aGuestCpuIdPatmCentaur[4];
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|---|
| 406 |
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|---|
| 407 | /** @name MSR statistics.
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|---|
| 408 | * @{ */
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|---|
| 409 | STAMCOUNTER cMsrWrites;
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|---|
| 410 | STAMCOUNTER cMsrWritesToIgnoredBits;
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|---|
| 411 | STAMCOUNTER cMsrWritesRaiseGp;
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|---|
| 412 | STAMCOUNTER cMsrWritesUnknown;
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|---|
| 413 | STAMCOUNTER cMsrReads;
|
|---|
| 414 | STAMCOUNTER cMsrReadsRaiseGp;
|
|---|
| 415 | STAMCOUNTER cMsrReadsUnknown;
|
|---|
| 416 | /** @} */
|
|---|
| 417 | } CPUM;
|
|---|
| 418 | #ifndef VBOX_FOR_DTRACE_LIB
|
|---|
| 419 | AssertCompileMemberOffset(CPUM, HostFeatures, 64);
|
|---|
| 420 | AssertCompileMemberOffset(CPUM, GuestFeatures, 112);
|
|---|
| 421 | #endif
|
|---|
| 422 | /** Pointer to the CPUM instance data residing in the shared VM structure. */
|
|---|
| 423 | typedef CPUM *PCPUM;
|
|---|
| 424 |
|
|---|
| 425 | /**
|
|---|
| 426 | * CPUM Data (part of VMCPU)
|
|---|
| 427 | */
|
|---|
| 428 | typedef struct CPUMCPU
|
|---|
| 429 | {
|
|---|
| 430 | /** Guest context.
|
|---|
| 431 | * Aligned on a 64-byte boundary. */
|
|---|
| 432 | CPUMCTX Guest;
|
|---|
| 433 | /** Guest context - misc MSRs
|
|---|
| 434 | * Aligned on a 64-byte boundary. */
|
|---|
| 435 | CPUMCTXMSRS GuestMsrs;
|
|---|
| 436 |
|
|---|
| 437 | /** Nested VMX: VMX-preemption timer. */
|
|---|
| 438 | TMTIMERHANDLE hNestedVmxPreemptTimer;
|
|---|
| 439 |
|
|---|
| 440 | /** Use flags.
|
|---|
| 441 | * These flags indicates both what is to be used and what has been used. */
|
|---|
| 442 | uint32_t fUseFlags;
|
|---|
| 443 |
|
|---|
| 444 | /** Changed flags.
|
|---|
| 445 | * These flags indicates to REM (and others) which important guest
|
|---|
| 446 | * registers which has been changed since last time the flags were cleared.
|
|---|
| 447 | * See the CPUM_CHANGED_* defines for what we keep track of.
|
|---|
| 448 | *
|
|---|
| 449 | * @todo Obsolete, but will probably be refactored so keep it for reference. */
|
|---|
| 450 | uint32_t fChanged;
|
|---|
| 451 |
|
|---|
| 452 | /** Temporary storage for the return code of the function called in the
|
|---|
| 453 | * 32-64 switcher. */
|
|---|
| 454 | uint32_t u32RetCode;
|
|---|
| 455 |
|
|---|
| 456 | /** Whether the X86_CPUID_FEATURE_EDX_APIC and X86_CPUID_AMD_FEATURE_EDX_APIC
|
|---|
| 457 | * (?) bits are visible or not. (The APIC is responsible for setting this
|
|---|
| 458 | * when loading state, so we won't save it.) */
|
|---|
| 459 | bool fCpuIdApicFeatureVisible;
|
|---|
| 460 |
|
|---|
| 461 | /** Align the next member on a 64-byte boundary. */
|
|---|
| 462 | uint8_t abPadding2[64 - 8 - 4*3 - 1];
|
|---|
| 463 |
|
|---|
| 464 | /** Saved host context. Only valid while inside RC or HM contexts.
|
|---|
| 465 | * Must be aligned on a 64-byte boundary. */
|
|---|
| 466 | CPUMHOSTCTX Host;
|
|---|
| 467 | /** Old hypervisor context, only used for combined DRx values now.
|
|---|
| 468 | * Must be aligned on a 64-byte boundary. */
|
|---|
| 469 | CPUMHYPERCTX Hyper;
|
|---|
| 470 |
|
|---|
| 471 | #ifdef VBOX_WITH_CRASHDUMP_MAGIC
|
|---|
| 472 | uint8_t aMagic[56];
|
|---|
| 473 | uint64_t uMagic;
|
|---|
| 474 | #endif
|
|---|
| 475 | } CPUMCPU;
|
|---|
| 476 | #ifndef VBOX_FOR_DTRACE_LIB
|
|---|
| 477 | AssertCompileMemberAlignment(CPUMCPU, Host, 64);
|
|---|
| 478 | #endif
|
|---|
| 479 | /** Pointer to the CPUMCPU instance data residing in the shared VMCPU structure. */
|
|---|
| 480 | typedef CPUMCPU *PCPUMCPU;
|
|---|
| 481 |
|
|---|
| 482 | #ifndef VBOX_FOR_DTRACE_LIB
|
|---|
| 483 | RT_C_DECLS_BEGIN
|
|---|
| 484 |
|
|---|
| 485 | PCPUMCPUIDLEAF cpumCpuIdGetLeaf(PVM pVM, uint32_t uLeaf);
|
|---|
| 486 | PCPUMCPUIDLEAF cpumCpuIdGetLeafEx(PVM pVM, uint32_t uLeaf, uint32_t uSubLeaf, bool *pfExactSubLeafHit);
|
|---|
| 487 | PCPUMCPUIDLEAF cpumCpuIdGetLeafInt(PCPUMCPUIDLEAF paLeaves, uint32_t cLeaves, uint32_t uLeaf, uint32_t uSubLeaf);
|
|---|
| 488 | PCPUMCPUIDLEAF cpumCpuIdEnsureSpace(PVM pVM, PCPUMCPUIDLEAF *ppaLeaves, uint32_t cLeaves);
|
|---|
| 489 | # ifdef VBOX_STRICT
|
|---|
| 490 | void cpumCpuIdAssertOrder(PCPUMCPUIDLEAF paLeaves, uint32_t cLeaves);
|
|---|
| 491 | # endif
|
|---|
| 492 | int cpumCpuIdExplodeFeaturesX86(PCCPUMCPUIDLEAF paLeaves, uint32_t cLeaves, PCCPUMMSRS pMsrs,
|
|---|
| 493 | PCPUMFEATURES pFeatures);
|
|---|
| 494 |
|
|---|
| 495 | # ifdef IN_RING3
|
|---|
| 496 | int cpumR3DbgInit(PVM pVM);
|
|---|
| 497 | int cpumR3InitCpuIdAndMsrs(PVM pVM, PCCPUMMSRS pHostMsrs);
|
|---|
| 498 | void cpumR3InitVmxGuestFeaturesAndMsrs(PVM pVM, PCFGMNODE pCpumCfg, PCVMXMSRS pHostVmxMsrs,
|
|---|
| 499 | PVMXMSRS pGuestVmxMsrs);
|
|---|
| 500 | void cpumR3CpuIdRing3InitDone(PVM pVM);
|
|---|
| 501 | void cpumR3SaveCpuId(PVM pVM, PSSMHANDLE pSSM);
|
|---|
| 502 | int cpumR3LoadCpuId(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion, PCCPUMMSRS pGuestMsrs);
|
|---|
| 503 | int cpumR3LoadCpuIdPre32(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion);
|
|---|
| 504 | DECLCALLBACK(void) cpumR3CpuIdInfo(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
|
|---|
| 505 |
|
|---|
| 506 | int cpumR3DbGetCpuInfo(const char *pszName, PCPUMINFO pInfo);
|
|---|
| 507 | int cpumR3MsrRangesInsert(PVM pVM, PCPUMMSRRANGE *ppaMsrRanges, uint32_t *pcMsrRanges, PCCPUMMSRRANGE pNewRange);
|
|---|
| 508 | int cpumR3MsrReconcileWithCpuId(PVM pVM);
|
|---|
| 509 | int cpumR3MsrApplyFudge(PVM pVM);
|
|---|
| 510 | int cpumR3MsrRegStats(PVM pVM);
|
|---|
| 511 | int cpumR3MsrStrictInitChecks(void);
|
|---|
| 512 | PCPUMMSRRANGE cpumLookupMsrRange(PVM pVM, uint32_t idMsr);
|
|---|
| 513 | # endif
|
|---|
| 514 |
|
|---|
| 515 | # ifdef IN_RC
|
|---|
| 516 | DECLASM(int) cpumHandleLazyFPUAsm(PCPUMCPU pCPUM);
|
|---|
| 517 | # endif
|
|---|
| 518 |
|
|---|
| 519 | # ifdef IN_RING0
|
|---|
| 520 | DECLASM(int) cpumR0SaveHostRestoreGuestFPUState(PCPUMCPU pCPUM);
|
|---|
| 521 | DECLASM(void) cpumR0SaveGuestRestoreHostFPUState(PCPUMCPU pCPUM);
|
|---|
| 522 | # if ARCH_BITS == 32 && defined(VBOX_WITH_64_BITS_GUESTS)
|
|---|
| 523 | DECLASM(void) cpumR0RestoreHostFPUState(PCPUMCPU pCPUM);
|
|---|
| 524 | # endif
|
|---|
| 525 | # endif
|
|---|
| 526 |
|
|---|
| 527 | # if defined(IN_RC) || defined(IN_RING0)
|
|---|
| 528 | DECLASM(int) cpumRZSaveHostFPUState(PCPUMCPU pCPUM);
|
|---|
| 529 | DECLASM(void) cpumRZSaveGuestFpuState(PCPUMCPU pCPUM, bool fLeaveFpuAccessible);
|
|---|
| 530 | DECLASM(void) cpumRZSaveGuestSseRegisters(PCPUMCPU pCPUM);
|
|---|
| 531 | DECLASM(void) cpumRZSaveGuestAvxRegisters(PCPUMCPU pCPUM);
|
|---|
| 532 | # endif
|
|---|
| 533 |
|
|---|
| 534 | RT_C_DECLS_END
|
|---|
| 535 | #endif /* !VBOX_FOR_DTRACE_LIB */
|
|---|
| 536 |
|
|---|
| 537 | /** @} */
|
|---|
| 538 |
|
|---|
| 539 | #endif /* !VMM_INCLUDED_SRC_include_CPUMInternal_h */
|
|---|
| 540 |
|
|---|
