CPUMInternal.h@ 107570

Last change on this file since 107570 was 107570, checked in by vboxsync, 10 days ago
VMM/CPUM: Report the host CPU microcode revision number to the guest when on an amd64 host. jiraref:VBP-947
Property svn:eol-style set to `native` Property svn:keywords set to `Id Revision`
File size: 19.6 KB

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1	/* $Id: CPUMInternal.h 107570 2025-01-09 09:23:18Z vboxsync $ */
2	/** @file
3	* CPUM - Internal header file.
4	*/
5
6	/*
7	* Copyright (C) 2006-2024 Oracle and/or its affiliates.
8	*
9	* This file is part of VirtualBox base platform packages, as
10	* available from https://www.virtualbox.org.
11	*
12	* This program is free software; you can redistribute it and/or
13	* modify it under the terms of the GNU General Public License
14	* as published by the Free Software Foundation, in version 3 of the
15	* License.
16	*
17	* This program is distributed in the hope that it will be useful, but
18	* WITHOUT ANY WARRANTY; without even the implied warranty of
19	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
20	* General Public License for more details.
21	*
22	* You should have received a copy of the GNU General Public License
23	* along with this program; if not, see <https://www.gnu.org/licenses>.
24	*
25	* SPDX-License-Identifier: GPL-3.0-only
26	*/
27
28	#ifndef VMM_INCLUDED_SRC_include_CPUMInternal_h
29	#define VMM_INCLUDED_SRC_include_CPUMInternal_h
30	#ifndef RT_WITHOUT_PRAGMA_ONCE
31	# pragma once
32	#endif
33
34	#ifndef VBOX_FOR_DTRACE_LIB
35	# include <VBox/cdefs.h>
36	# include <VBox/types.h>
37	# include <VBox/vmm/stam.h>
38	# include <iprt/x86.h>
39	# include <VBox/vmm/pgm.h>
40	#else
41	# pragma D depends_on library x86.d
42	# pragma D depends_on library cpumctx.d
43	# pragma D depends_on library cpum.d
44
45	/* Some fudging. */
46	typedef uint64_t STAMCOUNTER;
47	#endif
48
49
50
51
52	/** @defgroup grp_cpum_int Internals
53	* @ingroup grp_cpum
54	* @internal
55	* @{
56	*/
57
58	/** Use flags (CPUM::fUseFlags).
59	* (Don't forget to sync this with CPUMInternal.mac !)
60	* @note Was part of saved state (6.1 and earlier).
61	* @{ */
62	/** Indicates that we've saved the host FPU, SSE, whatever state and that it
63	* needs to be restored. */
64	#define CPUM_USED_FPU_HOST RT_BIT(0)
65	/** Indicates that we've loaded the guest FPU, SSE, whatever state and that it
66	* needs to be saved.
67	* @note Mirrored in CPUMCTX::fUsedFpuGuest for the HM switcher code. */
68	#define CPUM_USED_FPU_GUEST RT_BIT(10)
69	/** Used the guest FPU, SSE or such stuff since last we were in REM.
70	* REM syncing is clearing this, lazy FPU is setting it. */
71	#define CPUM_USED_FPU_SINCE_REM RT_BIT(1)
72	/** The XMM state was manually restored. (AMD only) */
73	#define CPUM_USED_MANUAL_XMM_RESTORE RT_BIT(2)
74
75	/** Host OS is using SYSENTER and we must NULL the CS. */
76	#define CPUM_USE_SYSENTER RT_BIT(3)
77	/** Host OS is using SYSENTER and we must NULL the CS. */
78	#define CPUM_USE_SYSCALL RT_BIT(4)
79
80	/** Debug registers are used by host and that DR7 and DR6 must be saved and
81	* disabled when switching to raw-mode. */
82	#define CPUM_USE_DEBUG_REGS_HOST RT_BIT(5)
83	/** Records that we've saved the host DRx registers.
84	* In ring-0 this means all (DR0-7), while in raw-mode context this means DR0-3
85	* since DR6 and DR7 are covered by CPUM_USE_DEBUG_REGS_HOST. */
86	#define CPUM_USED_DEBUG_REGS_HOST RT_BIT(6)
87	/** Set to indicate that we should save host DR0-7 and load the hypervisor debug
88	* registers in the raw-mode world switchers. (See CPUMRecalcHyperDRx.) */
89	#define CPUM_USE_DEBUG_REGS_HYPER RT_BIT(7)
90	/** Used in ring-0 to indicate that we have loaded the hypervisor debug
91	* registers. */
92	#define CPUM_USED_DEBUG_REGS_HYPER RT_BIT(8)
93	/** Used in ring-0 to indicate that we have loaded the guest debug
94	* registers (DR0-3 and maybe DR6) for direct use by the guest.
95	* DR7 (and AMD-V DR6) are handled via the VMCB. */
96	#define CPUM_USED_DEBUG_REGS_GUEST RT_BIT(9)
97
98	/** Host CPU requires fxsave/fxrstor leaky bit handling. */
99	#define CPUM_USE_FFXSR_LEAKY RT_BIT(19)
100	/** Set if the VM supports long-mode. */
101	#define CPUM_USE_SUPPORTS_LONGMODE RT_BIT(20)
102	/** @} */
103
104
105	/** @name CPUM Saved State Version.
106	* @{ */
107	/** The current saved state version.
108	* @todo When bumping to next version, add CPUMCTX::enmHwVirt and
109	* uMicrocodeRevision to the saved state. */
110	#define CPUM_SAVED_STATE_VERSION CPUM_SAVED_STATE_VERSION_HWVIRT_VMX_4
111	/** The saved state version with u32RestoreProcCtls2 for Nested Microsoft
112	* Hyper-V. */
113	#define CPUM_SAVED_STATE_VERSION_HWVIRT_VMX_4 23
114	/** The saved state version with more virtual VMCS fields (HLAT prefix size,
115	* PCONFIG-exiting bitmap, HLAT ptr, VM-exit ctls2) and a CPUMCTX field (VM-exit
116	* ctls2 MSR). */
117	#define CPUM_SAVED_STATE_VERSION_HWVIRT_VMX_3 22
118	/** The saved state version with PAE PDPEs added. */
119	#define CPUM_SAVED_STATE_VERSION_PAE_PDPES 21
120	/** The saved state version with more virtual VMCS fields and CPUMCTX VMX fields. */
121	#define CPUM_SAVED_STATE_VERSION_HWVIRT_VMX_2 20
122	/** The saved state version including VMX hardware virtualization state. */
123	#define CPUM_SAVED_STATE_VERSION_HWVIRT_VMX 19
124	/** The saved state version including SVM hardware virtualization state. */
125	#define CPUM_SAVED_STATE_VERSION_HWVIRT_SVM 18
126	/** The saved state version including XSAVE state. */
127	#define CPUM_SAVED_STATE_VERSION_XSAVE 17
128	/** The saved state version with good CPUID leaf count. */
129	#define CPUM_SAVED_STATE_VERSION_GOOD_CPUID_COUNT 16
130	/** CPUID changes with explode forgetting to update the leaf count on
131	* restore, resulting in garbage being saved restoring+saving old states). */
132	#define CPUM_SAVED_STATE_VERSION_BAD_CPUID_COUNT 15
133	/** The saved state version before the CPUIDs changes. */
134	#define CPUM_SAVED_STATE_VERSION_PUT_STRUCT 14
135	/** The saved state version before using SSMR3PutStruct. */
136	#define CPUM_SAVED_STATE_VERSION_MEM 13
137	/** The saved state version before introducing the MSR size field. */
138	#define CPUM_SAVED_STATE_VERSION_NO_MSR_SIZE 12
139	/** The saved state version of 3.2, 3.1 and 3.3 trunk before the hidden
140	* selector register change (CPUM_CHANGED_HIDDEN_SEL_REGS_INVALID). */
141	#define CPUM_SAVED_STATE_VERSION_VER3_2 11
142	/** The saved state version of 3.0 and 3.1 trunk before the teleportation
143	* changes. */
144	#define CPUM_SAVED_STATE_VERSION_VER3_0 10
145	/** The saved state version for the 2.1 trunk before the MSR changes. */
146	#define CPUM_SAVED_STATE_VERSION_VER2_1_NOMSR 9
147	/** The saved state version of 2.0, used for backwards compatibility. */
148	#define CPUM_SAVED_STATE_VERSION_VER2_0 8
149	/** The saved state version of 1.6, used for backwards compatibility. */
150	#define CPUM_SAVED_STATE_VERSION_VER1_6 6
151	/** @} */
152
153
154	/** @name XSAVE limits.
155	* @{ */
156	/** Max size we accept for the XSAVE area.
157	* @see CPUMCTX::abXSave */
158	#define CPUM_MAX_XSAVE_AREA_SIZE (0x4000 - 0x300)
159	/* Min size we accept for the XSAVE area. */
160	#define CPUM_MIN_XSAVE_AREA_SIZE 0x240
161	/** @} */
162
163
164	/**
165	* CPU info
166	*/
167	typedef struct CPUMINFO
168	{
169	/** The number of MSR ranges (CPUMMSRRANGE) in the array pointed to below. */
170	uint32_t cMsrRanges;
171	/** Mask applied to ECX before looking up the MSR for a RDMSR/WRMSR
172	* instruction. Older hardware has been observed to ignore higher bits. */
173	uint32_t fMsrMask;
174
175	/** MXCSR mask. */
176	uint32_t fMxCsrMask;
177
178	/** The number of CPUID leaves (CPUMCPUIDLEAF) in the array pointed to below. */
179	uint32_t cCpuIdLeaves;
180	/** The index of the first extended CPUID leaf in the array.
181	* Set to cCpuIdLeaves if none present. */
182	uint32_t iFirstExtCpuIdLeaf;
183	/** How to handle unknown CPUID leaves. */
184	CPUMUNKNOWNCPUID enmUnknownCpuIdMethod;
185	/** For use with CPUMUNKNOWNCPUID_DEFAULTS (DB & VM),
186	* CPUMUNKNOWNCPUID_LAST_STD_LEAF (VM) and CPUMUNKNOWNCPUID_LAST_STD_LEAF_WITH_ECX (VM). */
187	CPUMCPUID DefCpuId;
188
189	/** Scalable bus frequency used for reporting other frequencies. */
190	uint64_t uScalableBusFreq;
191
192	/** The microcode revision.
193	* UINT32_MAX if the one from the CPU database entry is to be used.
194	* @see /CPUM/GuestMicrocodeRevision in CFGM. */
195	uint32_t uMicrocodeRevision;
196	uint32_t uPadding;
197
198	/** Pointer to the MSR ranges (for compatibility with old hyper heap code). */
199	R3PTRTYPE(PCPUMMSRRANGE) paMsrRangesR3;
200	/** Pointer to the CPUID leaves (for compatibility with old hyper heap code). */
201	R3PTRTYPE(PCPUMCPUIDLEAF) paCpuIdLeavesR3;
202
203	/** CPUID leaves. */
204	CPUMCPUIDLEAF aCpuIdLeaves[256];
205	/** MSR ranges.
206	* @todo This is insane, so might want to move this into a separate
207	* allocation. The insanity is mainly for more recent AMD CPUs. */
208	CPUMMSRRANGE aMsrRanges[8192];
209	} CPUMINFO;
210	/** Pointer to a CPU info structure. */
211	typedef CPUMINFO *PCPUMINFO;
212	/** Pointer to a const CPU info structure. */
213	typedef CPUMINFO const *CPCPUMINFO;
214
215
216	/**
217	* The saved host CPU state.
218	*/
219	typedef struct CPUMHOSTCTX
220	{
221	/** The extended state (FPU/SSE/AVX/AVX-2/XXXX). Must be aligned on 64 bytes. */
222	union /* no tag */
223	{
224	X86XSAVEAREA XState;
225	/** Byte view for simple indexing and space allocation.
226	* @note Must match or exceed the size of CPUMCTX::abXState. */
227	uint8_t abXState[0x4000 - 0x300];
228	} CPUM_UNION_NM(u);
229
230	/** General purpose register, selectors, flags and more
231	* @{ */
232	/** General purpose register ++
233	* { */
234	/uint64_t rax; - scratch/
235	uint64_t rbx;
236	/uint64_t rcx; - scratch/
237	/uint64_t rdx; - scratch/
238	uint64_t rdi;
239	uint64_t rsi;
240	uint64_t rbp;
241	uint64_t rsp;
242	/uint64_t r8; - scratch/
243	/uint64_t r9; - scratch/
244	uint64_t r10;
245	uint64_t r11;
246	uint64_t r12;
247	uint64_t r13;
248	uint64_t r14;
249	uint64_t r15;
250	/uint64_t rip; - scratch/
251	uint64_t rflags;
252	/** @} */
253
254	/** Selector registers
255	* @{ */
256	RTSEL ss;
257	RTSEL ssPadding;
258	RTSEL gs;
259	RTSEL gsPadding;
260	RTSEL fs;
261	RTSEL fsPadding;
262	RTSEL es;
263	RTSEL esPadding;
264	RTSEL ds;
265	RTSEL dsPadding;
266	RTSEL cs;
267	RTSEL csPadding;
268	/** @} */
269
270	/** Control registers.
271	* @{ */
272	/** The CR0 FPU state in HM mode. */
273	uint64_t cr0;
274	/uint64_t cr2; - scratch/
275	uint64_t cr3;
276	uint64_t cr4;
277	uint64_t cr8;
278	/** @} */
279
280	/** Debug registers.
281	* @{ */
282	uint64_t dr0;
283	uint64_t dr1;
284	uint64_t dr2;
285	uint64_t dr3;
286	uint64_t dr6;
287	uint64_t dr7;
288	/** @} */
289
290	/** Global Descriptor Table register. */
291	X86XDTR64 gdtr;
292	uint16_t gdtrPadding;
293	/** Interrupt Descriptor Table register. */
294	X86XDTR64 idtr;
295	uint16_t idtrPadding;
296	/** The task register. */
297	RTSEL ldtr;
298	RTSEL ldtrPadding;
299	/** The task register. */
300	RTSEL tr;
301	RTSEL trPadding;
302
303	/** MSRs
304	* @{ */
305	CPUMSYSENTER SysEnter;
306	uint64_t FSbase;
307	uint64_t GSbase;
308	uint64_t efer;
309	/** @} */
310
311	/** The XCR0 register. */
312	uint64_t xcr0;
313	/** The mask to pass to XSAVE/XRSTOR in EDX:EAX. If zero we use
314	* FXSAVE/FXRSTOR (since bit 0 will always be set, we only need to test it). */
315	uint64_t fXStateMask;
316
317	/* padding to get 64byte aligned size */
318	uint8_t auPadding[24];
319	#if HC_ARCH_BITS != 64
320	# error HC_ARCH_BITS not defined or unsupported
321	#endif
322	} CPUMHOSTCTX;
323	#ifndef VBOX_FOR_DTRACE_LIB
324	AssertCompileSizeAlignment(CPUMHOSTCTX, 64);
325	#endif
326	/** Pointer to the saved host CPU state. */
327	typedef CPUMHOSTCTX *PCPUMHOSTCTX;
328
329
330	/**
331	* The hypervisor context CPU state (just DRx left now).
332	*/
333	typedef struct CPUMHYPERCTX
334	{
335	/** Debug registers.
336	* @remarks DR4 and DR5 should not be used since they are aliases for
337	* DR6 and DR7 respectively on both AMD and Intel CPUs.
338	* @remarks DR8-15 are currently not supported by AMD or Intel, so
339	* neither do we.
340	*/
341	uint64_t dr[8];
342	/** @todo eliminiate the rest. */
343	uint64_t cr3;
344	uint64_t au64Padding[7];
345	} CPUMHYPERCTX;
346	#ifndef VBOX_FOR_DTRACE_LIB
347	AssertCompileSizeAlignment(CPUMHYPERCTX, 64);
348	#endif
349	/** Pointer to the hypervisor context CPU state. */
350	typedef CPUMHYPERCTX *PCPUMHYPERCTX;
351
352
353	/**
354	* CPUM Data (part of VM)
355	*/
356	typedef struct CPUM
357	{
358	/** Use flags.
359	* These flags indicates which CPU features the host uses.
360	*/
361	uint32_t fHostUseFlags;
362
363	/** The (more) portable CPUID level. */
364	uint8_t u8PortableCpuIdLevel;
365	/** Indicates that a state restore is pending.
366	* This is used to verify load order dependencies (PGM). */
367	bool fPendingRestore;
368	/** Whether MTRR reads report valid memory types for memory regions. */
369	bool fMtrrRead;
370	/** Whether the guest's writes to MTRRs are implemented. */
371	bool fMtrrWrite;
372
373	/** XSAVE/XRTOR components we can expose to the guest mask. */
374	uint64_t fXStateGuestMask;
375	/** XSAVE/XRSTOR host mask. Only state components in this mask can be exposed
376	* to the guest. This is 0 if no XSAVE/XRSTOR bits can be exposed. */
377	uint64_t fXStateHostMask;
378
379	#if defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)
380	/** The host MXCSR mask (determined at init). */
381	uint32_t fHostMxCsrMask;
382	#else
383	uint32_t u32UnusedOnNonX86;
384	#endif
385	uint8_t abPadding1[4];
386
387	/** Random value we store in the reserved RFLAGS bits we don't use ourselves so
388	* we can detect corruption. */
389	uint64_t fReservedRFlagsCookie;
390
391	/** Align to 64-byte boundary. */
392	uint8_t abPadding2[16+8];
393
394	/** Host CPU feature information.
395	* Externaly visible via the VM structure, aligned on 64-byte boundrary. */
396	CPUMFEATURES HostFeatures;
397	/** Guest CPU feature information.
398	* Externaly visible via that VM structure, aligned with HostFeatures. */
399	CPUMFEATURES GuestFeatures;
400	/** Guest CPU info. */
401	CPUMINFO GuestInfo;
402
403	/** The standard set of CpuId leaves. */
404	CPUMCPUID aGuestCpuIdPatmStd[6];
405	/** The extended set of CpuId leaves. */
406	CPUMCPUID aGuestCpuIdPatmExt[10];
407	/** The centaur set of CpuId leaves. */
408	CPUMCPUID aGuestCpuIdPatmCentaur[4];
409
410	/** @name MSR statistics.
411	* @{ */
412	STAMCOUNTER cMsrWrites;
413	STAMCOUNTER cMsrWritesToIgnoredBits;
414	STAMCOUNTER cMsrWritesRaiseGp;
415	STAMCOUNTER cMsrWritesUnknown;
416	STAMCOUNTER cMsrReads;
417	STAMCOUNTER cMsrReadsRaiseGp;
418	STAMCOUNTER cMsrReadsUnknown;
419	/** @} */
420	} CPUM;
421	#ifndef VBOX_FOR_DTRACE_LIB
422	AssertCompileMemberOffset(CPUM, HostFeatures, 64);
423	AssertCompileMemberOffset(CPUM, GuestFeatures, 112);
424	#endif
425	/** Pointer to the CPUM instance data residing in the shared VM structure. */
426	typedef CPUM *PCPUM;
427
428	/**
429	* CPUM Data (part of VMCPU)
430	*/
431	typedef struct CPUMCPU
432	{
433	/** Guest context.
434	* Aligned on a 64-byte boundary. */
435	CPUMCTX Guest;
436	/** Guest context - misc MSRs
437	* Aligned on a 64-byte boundary. */
438	CPUMCTXMSRS GuestMsrs;
439
440	/** Nested VMX: VMX-preemption timer. */
441	TMTIMERHANDLE hNestedVmxPreemptTimer;
442
443	/** Use flags.
444	* These flags indicates both what is to be used and what has been used. */
445	uint32_t fUseFlags;
446
447	/** Changed flags.
448	* These flags indicates to REM (and others) which important guest
449	* registers which has been changed since last time the flags were cleared.
450	* See the CPUM_CHANGED_* defines for what we keep track of.
451	*
452	* @todo Obsolete, but will probably be refactored so keep it for reference. */
453	uint32_t fChanged;
454
455	/** Temporary storage for the return code of the function called in the
456	* 32-64 switcher. */
457	uint32_t u32RetCode;
458
459	/** Whether the X86_CPUID_FEATURE_EDX_APIC and X86_CPUID_AMD_FEATURE_EDX_APIC
460	* (?) bits are visible or not. (The APIC is responsible for setting this
461	* when loading state, so we won't save it.) */
462	bool fCpuIdApicFeatureVisible;
463
464	/** Align the next member on a 64-byte boundary. */
465	uint8_t abPadding2[64 - 8 - 4*3 - 1];
466
467	/** Saved host context. Only valid while inside RC or HM contexts.
468	* Must be aligned on a 64-byte boundary. */
469	CPUMHOSTCTX Host;
470	/** Old hypervisor context, only used for combined DRx values now.
471	* Must be aligned on a 64-byte boundary. */
472	CPUMHYPERCTX Hyper;
473
474	#ifdef VBOX_WITH_CRASHDUMP_MAGIC
475	uint8_t aMagic[56];
476	uint64_t uMagic;
477	#endif
478	} CPUMCPU;
479	#ifndef VBOX_FOR_DTRACE_LIB
480	AssertCompileMemberAlignment(CPUMCPU, Host, 64);
481	#endif
482	/** Pointer to the CPUMCPU instance data residing in the shared VMCPU structure. */
483	typedef CPUMCPU *PCPUMCPU;
484
485	#ifndef VBOX_FOR_DTRACE_LIB
486	RT_C_DECLS_BEGIN
487
488	PCPUMCPUIDLEAF cpumCpuIdGetLeaf(PVM pVM, uint32_t uLeaf);
489	PCPUMCPUIDLEAF cpumCpuIdGetLeafEx(PVM pVM, uint32_t uLeaf, uint32_t uSubLeaf, bool *pfExactSubLeafHit);
490	PCPUMCPUIDLEAF cpumCpuIdGetLeafInt(PCPUMCPUIDLEAF paLeaves, uint32_t cLeaves, uint32_t uLeaf, uint32_t uSubLeaf);
491	PCPUMCPUIDLEAF cpumCpuIdEnsureSpace(PVM pVM, PCPUMCPUIDLEAF *ppaLeaves, uint32_t cLeaves);
492	# ifdef VBOX_STRICT
493	void cpumCpuIdAssertOrder(PCPUMCPUIDLEAF paLeaves, uint32_t cLeaves);
494	# endif
495	int cpumCpuIdExplodeFeaturesX86(PCCPUMCPUIDLEAF paLeaves, uint32_t cLeaves, PCCPUMMSRS pMsrs,
496	PCPUMFEATURES pFeatures);
497
498	# ifdef IN_RING3
499	int cpumR3DbgInit(PVM pVM);
500	int cpumR3InitCpuIdAndMsrs(PVM pVM, PCCPUMMSRS pHostMsrs);
501	void cpumR3InitVmxGuestFeaturesAndMsrs(PVM pVM, PCFGMNODE pCpumCfg, PCVMXMSRS pHostVmxMsrs,
502	PVMXMSRS pGuestVmxMsrs);
503	void cpumR3CpuIdRing3InitDone(PVM pVM);
504	void cpumR3SaveCpuId(PVM pVM, PSSMHANDLE pSSM);
505	int cpumR3LoadCpuId(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion, PCCPUMMSRS pGuestMsrs);
506	int cpumR3LoadCpuIdPre32(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion);
507	DECLCALLBACK(void) cpumR3CpuIdInfo(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
508
509	int cpumR3DbGetCpuInfo(const char *pszName, PCPUMINFO pInfo);
510	int cpumR3MsrRangesInsert(PVM pVM, PCPUMMSRRANGE ppaMsrRanges, uint32_t pcMsrRanges, PCCPUMMSRRANGE pNewRange);
511	int cpumR3MsrReconcileWithCpuId(PVM pVM);
512	int cpumR3MsrApplyFudge(PVM pVM);
513	int cpumR3MsrRegStats(PVM pVM);
514	int cpumR3MsrStrictInitChecks(void);
515	PCPUMMSRRANGE cpumLookupMsrRange(PVM pVM, uint32_t idMsr);
516	# endif
517
518	# ifdef IN_RC
519	DECLASM(int) cpumHandleLazyFPUAsm(PCPUMCPU pCPUM);
520	# endif
521
522	# ifdef IN_RING0
523	DECLASM(int) cpumR0SaveHostRestoreGuestFPUState(PCPUMCPU pCPUM);
524	DECLASM(void) cpumR0SaveGuestRestoreHostFPUState(PCPUMCPU pCPUM);
525	# if ARCH_BITS == 32 && defined(VBOX_WITH_64_BITS_GUESTS)
526	DECLASM(void) cpumR0RestoreHostFPUState(PCPUMCPU pCPUM);
527	# endif
528	# endif
529
530	# if defined(IN_RC) \|\| defined(IN_RING0)
531	DECLASM(int) cpumRZSaveHostFPUState(PCPUMCPU pCPUM);
532	DECLASM(void) cpumRZSaveGuestFpuState(PCPUMCPU pCPUM, bool fLeaveFpuAccessible);
533	DECLASM(void) cpumRZSaveGuestSseRegisters(PCPUMCPU pCPUM);
534	DECLASM(void) cpumRZSaveGuestAvxRegisters(PCPUMCPU pCPUM);
535	# endif
536
537	RT_C_DECLS_END
538	#endif /* !VBOX_FOR_DTRACE_LIB */
539
540	/** @} */
541
542	#endif /* !VMM_INCLUDED_SRC_include_CPUMInternal_h */
543

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