VirtualBox

source: vbox/trunk/src/VBox/VMM/include/CPUMInternal.h@ 107650

Last change on this file since 107650 was 107650, checked in by vboxsync, 8 days ago

VMM/CPUM,++: Made the HostFeatures match the host when targeting x86 guests on arm64 hosts. Merged and deduplicated code targeting x86 & amd64. jiraref:VBP-1470
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File size: 22.8 KB
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1/* $Id: CPUMInternal.h 107650 2025-01-10 13:42:28Z vboxsync $ */
2/** @file
3 * CPUM - Internal header file.
4 */
5
6/*
7 * Copyright (C) 2006-2024 Oracle and/or its affiliates.
8 *
9 * This file is part of VirtualBox base platform packages, as
10 * available from https://www.virtualbox.org.
11 *
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License
14 * as published by the Free Software Foundation, in version 3 of the
15 * License.
16 *
17 * This program is distributed in the hope that it will be useful, but
18 * WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
20 * General Public License for more details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, see <https://www.gnu.org/licenses>.
24 *
25 * SPDX-License-Identifier: GPL-3.0-only
26 */
27
28#ifndef VMM_INCLUDED_SRC_include_CPUMInternal_h
29#define VMM_INCLUDED_SRC_include_CPUMInternal_h
30#ifndef RT_WITHOUT_PRAGMA_ONCE
31# pragma once
32#endif
33
34#ifndef VBOX_FOR_DTRACE_LIB
35# include <VBox/cdefs.h>
36# include <VBox/types.h>
37# include <VBox/vmm/stam.h>
38# include <iprt/x86.h>
39# include <VBox/vmm/pgm.h>
40#else
41# pragma D depends_on library x86.d
42# pragma D depends_on library cpumctx.d
43# pragma D depends_on library cpum.d
44
45/* Some fudging. */
46typedef uint64_t STAMCOUNTER;
47#endif
48
49
50
51
52/** @defgroup grp_cpum_int Internals
53 * @ingroup grp_cpum
54 * @internal
55 * @{
56 */
57
58/** Use flags (CPUM::fUseFlags).
59 * (Don't forget to sync this with CPUMInternal.mac !)
60 * @note Was part of saved state (6.1 and earlier).
61 * @{ */
62#if defined(RT_ARCH_AMD64) || defined(VBOX_VMM_TARGET_X86) /** @todo temporary: */ || defined(VBOX_VMM_TARGET_AGNOSTIC)
63
64/** Indicates that we've saved the host FPU, SSE, whatever state and that it
65 * needs to be restored. */
66#define CPUM_USED_FPU_HOST RT_BIT(0)
67/** Indicates that we've loaded the guest FPU, SSE, whatever state and that it
68 * needs to be saved.
69 * @note Mirrored in CPUMCTX::fUsedFpuGuest for the HM switcher code. */
70#define CPUM_USED_FPU_GUEST RT_BIT(10)
71/** Used the guest FPU, SSE or such stuff since last we were in REM.
72 * REM syncing is clearing this, lazy FPU is setting it. */
73#define CPUM_USED_FPU_SINCE_REM RT_BIT(1)
74/** The XMM state was manually restored. (AMD only) */
75#define CPUM_USED_MANUAL_XMM_RESTORE RT_BIT(2)
76
77/** Host OS is using SYSENTER and we must NULL the CS. */
78#define CPUM_USE_SYSENTER RT_BIT(3)
79/** Host OS is using SYSENTER and we must NULL the CS. */
80#define CPUM_USE_SYSCALL RT_BIT(4)
81
82/** Debug registers are used by host and that DR7 and DR6 must be saved and
83 * disabled when switching to raw-mode. */
84#define CPUM_USE_DEBUG_REGS_HOST RT_BIT(5)
85/** Records that we've saved the host DRx registers.
86 * In ring-0 this means all (DR0-7), while in raw-mode context this means DR0-3
87 * since DR6 and DR7 are covered by CPUM_USE_DEBUG_REGS_HOST. */
88#define CPUM_USED_DEBUG_REGS_HOST RT_BIT(6)
89/** Set to indicate that we should save host DR0-7 and load the hypervisor debug
90 * registers in the raw-mode world switchers. (See CPUMRecalcHyperDRx.) */
91#define CPUM_USE_DEBUG_REGS_HYPER RT_BIT(7)
92/** Used in ring-0 to indicate that we have loaded the hypervisor debug
93 * registers. */
94#define CPUM_USED_DEBUG_REGS_HYPER RT_BIT(8)
95/** Used in ring-0 to indicate that we have loaded the guest debug
96 * registers (DR0-3 and maybe DR6) for direct use by the guest.
97 * DR7 (and AMD-V DR6) are handled via the VMCB. */
98#define CPUM_USED_DEBUG_REGS_GUEST RT_BIT(9)
99
100/** Host CPU requires fxsave/fxrstor leaky bit handling. */
101#define CPUM_USE_FFXSR_LEAKY RT_BIT(19)
102/** Set if the VM supports long-mode. */
103#define CPUM_USE_SUPPORTS_LONGMODE RT_BIT(20)
104
105#endif
106/** @} */
107
108
109/** @name CPUM Saved State Version.
110 * @{ */
111
112/** The current saved state version.
113 * @todo AMD64:When bumping to next version, add CPUMCTX::enmHwVirt and
114 * uMicrocodeRevision to the saved state. */
115#if defined(VBOX_VMM_TARGET_X86)
116# define CPUM_SAVED_STATE_VERSION CPUM_SAVED_STATE_VERSION_HWVIRT_VMX_4
117#elif defined(VBOX_VMM_TARGET_ARMV8)
118# define CPUM_SAVED_STATE_VERSION CPUM_SAVED_STATE_VERSION_ARMV8_V1
119#endif
120
121#if defined(VBOX_VMM_TARGET_X86)
122/** The saved state version with u32RestoreProcCtls2 for Nested Microsoft
123 * Hyper-V. */
124# define CPUM_SAVED_STATE_VERSION_HWVIRT_VMX_4 23
125/** The saved state version with more virtual VMCS fields (HLAT prefix size,
126 * PCONFIG-exiting bitmap, HLAT ptr, VM-exit ctls2) and a CPUMCTX field (VM-exit
127 * ctls2 MSR). */
128# define CPUM_SAVED_STATE_VERSION_HWVIRT_VMX_3 22
129/** The saved state version with PAE PDPEs added. */
130# define CPUM_SAVED_STATE_VERSION_PAE_PDPES 21
131/** The saved state version with more virtual VMCS fields and CPUMCTX VMX fields. */
132# define CPUM_SAVED_STATE_VERSION_HWVIRT_VMX_2 20
133/** The saved state version including VMX hardware virtualization state. */
134# define CPUM_SAVED_STATE_VERSION_HWVIRT_VMX 19
135/** The saved state version including SVM hardware virtualization state. */
136# define CPUM_SAVED_STATE_VERSION_HWVIRT_SVM 18
137/** The saved state version including XSAVE state. */
138# define CPUM_SAVED_STATE_VERSION_XSAVE 17
139/** The saved state version with good CPUID leaf count. */
140# define CPUM_SAVED_STATE_VERSION_GOOD_CPUID_COUNT 16
141/** CPUID changes with explode forgetting to update the leaf count on
142 * restore, resulting in garbage being saved restoring+saving old states). */
143# define CPUM_SAVED_STATE_VERSION_BAD_CPUID_COUNT 15
144/** The saved state version before the CPUIDs changes. */
145# define CPUM_SAVED_STATE_VERSION_PUT_STRUCT 14
146/** The saved state version before using SSMR3PutStruct. */
147# define CPUM_SAVED_STATE_VERSION_MEM 13
148/** The saved state version before introducing the MSR size field. */
149# define CPUM_SAVED_STATE_VERSION_NO_MSR_SIZE 12
150/** The saved state version of 3.2, 3.1 and 3.3 trunk before the hidden
151 * selector register change (CPUM_CHANGED_HIDDEN_SEL_REGS_INVALID). */
152# define CPUM_SAVED_STATE_VERSION_VER3_2 11
153/** The saved state version of 3.0 and 3.1 trunk before the teleportation
154 * changes. */
155# define CPUM_SAVED_STATE_VERSION_VER3_0 10
156/** The saved state version for the 2.1 trunk before the MSR changes. */
157# define CPUM_SAVED_STATE_VERSION_VER2_1_NOMSR 9
158/** The saved state version of 2.0, used for backwards compatibility. */
159# define CPUM_SAVED_STATE_VERSION_VER2_0 8
160/** The saved state version of 1.6, used for backwards compatibility. */
161# define CPUM_SAVED_STATE_VERSION_VER1_6 6
162#endif
163
164#if defined(VBOX_VMM_TARGET_ARMV8)
165/** The initial ARMv8 saved state. */
166# define CPUM_SAVED_STATE_VERSION_ARMV8_V1 1
167#endif
168/** @} */
169
170
171#if defined(RT_ARCH_X86) || defined(RT_ARCH_AMD64) || defined(VBOX_VMM_TARGET_X86)
172/** @name AMD64: XSAVE limits.
173 * @{ */
174/** Max size we accept for the XSAVE area.
175 * @see CPUMCTX::abXSave */
176#define CPUM_MAX_XSAVE_AREA_SIZE (0x4000 - 0x300)
177/* Min size we accept for the XSAVE area. */
178#define CPUM_MIN_XSAVE_AREA_SIZE 0x240
179/** @} */
180#endif
181
182/**
183 * CPU info
184 */
185typedef struct CPUMINFO
186{
187#if defined(VBOX_VMM_TARGET_X86) /** @todo temporary: */ || defined(VBOX_VMM_TARGET_AGNOSTIC)
188 /** The number of MSR ranges (CPUMMSRRANGE) in the array pointed to below. */
189 uint32_t cMsrRanges;
190 /** Mask applied to ECX before looking up the MSR for a RDMSR/WRMSR
191 * instruction. Older hardware has been observed to ignore higher bits. */
192 uint32_t fMsrMask;
193
194 /** MXCSR mask. */
195 uint32_t fMxCsrMask;
196
197 /** The number of CPUID leaves (CPUMCPUIDLEAF) in the array pointed to below. */
198 uint32_t cCpuIdLeaves;
199 /** The index of the first extended CPUID leaf in the array.
200 * Set to cCpuIdLeaves if none present. */
201 uint32_t iFirstExtCpuIdLeaf;
202 /** How to handle unknown CPUID leaves. */
203 CPUMUNKNOWNCPUID enmUnknownCpuIdMethod;
204 /** For use with CPUMUNKNOWNCPUID_DEFAULTS (DB & VM),
205 * CPUMUNKNOWNCPUID_LAST_STD_LEAF (VM) and CPUMUNKNOWNCPUID_LAST_STD_LEAF_WITH_ECX (VM). */
206 CPUMCPUID DefCpuId;
207
208 /** Scalable bus frequency used for reporting other frequencies. */
209 uint64_t uScalableBusFreq;
210
211 /** The microcode revision.
212 * UINT32_MAX if the one from the CPU database entry is to be used.
213 * @see /CPUM/GuestMicrocodeRevision in CFGM. */
214 uint32_t uMicrocodeRevision;
215 uint32_t uPadding;
216
217 /** Pointer to the MSR ranges (for compatibility with old hyper heap code). */
218 R3PTRTYPE(PCPUMMSRRANGE) paMsrRangesR3;
219 /** Pointer to the CPUID leaves (for compatibility with old hyper heap code). */
220 R3PTRTYPE(PCPUMCPUIDLEAF) paCpuIdLeavesR3;
221
222 /** CPUID leaves. */
223 CPUMCPUIDLEAF aCpuIdLeaves[256];
224 /** MSR ranges.
225 * @todo This is insane, so might want to move this into a separate
226 * allocation. The insanity is mainly for more recent AMD CPUs. */
227 CPUMMSRRANGE aMsrRanges[8192];
228
229#elif defined(VBOX_VMM_TARGET_ARMV8)
230 /** The number of system register ranges (CPUMSSREGRANGE) in the array pointed to below. */
231 uint32_t cSysRegRanges;
232 uint32_t uPadding;
233
234 /** Pointer to the sysrem register ranges. */
235 R3PTRTYPE(PCPUMSYSREGRANGE) paSysRegRangesR3;
236
237 /** System register ranges. */
238 CPUMSYSREGRANGE aSysRegRanges[128];
239#else
240# error "port me"
241#endif
242} CPUMINFO;
243/** Pointer to a CPU info structure. */
244typedef CPUMINFO *PCPUMINFO;
245/** Pointer to a const CPU info structure. */
246typedef CPUMINFO const *CPCPUMINFO;
247
248
249#ifdef RT_ARCH_AMD64
250/**
251 * The saved host CPU state.
252 */
253typedef struct CPUMHOSTCTX
254{
255 /** The extended state (FPU/SSE/AVX/AVX-2/XXXX). Must be aligned on 64 bytes. */
256 union /* no tag */
257 {
258 X86XSAVEAREA XState;
259 /** Byte view for simple indexing and space allocation.
260 * @note Must match or exceed the size of CPUMCTX::abXState. */
261 uint8_t abXState[0x4000 - 0x300];
262 } CPUM_UNION_NM(u);
263
264 /** General purpose register, selectors, flags and more
265 * @{ */
266 /** General purpose register ++
267 * { */
268 /*uint64_t rax; - scratch*/
269 uint64_t rbx;
270 /*uint64_t rcx; - scratch*/
271 /*uint64_t rdx; - scratch*/
272 uint64_t rdi;
273 uint64_t rsi;
274 uint64_t rbp;
275 uint64_t rsp;
276 /*uint64_t r8; - scratch*/
277 /*uint64_t r9; - scratch*/
278 uint64_t r10;
279 uint64_t r11;
280 uint64_t r12;
281 uint64_t r13;
282 uint64_t r14;
283 uint64_t r15;
284 /*uint64_t rip; - scratch*/
285 uint64_t rflags;
286 /** @} */
287
288 /** Selector registers
289 * @{ */
290 RTSEL ss;
291 RTSEL ssPadding;
292 RTSEL gs;
293 RTSEL gsPadding;
294 RTSEL fs;
295 RTSEL fsPadding;
296 RTSEL es;
297 RTSEL esPadding;
298 RTSEL ds;
299 RTSEL dsPadding;
300 RTSEL cs;
301 RTSEL csPadding;
302 /** @} */
303
304 /** Control registers.
305 * @{ */
306 /** The CR0 FPU state in HM mode. */
307 uint64_t cr0;
308 /*uint64_t cr2; - scratch*/
309 uint64_t cr3;
310 uint64_t cr4;
311 uint64_t cr8;
312 /** @} */
313
314 /** Debug registers.
315 * @{ */
316 uint64_t dr0;
317 uint64_t dr1;
318 uint64_t dr2;
319 uint64_t dr3;
320 uint64_t dr6;
321 uint64_t dr7;
322 /** @} */
323
324 /** Global Descriptor Table register. */
325 X86XDTR64 gdtr;
326 uint16_t gdtrPadding;
327 /** Interrupt Descriptor Table register. */
328 X86XDTR64 idtr;
329 uint16_t idtrPadding;
330 /** The task register. */
331 RTSEL ldtr;
332 RTSEL ldtrPadding;
333 /** The task register. */
334 RTSEL tr;
335 RTSEL trPadding;
336
337 /** MSRs
338 * @{ */
339 CPUMSYSENTER SysEnter;
340 uint64_t FSbase;
341 uint64_t GSbase;
342 uint64_t efer;
343 /** @} */
344
345 /** The XCR0 register. */
346 uint64_t xcr0;
347 /** The mask to pass to XSAVE/XRSTOR in EDX:EAX. If zero we use
348 * FXSAVE/FXRSTOR (since bit 0 will always be set, we only need to test it). */
349 uint64_t fXStateMask;
350
351 /* padding to get 64byte aligned size */
352 uint8_t auPadding[24];
353# if HC_ARCH_BITS != 64
354# error HC_ARCH_BITS not defined or unsupported
355# endif
356} CPUMHOSTCTX;
357# ifndef VBOX_FOR_DTRACE_LIB
358AssertCompileSizeAlignment(CPUMHOSTCTX, 64);
359# endif
360/** Pointer to the saved host CPU state. */
361typedef CPUMHOSTCTX *PCPUMHOSTCTX;
362#endif /* RT_ARCH_AMD64 */
363
364
365#if defined(VBOX_VMM_TARGET_X86) /** @todo temporary: */ || defined(VBOX_VMM_TARGET_AGNOSTIC)
366/**
367 * The hypervisor context CPU state (just DRx left now).
368 */
369typedef struct CPUMHYPERCTX
370{
371 /** Debug registers.
372 * @remarks DR4 and DR5 should not be used since they are aliases for
373 * DR6 and DR7 respectively on both AMD and Intel CPUs.
374 * @remarks DR8-15 are currently not supported by AMD or Intel, so
375 * neither do we.
376 */
377 uint64_t dr[8];
378 /** @todo eliminiate the rest. */
379 uint64_t cr3;
380 uint64_t au64Padding[7];
381} CPUMHYPERCTX;
382# ifndef VBOX_FOR_DTRACE_LIB
383AssertCompileSizeAlignment(CPUMHYPERCTX, 64);
384# endif
385/** Pointer to the hypervisor context CPU state. */
386typedef CPUMHYPERCTX *PCPUMHYPERCTX;
387#endif
388
389
390/**
391 * CPUM Data (part of VM)
392 */
393typedef struct CPUM
394{
395 /** Guest CPU feature information.
396 * Externaly visible via that VM structure, aligned with HostFeatures. */
397 CPUMFEATURES GuestFeatures;
398 /** Host CPU feature information.
399 * Externaly visible via the VM structure, aligned on 64-byte boundrary. */
400 CPUHOSTFEATURES HostFeatures;
401
402 /** The (more) portable CPUID level. */
403 uint8_t u8PortableCpuIdLevel;
404 /** Indicates that a state restore is pending.
405 * This is used to verify load order dependencies (PGM). */
406 bool fPendingRestore;
407
408#if defined(VBOX_VMM_TARGET_X86) /** @todo temporary: */ || defined(VBOX_VMM_TARGET_AGNOSTIC)
409 /** Whether MTRR reads report valid memory types for memory regions. */
410 bool fMtrrRead;
411 /** Whether the guest's writes to MTRRs are implemented. */
412 bool fMtrrWrite;
413 /** Use flags.
414 * These flags indicates which CPU features the host uses.
415 */
416 uint32_t fHostUseFlags;
417
418 /** XSAVE/XRTOR components we can expose to the guest mask. */
419 uint64_t fXStateGuestMask;
420 /** XSAVE/XRSTOR host mask. Only state components in this mask can be exposed
421 * to the guest. This is 0 if no XSAVE/XRSTOR bits can be exposed. */
422 uint64_t fXStateHostMask;
423
424 /** Random value we store in the reserved RFLAGS bits we don't use ourselves so
425 * we can detect corruption. */
426 uint64_t fReservedRFlagsCookie;
427
428 /** Guest CPU info. */
429 CPUMINFO GuestInfo;
430
431 /** The standard set of CpuId leaves. */
432 CPUMCPUID aGuestCpuIdPatmStd[6];
433 /** The extended set of CpuId leaves. */
434 CPUMCPUID aGuestCpuIdPatmExt[10];
435 /** The centaur set of CpuId leaves. */
436 CPUMCPUID aGuestCpuIdPatmCentaur[4];
437
438 /** @name MSR statistics.
439 * @{ */
440 STAMCOUNTER cMsrWrites;
441 STAMCOUNTER cMsrWritesToIgnoredBits;
442 STAMCOUNTER cMsrWritesRaiseGp;
443 STAMCOUNTER cMsrWritesUnknown;
444 STAMCOUNTER cMsrReads;
445 STAMCOUNTER cMsrReadsRaiseGp;
446 STAMCOUNTER cMsrReadsUnknown;
447 /** @} */
448
449#elif defined(VBOX_VMM_TARGET_ARMV8)
450 /** The initial exception level (EL) to start the CPU after a reset,
451 * should be either ARMV8_AARCH64_EL_1 or ARMV8_AARCH64_EL_2 for nested virtualization. */
452 uint8_t bResetEl;
453 uint8_t abPadding0[5];
454
455 /** The reset value of the program counter. */
456 uint64_t u64ResetPc;
457
458 /** Guest CPU info. */
459 CPUMINFO GuestInfo;
460 /** Guest CPU ID registers. */
461 CPUMARMV8IDREGS GuestIdRegs;
462
463 /** @name System register statistics.
464 * @{ */
465 STAMCOUNTER cSysRegWrites;
466 STAMCOUNTER cSysRegWritesToIgnoredBits;
467 STAMCOUNTER cSysRegWritesRaiseExcp;
468 STAMCOUNTER cSysRegWritesUnknown;
469 STAMCOUNTER cSysRegReads;
470 STAMCOUNTER cSysRegReadsRaiseExcp;
471 STAMCOUNTER cSysRegReadsUnknown;
472 /** @} */
473#endif
474
475#ifdef RT_ARCH_ARM64
476 /** Host CPU ID registers. */
477 CPUMARMV8IDREGS HostIdRegs;
478
479#elif defined(RT_ARCH_X86) || defined(RT_ARCH_AMD64)
480 /** The host MXCSR mask (determined at init). */
481 uint32_t fHostMxCsrMask;
482#endif
483} CPUM;
484#ifndef VBOX_FOR_DTRACE_LIB
485AssertCompileMemberOffset(CPUM, GuestFeatures, 0);
486AssertCompileMemberOffset(CPUM, HostFeatures, 64);
487AssertCompileMemberOffset(CPUM, u8PortableCpuIdLevel, 128);
488#endif
489/** Pointer to the CPUM instance data residing in the shared VM structure. */
490typedef CPUM *PCPUM;
491
492/**
493 * CPUM Data (part of VMCPU)
494 */
495typedef struct CPUMCPU
496{
497 /** Guest context.
498 * Aligned on a 64-byte boundary. */
499 CPUMCTX Guest;
500#if defined(VBOX_VMM_TARGET_X86) /** @todo temporary: */ || defined(VBOX_VMM_TARGET_AGNOSTIC)
501 /** Guest context - misc MSRs
502 * Aligned on a 64-byte boundary. */
503 CPUMCTXMSRS GuestMsrs;
504#endif
505#ifdef RT_ARCH_AMD64
506 /** Saved host context. Only valid while inside RC or HM contexts.
507 * Must be aligned on a 64-byte boundary. */
508 CPUMHOSTCTX Host;
509#endif
510
511 /** Use flags.
512 * These flags indicates both what is to be used and what has been used. */
513 uint32_t fUseFlags;
514
515 /** Changed flags.
516 * These flags indicates to REM (and others) which important guest
517 * registers which has been changed since last time the flags were cleared.
518 * See the CPUM_CHANGED_* defines for what we keep track of.
519 *
520 * @todo Obsolete, but will probably be refactored so keep it for reference. */
521 uint32_t fChanged;
522
523#if defined(VBOX_VMM_TARGET_X86) /** @todo temporary: */ || defined(VBOX_VMM_TARGET_AGNOSTIC)
524 /** Nested VMX: VMX-preemption timer. */
525 TMTIMERHANDLE hNestedVmxPreemptTimer;
526 /** Whether the X86_CPUID_FEATURE_EDX_APIC and X86_CPUID_AMD_FEATURE_EDX_APIC
527 * (?) bits are visible or not. (The APIC is responsible for setting this
528 * when loading state, so we won't save it.) */
529 bool fCpuIdApicFeatureVisible;
530 uint8_t abPadding[7];
531
532 /** Old hypervisor context, only used for combined DRx values now.
533 * Must be aligned on a 64-byte boundary. */
534 CPUMHYPERCTX Hyper;
535#endif
536
537#ifdef VBOX_WITH_CRASHDUMP_MAGIC
538 uint8_t aMagic[56];
539 uint64_t uMagic;
540#endif
541} CPUMCPU;
542#ifndef VBOX_FOR_DTRACE_LIB
543# ifdef RT_ARCH_AMD64
544AssertCompileMemberAlignment(CPUMCPU, Host, 64);
545# endif
546#endif
547/** Pointer to the CPUMCPU instance data residing in the shared VMCPU structure. */
548typedef CPUMCPU *PCPUMCPU;
549
550#ifndef VBOX_FOR_DTRACE_LIB
551RT_C_DECLS_BEGIN
552
553# if defined(VBOX_VMM_TARGET_X86) /** @todo temporary: */ || defined(VBOX_VMM_TARGET_AGNOSTIC)
554PCPUMCPUIDLEAF cpumCpuIdGetLeaf(PVM pVM, uint32_t uLeaf);
555PCPUMCPUIDLEAF cpumCpuIdGetLeafEx(PVM pVM, uint32_t uLeaf, uint32_t uSubLeaf, bool *pfExactSubLeafHit);
556# endif
557# if defined(RT_ARCH_X86) || defined(RT_ARCH_AMD64) || defined(VBOX_VMM_TARGET_X86)
558PCPUMCPUIDLEAF cpumCpuIdGetLeafInt(PCPUMCPUIDLEAF paLeaves, uint32_t cLeaves, uint32_t uLeaf, uint32_t uSubLeaf);
559PCPUMCPUIDLEAF cpumCpuIdEnsureSpace(PVM pVM, PCPUMCPUIDLEAF *ppaLeaves, uint32_t cLeaves);
560# ifdef VBOX_STRICT
561void cpumCpuIdAssertOrder(PCPUMCPUIDLEAF paLeaves, uint32_t cLeaves);
562# endif
563int cpumCpuIdExplodeFeaturesX86(PCCPUMCPUIDLEAF paLeaves, uint32_t cLeaves, PCCPUMMSRS pMsrs,
564 CPUMFEATURESX86 *pFeatures);
565# endif /* defined(RT_ARCH_X86) || defined(RT_ARCH_AMD64) || defined(VBOX_VMM_TARGET_X86) */
566# if defined(RT_ARCH_ARM64) || defined(VBOX_VMM_TARGET_ARMV8)
567int cpumCpuIdExplodeFeaturesArmV8(PCCPUMARMV8IDREGS pIdRegs, CPUMFEATURESARMV8 *pFeatures);
568# endif
569
570# ifdef IN_RING3
571DECLHIDDEN(int) cpumR3DbgInit(PVM pVM);
572# if defined(VBOX_VMM_TARGET_ARMV8)
573DECLHIDDEN(int) cpumR3SysRegStrictInitChecks(void);
574# elif defined(VBOX_VMM_TARGET_X86)
575int cpumR3InitCpuIdAndMsrs(PVM pVM, PCCPUMMSRS pHostMsrs);
576void cpumR3InitVmxGuestFeaturesAndMsrs(PVM pVM, PCFGMNODE pCpumCfg, PCVMXMSRS pHostVmxMsrs,
577 PVMXMSRS pGuestVmxMsrs);
578void cpumR3CpuIdRing3InitDone(PVM pVM);
579# endif
580void cpumR3SaveCpuId(PVM pVM, PSSMHANDLE pSSM);
581# ifdef VBOX_VMM_TARGET_X86
582int cpumR3LoadCpuIdX86(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion, PCCPUMMSRS pGuestMsrs);
583int cpumR3LoadCpuIdPre32(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion);
584# elif defined(VBOX_VMM_TARGET_ARMV8)
585int cpumR3LoadCpuIdArmV8(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion);
586DECLCALLBACK(void) cpumR3CpuFeatInfo(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
587# endif
588DECLCALLBACK(void) cpumR3CpuIdInfo(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
589
590int cpumR3DbGetCpuInfo(const char *pszName, PCPUMINFO pInfo);
591# ifdef VBOX_VMM_TARGET_X86
592int cpumR3MsrRangesInsert(PVM pVM, PCPUMMSRRANGE *ppaMsrRanges, uint32_t *pcMsrRanges, PCCPUMMSRRANGE pNewRange);
593int cpumR3MsrReconcileWithCpuId(PVM pVM);
594int cpumR3MsrApplyFudge(PVM pVM);
595int cpumR3MsrRegStats(PVM pVM);
596int cpumR3MsrStrictInitChecks(void);
597PCPUMMSRRANGE cpumLookupMsrRange(PVM pVM, uint32_t idMsr);
598# endif
599# endif /* IN_RING3 */
600
601# ifdef IN_RING0
602# if defined(VBOX_VMM_TARGET_X86) /** @todo temporary: */ || defined(VBOX_VMM_TARGET_AGNOSTIC)
603DECLASM(int) cpumR0SaveHostRestoreGuestFPUState(PCPUMCPU pCPUM);
604DECLASM(void) cpumR0SaveGuestRestoreHostFPUState(PCPUMCPU pCPUM);
605# if ARCH_BITS == 32 && defined(VBOX_WITH_64_BITS_GUESTS)
606DECLASM(void) cpumR0RestoreHostFPUState(PCPUMCPU pCPUM);
607# endif
608# endif
609# endif
610
611# if defined(IN_RC) || defined(IN_RING0)
612# if defined(VBOX_VMM_TARGET_X86) /** @todo temporary: */ || defined(VBOX_VMM_TARGET_AGNOSTIC)
613DECLASM(int) cpumRZSaveHostFPUState(PCPUMCPU pCPUM);
614DECLASM(void) cpumRZSaveGuestFpuState(PCPUMCPU pCPUM, bool fLeaveFpuAccessible);
615DECLASM(void) cpumRZSaveGuestSseRegisters(PCPUMCPU pCPUM);
616DECLASM(void) cpumRZSaveGuestAvxRegisters(PCPUMCPU pCPUM);
617# endif
618# endif
619
620RT_C_DECLS_END
621#endif /* !VBOX_FOR_DTRACE_LIB */
622
623/** @} */
624
625#endif /* !VMM_INCLUDED_SRC_include_CPUMInternal_h */
626
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