VirtualBox

source: vbox/trunk/src/VBox/VMM/include/CPUMInternal.h@ 49977

Last change on this file since 49977 was 49977, checked in by vboxsync, 11 years ago

CPUM: Make sure a minimum of commonly used MSRs are present by default.
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File size: 41.6 KB
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1/* $Id: CPUMInternal.h 49977 2013-12-18 17:51:13Z vboxsync $ */
2/** @file
3 * CPUM - Internal header file.
4 */
5
6/*
7 * Copyright (C) 2006-2012 Oracle Corporation
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 */
17
18#ifndef ___CPUMInternal_h
19#define ___CPUMInternal_h
20
21#ifndef VBOX_FOR_DTRACE_LIB
22# include <VBox/cdefs.h>
23# include <VBox/types.h>
24# include <VBox/vmm/stam.h>
25# include <iprt/x86.h>
26#else
27# pragma D depends_on library x86.d
28# pragma D depends_on library cpumctx.d
29#endif
30
31
32
33
34/** @defgroup grp_cpum_int Internals
35 * @ingroup grp_cpum
36 * @internal
37 * @{
38 */
39
40/** Flags and types for CPUM fault handlers
41 * @{ */
42/** Type: Load DS */
43#define CPUM_HANDLER_DS 1
44/** Type: Load ES */
45#define CPUM_HANDLER_ES 2
46/** Type: Load FS */
47#define CPUM_HANDLER_FS 3
48/** Type: Load GS */
49#define CPUM_HANDLER_GS 4
50/** Type: IRET */
51#define CPUM_HANDLER_IRET 5
52/** Type mask. */
53#define CPUM_HANDLER_TYPEMASK 0xff
54/** If set EBP points to the CPUMCTXCORE that's being used. */
55#define CPUM_HANDLER_CTXCORE_IN_EBP RT_BIT(31)
56/** @} */
57
58
59/** Use flags (CPUM::fUseFlags).
60 * (Don't forget to sync this with CPUMInternal.mac !)
61 * @{ */
62/** Used the FPU, SSE or such stuff. */
63#define CPUM_USED_FPU RT_BIT(0)
64/** Used the FPU, SSE or such stuff since last we were in REM.
65 * REM syncing is clearing this, lazy FPU is setting it. */
66#define CPUM_USED_FPU_SINCE_REM RT_BIT(1)
67/** The XMM state was manually restored. (AMD only) */
68#define CPUM_USED_MANUAL_XMM_RESTORE RT_BIT(2)
69
70/** Host OS is using SYSENTER and we must NULL the CS. */
71#define CPUM_USE_SYSENTER RT_BIT(3)
72/** Host OS is using SYSENTER and we must NULL the CS. */
73#define CPUM_USE_SYSCALL RT_BIT(4)
74
75/** Debug registers are used by host and that DR7 and DR6 must be saved and
76 * disabled when switching to raw-mode. */
77#define CPUM_USE_DEBUG_REGS_HOST RT_BIT(5)
78/** Records that we've saved the host DRx registers.
79 * In ring-0 this means all (DR0-7), while in raw-mode context this means DR0-3
80 * since DR6 and DR7 are covered by CPUM_USE_DEBUG_REGS_HOST. */
81#define CPUM_USED_DEBUG_REGS_HOST RT_BIT(6)
82/** Set to indicate that we should save host DR0-7 and load the hypervisor debug
83 * registers in the raw-mode world switchers. (See CPUMRecalcHyperDRx.) */
84#define CPUM_USE_DEBUG_REGS_HYPER RT_BIT(7)
85/** Used in ring-0 to indicate that we have loaded the hypervisor debug
86 * registers. */
87#define CPUM_USED_DEBUG_REGS_HYPER RT_BIT(8)
88/** Used in ring-0 to indicate that we have loaded the guest debug
89 * registers (DR0-3 and maybe DR6) for direct use by the guest.
90 * DR7 (and AMD-V DR6) are handled via the VMCB. */
91#define CPUM_USED_DEBUG_REGS_GUEST RT_BIT(9)
92
93
94/** Sync the FPU state on next entry (32->64 switcher only). */
95#define CPUM_SYNC_FPU_STATE RT_BIT(16)
96/** Sync the debug state on next entry (32->64 switcher only). */
97#define CPUM_SYNC_DEBUG_REGS_GUEST RT_BIT(17)
98/** Sync the debug state on next entry (32->64 switcher only).
99 * Almost the same as CPUM_USE_DEBUG_REGS_HYPER in the raw-mode switchers. */
100#define CPUM_SYNC_DEBUG_REGS_HYPER RT_BIT(18)
101/** Host CPU requires fxsave/fxrstor leaky bit handling. */
102#define CPUM_USE_FFXSR_LEAKY RT_BIT(19)
103/** @} */
104
105/* Sanity check. */
106#ifndef VBOX_FOR_DTRACE_LIB
107#if defined(VBOX_WITH_HYBRID_32BIT_KERNEL) && (HC_ARCH_BITS != 32 || R0_ARCH_BITS != 32)
108# error "VBOX_WITH_HYBRID_32BIT_KERNEL is only for 32 bit builds."
109#endif
110#endif
111
112
113/**
114 * MSR read functions.
115 */
116typedef enum CPUMMSRRDFN
117{
118 /** Invalid zero value. */
119 kCpumMsrRdFn_Invalid = 0,
120 /** Return the CPUMMSRRANGE::uValue. */
121 kCpumMsrRdFn_FixedValue,
122 /** Alias to the MSR range starting at the MSR given by
123 * CPUMMSRRANGE::uValue. Must be used in pair with
124 * kCpumMsrWrFn_MsrAlias. */
125 kCpumMsrRdFn_MsrAlias,
126 /** Write only register, GP all read attempts. */
127 kCpumMsrRdFn_WriteOnly,
128
129 kCpumMsrRdFn_Ia32P5McAddr,
130 kCpumMsrRdFn_Ia32P5McType,
131 kCpumMsrRdFn_Ia32TimestampCounter,
132 kCpumMsrRdFn_Ia32ApicBase,
133 kCpumMsrRdFn_Ia32FeatureControl,
134 kCpumMsrRdFn_Ia32BiosSignId, /**< Range value returned. */
135 kCpumMsrRdFn_Ia32SmmMonitorCtl,
136 kCpumMsrRdFn_Ia32PmcN,
137 kCpumMsrRdFn_Ia32MonitorFilterLineSize,
138 kCpumMsrRdFn_Ia32MPerf,
139 kCpumMsrRdFn_Ia32APerf,
140 kCpumMsrRdFn_Ia32MtrrCap, /**< Takes real CPU value for reference. */
141 kCpumMsrRdFn_Ia32MtrrPhysBaseN, /**< Takes register number. */
142 kCpumMsrRdFn_Ia32MtrrPhysMaskN, /**< Takes register number. */
143 kCpumMsrRdFn_Ia32MtrrFixed, /**< Takes CPUMCPU offset. */
144 kCpumMsrRdFn_Ia32MtrrDefType,
145 kCpumMsrRdFn_Ia32Pat,
146 kCpumMsrRdFn_Ia32SysEnterCs,
147 kCpumMsrRdFn_Ia32SysEnterEsp,
148 kCpumMsrRdFn_Ia32SysEnterEip,
149 kCpumMsrRdFn_Ia32McgCap,
150 kCpumMsrRdFn_Ia32McgStatus,
151 kCpumMsrRdFn_Ia32McgCtl,
152 kCpumMsrRdFn_Ia32DebugCtl,
153 kCpumMsrRdFn_Ia32SmrrPhysBase,
154 kCpumMsrRdFn_Ia32SmrrPhysMask,
155 kCpumMsrRdFn_Ia32PlatformDcaCap,
156 kCpumMsrRdFn_Ia32CpuDcaCap,
157 kCpumMsrRdFn_Ia32Dca0Cap,
158 kCpumMsrRdFn_Ia32PerfEvtSelN, /**< Range value indicates the register number. */
159 kCpumMsrRdFn_Ia32PerfStatus, /**< Range value returned. */
160 kCpumMsrRdFn_Ia32PerfCtl, /**< Range value returned. */
161 kCpumMsrRdFn_Ia32FixedCtrN, /**< Takes register number of start of range. */
162 kCpumMsrRdFn_Ia32PerfCapabilities, /**< Takes reference value. */
163 kCpumMsrRdFn_Ia32FixedCtrCtrl,
164 kCpumMsrRdFn_Ia32PerfGlobalStatus, /**< Takes reference value. */
165 kCpumMsrRdFn_Ia32PerfGlobalCtrl,
166 kCpumMsrRdFn_Ia32PerfGlobalOvfCtrl,
167 kCpumMsrRdFn_Ia32PebsEnable,
168 kCpumMsrRdFn_Ia32ClockModulation, /**< Range value returned. */
169 kCpumMsrRdFn_Ia32ThermInterrupt, /**< Range value returned. */
170 kCpumMsrRdFn_Ia32ThermStatus, /**< Range value returned. */
171 kCpumMsrRdFn_Ia32Therm2Ctl, /**< Range value returned. */
172 kCpumMsrRdFn_Ia32MiscEnable, /**< Range value returned. */
173 kCpumMsrRdFn_Ia32McCtlStatusAddrMiscN, /**< Takes bank number. */
174 kCpumMsrRdFn_Ia32McNCtl2, /**< Takes register number of start of range. */
175 kCpumMsrRdFn_Ia32DsArea,
176 kCpumMsrRdFn_Ia32TscDeadline,
177 kCpumMsrRdFn_Ia32X2ApicN,
178 kCpumMsrRdFn_Ia32DebugInterface,
179 kCpumMsrRdFn_Ia32VmxBase, /**< Takes real value as reference. */
180 kCpumMsrRdFn_Ia32VmxPinbasedCtls, /**< Takes real value as reference. */
181 kCpumMsrRdFn_Ia32VmxProcbasedCtls, /**< Takes real value as reference. */
182 kCpumMsrRdFn_Ia32VmxExitCtls, /**< Takes real value as reference. */
183 kCpumMsrRdFn_Ia32VmxEntryCtls, /**< Takes real value as reference. */
184 kCpumMsrRdFn_Ia32VmxMisc, /**< Takes real value as reference. */
185 kCpumMsrRdFn_Ia32VmxCr0Fixed0, /**< Takes real value as reference. */
186 kCpumMsrRdFn_Ia32VmxCr0Fixed1, /**< Takes real value as reference. */
187 kCpumMsrRdFn_Ia32VmxCr4Fixed0, /**< Takes real value as reference. */
188 kCpumMsrRdFn_Ia32VmxCr4Fixed1, /**< Takes real value as reference. */
189 kCpumMsrRdFn_Ia32VmxVmcsEnum, /**< Takes real value as reference. */
190 kCpumMsrRdFn_Ia32VmxProcBasedCtls2, /**< Takes real value as reference. */
191 kCpumMsrRdFn_Ia32VmxEptVpidCap, /**< Takes real value as reference. */
192 kCpumMsrRdFn_Ia32VmxTruePinbasedCtls, /**< Takes real value as reference. */
193 kCpumMsrRdFn_Ia32VmxTrueProcbasedCtls, /**< Takes real value as reference. */
194 kCpumMsrRdFn_Ia32VmxTrueExitCtls, /**< Takes real value as reference. */
195 kCpumMsrRdFn_Ia32VmxTrueEntryCtls, /**< Takes real value as reference. */
196
197 kCpumMsrRdFn_Amd64Efer,
198 kCpumMsrRdFn_Amd64SyscallTarget,
199 kCpumMsrRdFn_Amd64LongSyscallTarget,
200 kCpumMsrRdFn_Amd64CompSyscallTarget,
201 kCpumMsrRdFn_Amd64SyscallFlagMask,
202 kCpumMsrRdFn_Amd64FsBase,
203 kCpumMsrRdFn_Amd64GsBase,
204 kCpumMsrRdFn_Amd64KernelGsBase,
205 kCpumMsrRdFn_Amd64TscAux,
206
207 kCpumMsrRdFn_IntelEblCrPowerOn,
208 kCpumMsrRdFn_IntelP4EbcHardPowerOn,
209 kCpumMsrRdFn_IntelP4EbcSoftPowerOn,
210 kCpumMsrRdFn_IntelP4EbcFrequencyId,
211 kCpumMsrRdFn_IntelPlatformInfo100MHz,
212 kCpumMsrRdFn_IntelPlatformInfo133MHz,
213 kCpumMsrRdFn_IntelPkgCStConfigControl,
214 kCpumMsrRdFn_IntelPmgIoCaptureBase,
215 kCpumMsrRdFn_IntelLastBranchFromToN,
216 kCpumMsrRdFn_IntelLastBranchFromN,
217 kCpumMsrRdFn_IntelLastBranchToN,
218 kCpumMsrRdFn_IntelLastBranchTos,
219 kCpumMsrRdFn_IntelBblCrCtl,
220 kCpumMsrRdFn_IntelBblCrCtl3,
221 kCpumMsrRdFn_IntelI7TemperatureTarget, /**< Range value returned. */
222 kCpumMsrRdFn_IntelI7MsrOffCoreResponseN,/**< Takes register number. */
223 kCpumMsrRdFn_IntelI7MiscPwrMgmt,
224 kCpumMsrRdFn_IntelP6CrN,
225 kCpumMsrRdFn_IntelCpuId1FeatureMaskEcdx,
226 kCpumMsrRdFn_IntelCpuId1FeatureMaskEax,
227 kCpumMsrRdFn_IntelCpuId80000001FeatureMaskEcdx,
228 kCpumMsrRdFn_IntelI7SandyAesNiCtl,
229 kCpumMsrRdFn_IntelI7TurboRatioLimit, /**< Returns range value. */
230 kCpumMsrRdFn_IntelI7LbrSelect,
231 kCpumMsrRdFn_IntelI7SandyErrorControl,
232 kCpumMsrRdFn_IntelI7VirtualLegacyWireCap,/**< Returns range value. */
233 kCpumMsrRdFn_IntelI7PowerCtl,
234 kCpumMsrRdFn_IntelI7SandyPebsNumAlt,
235 kCpumMsrRdFn_IntelI7PebsLdLat,
236 kCpumMsrRdFn_IntelI7PkgCnResidencyN, /**< Takes C-state number. */
237 kCpumMsrRdFn_IntelI7CoreCnResidencyN, /**< Takes C-state number. */
238 kCpumMsrRdFn_IntelI7SandyVrCurrentConfig,/**< Takes real value as reference. */
239 kCpumMsrRdFn_IntelI7SandyVrMiscConfig, /**< Takes real value as reference. */
240 kCpumMsrRdFn_IntelI7SandyRaplPowerUnit, /**< Takes real value as reference. */
241 kCpumMsrRdFn_IntelI7SandyPkgCnIrtlN, /**< Takes real value as reference. */
242 kCpumMsrRdFn_IntelI7SandyPkgC2Residency, /**< Takes real value as reference. */
243 kCpumMsrRdFn_IntelI7RaplPkgPowerLimit, /**< Takes real value as reference. */
244 kCpumMsrRdFn_IntelI7RaplPkgEnergyStatus, /**< Takes real value as reference. */
245 kCpumMsrRdFn_IntelI7RaplPkgPerfStatus, /**< Takes real value as reference. */
246 kCpumMsrRdFn_IntelI7RaplPkgPowerInfo, /**< Takes real value as reference. */
247 kCpumMsrRdFn_IntelI7RaplDramPowerLimit, /**< Takes real value as reference. */
248 kCpumMsrRdFn_IntelI7RaplDramEnergyStatus,/**< Takes real value as reference. */
249 kCpumMsrRdFn_IntelI7RaplDramPerfStatus, /**< Takes real value as reference. */
250 kCpumMsrRdFn_IntelI7RaplDramPowerInfo, /**< Takes real value as reference. */
251 kCpumMsrRdFn_IntelI7RaplPp0PowerLimit, /**< Takes real value as reference. */
252 kCpumMsrRdFn_IntelI7RaplPp0EnergyStatus, /**< Takes real value as reference. */
253 kCpumMsrRdFn_IntelI7RaplPp0Policy, /**< Takes real value as reference. */
254 kCpumMsrRdFn_IntelI7RaplPp0PerfStatus, /**< Takes real value as reference. */
255 kCpumMsrRdFn_IntelI7RaplPp1PowerLimit, /**< Takes real value as reference. */
256 kCpumMsrRdFn_IntelI7RaplPp1EnergyStatus, /**< Takes real value as reference. */
257 kCpumMsrRdFn_IntelI7RaplPp1Policy, /**< Takes real value as reference. */
258 kCpumMsrRdFn_IntelI7IvyConfigTdpNominal, /**< Takes real value as reference. */
259 kCpumMsrRdFn_IntelI7IvyConfigTdpLevel1, /**< Takes real value as reference. */
260 kCpumMsrRdFn_IntelI7IvyConfigTdpLevel2, /**< Takes real value as reference. */
261 kCpumMsrRdFn_IntelI7IvyConfigTdpControl,
262 kCpumMsrRdFn_IntelI7IvyTurboActivationRatio,
263 kCpumMsrRdFn_IntelI7UncPerfGlobalCtrl,
264 kCpumMsrRdFn_IntelI7UncPerfGlobalStatus,
265 kCpumMsrRdFn_IntelI7UncPerfGlobalOvfCtrl,
266 kCpumMsrRdFn_IntelI7UncPerfFixedCtrCtrl,
267 kCpumMsrRdFn_IntelI7UncPerfFixedCtr,
268 kCpumMsrRdFn_IntelI7UncCBoxConfig,
269 kCpumMsrRdFn_IntelI7UncArbPerfCtrN,
270 kCpumMsrRdFn_IntelI7UncArbPerfEvtSelN,
271 kCpumMsrRdFn_IntelCore2EmttmCrTablesN, /**< Range value returned. */
272 kCpumMsrRdFn_IntelCore2SmmCStMiscInfo,
273 kCpumMsrRdFn_IntelCore1ExtConfig,
274 kCpumMsrRdFn_IntelCore1DtsCalControl,
275 kCpumMsrRdFn_IntelCore2PeciControl,
276
277 kCpumMsrRdFn_P6LastBranchFromIp,
278 kCpumMsrRdFn_P6LastBranchToIp,
279 kCpumMsrRdFn_P6LastIntFromIp,
280 kCpumMsrRdFn_P6LastIntToIp,
281
282 kCpumMsrRdFn_AmdFam15hTscRate,
283 kCpumMsrRdFn_AmdFam15hLwpCfg,
284 kCpumMsrRdFn_AmdFam15hLwpCbAddr,
285 kCpumMsrRdFn_AmdFam10hMc4MiscN,
286 kCpumMsrRdFn_AmdK8PerfCtlN,
287 kCpumMsrRdFn_AmdK8PerfCtrN,
288 kCpumMsrRdFn_AmdK8SysCfg, /**< Range value returned. */
289 kCpumMsrRdFn_AmdK8HwCr,
290 kCpumMsrRdFn_AmdK8IorrBaseN,
291 kCpumMsrRdFn_AmdK8IorrMaskN,
292 kCpumMsrRdFn_AmdK8TopOfMemN,
293 kCpumMsrRdFn_AmdK8NbCfg1,
294 kCpumMsrRdFn_AmdK8McXcptRedir,
295 kCpumMsrRdFn_AmdK8CpuNameN,
296 kCpumMsrRdFn_AmdK8HwThermalCtrl, /**< Range value returned. */
297 kCpumMsrRdFn_AmdK8SwThermalCtrl,
298 kCpumMsrRdFn_AmdK8FidVidControl, /**< Range value returned. */
299 kCpumMsrRdFn_AmdK8FidVidStatus, /**< Range value returned. */
300 kCpumMsrRdFn_AmdK8McCtlMaskN,
301 kCpumMsrRdFn_AmdK8SmiOnIoTrapN,
302 kCpumMsrRdFn_AmdK8SmiOnIoTrapCtlSts,
303 kCpumMsrRdFn_AmdK8IntPendingMessage,
304 kCpumMsrRdFn_AmdK8SmiTriggerIoCycle,
305 kCpumMsrRdFn_AmdFam10hMmioCfgBaseAddr,
306 kCpumMsrRdFn_AmdFam10hTrapCtlMaybe,
307 kCpumMsrRdFn_AmdFam10hPStateCurLimit, /**< Returns range value. */
308 kCpumMsrRdFn_AmdFam10hPStateControl, /**< Returns range value. */
309 kCpumMsrRdFn_AmdFam10hPStateStatus, /**< Returns range value. */
310 kCpumMsrRdFn_AmdFam10hPStateN, /**< Returns range value. This isn't an register index! */
311 kCpumMsrRdFn_AmdFam10hCofVidControl, /**< Returns range value. */
312 kCpumMsrRdFn_AmdFam10hCofVidStatus, /**< Returns range value. */
313 kCpumMsrRdFn_AmdFam10hCStateIoBaseAddr,
314 kCpumMsrRdFn_AmdFam10hCpuWatchdogTimer,
315 kCpumMsrRdFn_AmdK8SmmBase,
316 kCpumMsrRdFn_AmdK8SmmAddr,
317 kCpumMsrRdFn_AmdK8SmmMask,
318 kCpumMsrRdFn_AmdK8VmCr,
319 kCpumMsrRdFn_AmdK8IgnNe,
320 kCpumMsrRdFn_AmdK8SmmCtl,
321 kCpumMsrRdFn_AmdK8VmHSavePa,
322 kCpumMsrRdFn_AmdFam10hVmLockKey,
323 kCpumMsrRdFn_AmdFam10hSmmLockKey,
324 kCpumMsrRdFn_AmdFam10hLocalSmiStatus,
325 kCpumMsrRdFn_AmdFam10hOsVisWrkIdLength,
326 kCpumMsrRdFn_AmdFam10hOsVisWrkStatus,
327 kCpumMsrRdFn_AmdFam16hL2IPerfCtlN,
328 kCpumMsrRdFn_AmdFam16hL2IPerfCtrN,
329 kCpumMsrRdFn_AmdFam15hNorthbridgePerfCtlN,
330 kCpumMsrRdFn_AmdFam15hNorthbridgePerfCtrN,
331 kCpumMsrRdFn_AmdK7MicrocodeCtl, /**< Returns range value. */
332 kCpumMsrRdFn_AmdK7ClusterIdMaybe, /**< Returns range value. */
333 kCpumMsrRdFn_AmdK8CpuIdCtlStd07hEbax,
334 kCpumMsrRdFn_AmdK8CpuIdCtlStd06hEcx,
335 kCpumMsrRdFn_AmdK8CpuIdCtlStd01hEdcx,
336 kCpumMsrRdFn_AmdK8CpuIdCtlExt01hEdcx,
337 kCpumMsrRdFn_AmdK8PatchLevel, /**< Returns range value. */
338 kCpumMsrRdFn_AmdK7DebugStatusMaybe,
339 kCpumMsrRdFn_AmdK7BHTraceBaseMaybe,
340 kCpumMsrRdFn_AmdK7BHTracePtrMaybe,
341 kCpumMsrRdFn_AmdK7BHTraceLimitMaybe,
342 kCpumMsrRdFn_AmdK7HardwareDebugToolCfgMaybe,
343 kCpumMsrRdFn_AmdK7FastFlushCountMaybe,
344 kCpumMsrRdFn_AmdK7NodeId,
345 kCpumMsrRdFn_AmdK7DrXAddrMaskN, /**< Takes register index. */
346 kCpumMsrRdFn_AmdK7Dr0DataMatchMaybe,
347 kCpumMsrRdFn_AmdK7Dr0DataMaskMaybe,
348 kCpumMsrRdFn_AmdK7LoadStoreCfg,
349 kCpumMsrRdFn_AmdK7InstrCacheCfg,
350 kCpumMsrRdFn_AmdK7DataCacheCfg,
351 kCpumMsrRdFn_AmdK7BusUnitCfg,
352 kCpumMsrRdFn_AmdK7DebugCtl2Maybe,
353 kCpumMsrRdFn_AmdFam15hFpuCfg,
354 kCpumMsrRdFn_AmdFam15hDecoderCfg,
355 kCpumMsrRdFn_AmdFam10hBusUnitCfg2,
356 kCpumMsrRdFn_AmdFam15hCombUnitCfg,
357 kCpumMsrRdFn_AmdFam15hCombUnitCfg2,
358 kCpumMsrRdFn_AmdFam15hCombUnitCfg3,
359 kCpumMsrRdFn_AmdFam15hExecUnitCfg,
360 kCpumMsrRdFn_AmdFam15hLoadStoreCfg2,
361 kCpumMsrRdFn_AmdFam10hIbsFetchCtl,
362 kCpumMsrRdFn_AmdFam10hIbsFetchLinAddr,
363 kCpumMsrRdFn_AmdFam10hIbsFetchPhysAddr,
364 kCpumMsrRdFn_AmdFam10hIbsOpExecCtl,
365 kCpumMsrRdFn_AmdFam10hIbsOpRip,
366 kCpumMsrRdFn_AmdFam10hIbsOpData,
367 kCpumMsrRdFn_AmdFam10hIbsOpData2,
368 kCpumMsrRdFn_AmdFam10hIbsOpData3,
369 kCpumMsrRdFn_AmdFam10hIbsDcLinAddr,
370 kCpumMsrRdFn_AmdFam10hIbsDcPhysAddr,
371 kCpumMsrRdFn_AmdFam10hIbsCtl,
372 kCpumMsrRdFn_AmdFam14hIbsBrTarget,
373
374 /** End of valid MSR read function indexes. */
375 kCpumMsrRdFn_End
376} CPUMMSRRDFN;
377
378/**
379 * MSR write functions.
380 */
381typedef enum CPUMMSRWRFN
382{
383 /** Invalid zero value. */
384 kCpumMsrWrFn_Invalid = 0,
385 /** Writes are ignored, the fWrGpMask is observed though. */
386 kCpumMsrWrFn_IgnoreWrite,
387 /** Writes cause GP(0) to be raised, the fWrGpMask should be UINT64_MAX. */
388 kCpumMsrWrFn_ReadOnly,
389 /** Alias to the MSR range starting at the MSR given by
390 * CPUMMSRRANGE::uValue. Must be used in pair with
391 * kCpumMsrRdFn_MsrAlias. */
392 kCpumMsrWrFn_MsrAlias,
393
394 kCpumMsrWrFn_Ia32P5McAddr,
395 kCpumMsrWrFn_Ia32P5McType,
396 kCpumMsrWrFn_Ia32TimestampCounter,
397 kCpumMsrWrFn_Ia32ApicBase,
398 kCpumMsrWrFn_Ia32FeatureControl,
399 kCpumMsrWrFn_Ia32BiosSignId,
400 kCpumMsrWrFn_Ia32BiosUpdateTrigger,
401 kCpumMsrWrFn_Ia32SmmMonitorCtl,
402 kCpumMsrWrFn_Ia32PmcN,
403 kCpumMsrWrFn_Ia32MonitorFilterLineSize,
404 kCpumMsrWrFn_Ia32MPerf,
405 kCpumMsrWrFn_Ia32APerf,
406 kCpumMsrWrFn_Ia32MtrrPhysBaseN, /**< Takes register number. */
407 kCpumMsrWrFn_Ia32MtrrPhysMaskN, /**< Takes register number. */
408 kCpumMsrWrFn_Ia32MtrrFixed, /**< Takes CPUMCPU offset. */
409 kCpumMsrWrFn_Ia32MtrrDefType,
410 kCpumMsrWrFn_Ia32Pat,
411 kCpumMsrWrFn_Ia32SysEnterCs,
412 kCpumMsrWrFn_Ia32SysEnterEsp,
413 kCpumMsrWrFn_Ia32SysEnterEip,
414 kCpumMsrWrFn_Ia32McgStatus,
415 kCpumMsrWrFn_Ia32McgCtl,
416 kCpumMsrWrFn_Ia32DebugCtl,
417 kCpumMsrWrFn_Ia32SmrrPhysBase,
418 kCpumMsrWrFn_Ia32SmrrPhysMask,
419 kCpumMsrWrFn_Ia32PlatformDcaCap,
420 kCpumMsrWrFn_Ia32Dca0Cap,
421 kCpumMsrWrFn_Ia32PerfEvtSelN, /**< Range value indicates the register number. */
422 kCpumMsrWrFn_Ia32PerfStatus,
423 kCpumMsrWrFn_Ia32PerfCtl,
424 kCpumMsrWrFn_Ia32FixedCtrN, /**< Takes register number of start of range. */
425 kCpumMsrWrFn_Ia32PerfCapabilities,
426 kCpumMsrWrFn_Ia32FixedCtrCtrl,
427 kCpumMsrWrFn_Ia32PerfGlobalStatus,
428 kCpumMsrWrFn_Ia32PerfGlobalCtrl,
429 kCpumMsrWrFn_Ia32PerfGlobalOvfCtrl,
430 kCpumMsrWrFn_Ia32PebsEnable,
431 kCpumMsrWrFn_Ia32ClockModulation,
432 kCpumMsrWrFn_Ia32ThermInterrupt,
433 kCpumMsrWrFn_Ia32ThermStatus,
434 kCpumMsrWrFn_Ia32Therm2Ctl,
435 kCpumMsrWrFn_Ia32MiscEnable,
436 kCpumMsrWrFn_Ia32McCtlStatusAddrMiscN, /**< Takes bank number. */
437 kCpumMsrWrFn_Ia32McNCtl2, /**< Takes register number of start of range. */
438 kCpumMsrWrFn_Ia32DsArea,
439 kCpumMsrWrFn_Ia32TscDeadline,
440 kCpumMsrWrFn_Ia32X2ApicN,
441 kCpumMsrWrFn_Ia32DebugInterface,
442
443 kCpumMsrWrFn_Amd64Efer,
444 kCpumMsrWrFn_Amd64SyscallTarget,
445 kCpumMsrWrFn_Amd64LongSyscallTarget,
446 kCpumMsrWrFn_Amd64CompSyscallTarget,
447 kCpumMsrWrFn_Amd64SyscallFlagMask,
448 kCpumMsrWrFn_Amd64FsBase,
449 kCpumMsrWrFn_Amd64GsBase,
450 kCpumMsrWrFn_Amd64KernelGsBase,
451 kCpumMsrWrFn_Amd64TscAux,
452 kCpumMsrWrFn_IntelEblCrPowerOn,
453 kCpumMsrWrFn_IntelP4EbcHardPowerOn,
454 kCpumMsrWrFn_IntelP4EbcSoftPowerOn,
455 kCpumMsrWrFn_IntelP4EbcFrequencyId,
456 kCpumMsrWrFn_IntelPkgCStConfigControl,
457 kCpumMsrWrFn_IntelPmgIoCaptureBase,
458 kCpumMsrWrFn_IntelLastBranchFromToN,
459 kCpumMsrWrFn_IntelLastBranchFromN,
460 kCpumMsrWrFn_IntelLastBranchToN,
461 kCpumMsrWrFn_IntelLastBranchTos,
462 kCpumMsrWrFn_IntelBblCrCtl,
463 kCpumMsrWrFn_IntelBblCrCtl3,
464 kCpumMsrWrFn_IntelI7TemperatureTarget,
465 kCpumMsrWrFn_IntelI7MsrOffCoreResponseN, /**< Takes register number. */
466 kCpumMsrWrFn_IntelI7MiscPwrMgmt,
467 kCpumMsrWrFn_IntelP6CrN,
468 kCpumMsrWrFn_IntelCpuId1FeatureMaskEcdx,
469 kCpumMsrWrFn_IntelCpuId1FeatureMaskEax,
470 kCpumMsrWrFn_IntelCpuId80000001FeatureMaskEcdx,
471 kCpumMsrWrFn_IntelI7SandyAesNiCtl,
472 kCpumMsrWrFn_IntelI7TurboRatioLimit,
473 kCpumMsrWrFn_IntelI7LbrSelect,
474 kCpumMsrWrFn_IntelI7SandyErrorControl,
475 kCpumMsrWrFn_IntelI7PowerCtl,
476 kCpumMsrWrFn_IntelI7SandyPebsNumAlt,
477 kCpumMsrWrFn_IntelI7PebsLdLat,
478 kCpumMsrWrFn_IntelI7SandyVrCurrentConfig,
479 kCpumMsrWrFn_IntelI7SandyVrMiscConfig,
480 kCpumMsrWrFn_IntelI7SandyPkgCnIrtlN,
481 kCpumMsrWrFn_IntelI7RaplPkgPowerLimit,
482 kCpumMsrWrFn_IntelI7RaplDramPowerLimit,
483 kCpumMsrWrFn_IntelI7RaplPp0PowerLimit,
484 kCpumMsrWrFn_IntelI7RaplPp0Policy,
485 kCpumMsrWrFn_IntelI7RaplPp1PowerLimit,
486 kCpumMsrWrFn_IntelI7RaplPp1Policy,
487 kCpumMsrWrFn_IntelI7IvyConfigTdpControl,
488 kCpumMsrWrFn_IntelI7IvyTurboActivationRatio,
489 kCpumMsrWrFn_IntelI7UncPerfGlobalCtrl,
490 kCpumMsrWrFn_IntelI7UncPerfGlobalStatus,
491 kCpumMsrWrFn_IntelI7UncPerfGlobalOvfCtrl,
492 kCpumMsrWrFn_IntelI7UncPerfFixedCtrCtrl,
493 kCpumMsrWrFn_IntelI7UncPerfFixedCtr,
494 kCpumMsrWrFn_IntelI7UncArbPerfCtrN,
495 kCpumMsrWrFn_IntelI7UncArbPerfEvtSelN,
496 kCpumMsrWrFn_IntelCore2EmttmCrTablesN,
497 kCpumMsrWrFn_IntelCore2SmmCStMiscInfo,
498 kCpumMsrWrFn_IntelCore1ExtConfig,
499 kCpumMsrWrFn_IntelCore1DtsCalControl,
500 kCpumMsrWrFn_IntelCore2PeciControl,
501
502 kCpumMsrWrFn_P6LastIntFromIp,
503 kCpumMsrWrFn_P6LastIntToIp,
504
505 kCpumMsrWrFn_AmdFam15hTscRate,
506 kCpumMsrWrFn_AmdFam15hLwpCfg,
507 kCpumMsrWrFn_AmdFam15hLwpCbAddr,
508 kCpumMsrWrFn_AmdFam10hMc4MiscN,
509 kCpumMsrWrFn_AmdK8PerfCtlN,
510 kCpumMsrWrFn_AmdK8PerfCtrN,
511 kCpumMsrWrFn_AmdK8SysCfg,
512 kCpumMsrWrFn_AmdK8HwCr,
513 kCpumMsrWrFn_AmdK8IorrBaseN,
514 kCpumMsrWrFn_AmdK8IorrMaskN,
515 kCpumMsrWrFn_AmdK8TopOfMemN,
516 kCpumMsrWrFn_AmdK8NbCfg1,
517 kCpumMsrWrFn_AmdK8McXcptRedir,
518 kCpumMsrWrFn_AmdK8CpuNameN,
519 kCpumMsrWrFn_AmdK8HwThermalCtrl,
520 kCpumMsrWrFn_AmdK8SwThermalCtrl,
521 kCpumMsrWrFn_AmdK8FidVidControl,
522 kCpumMsrWrFn_AmdK8McCtlMaskN,
523 kCpumMsrWrFn_AmdK8SmiOnIoTrapN,
524 kCpumMsrWrFn_AmdK8SmiOnIoTrapCtlSts,
525 kCpumMsrWrFn_AmdK8IntPendingMessage,
526 kCpumMsrWrFn_AmdK8SmiTriggerIoCycle,
527 kCpumMsrWrFn_AmdFam10hMmioCfgBaseAddr,
528 kCpumMsrWrFn_AmdFam10hTrapCtlMaybe,
529 kCpumMsrWrFn_AmdFam10hPStateControl,
530 kCpumMsrWrFn_AmdFam10hPStateStatus,
531 kCpumMsrWrFn_AmdFam10hPStateN,
532 kCpumMsrWrFn_AmdFam10hCofVidControl,
533 kCpumMsrWrFn_AmdFam10hCofVidStatus,
534 kCpumMsrWrFn_AmdFam10hCStateIoBaseAddr,
535 kCpumMsrWrFn_AmdFam10hCpuWatchdogTimer,
536 kCpumMsrWrFn_AmdK8SmmBase,
537 kCpumMsrWrFn_AmdK8SmmAddr,
538 kCpumMsrWrFn_AmdK8SmmMask,
539 kCpumMsrWrFn_AmdK8VmCr,
540 kCpumMsrWrFn_AmdK8IgnNe,
541 kCpumMsrWrFn_AmdK8SmmCtl,
542 kCpumMsrWrFn_AmdK8VmHSavePa,
543 kCpumMsrWrFn_AmdFam10hVmLockKey,
544 kCpumMsrWrFn_AmdFam10hSmmLockKey,
545 kCpumMsrWrFn_AmdFam10hLocalSmiStatus,
546 kCpumMsrWrFn_AmdFam10hOsVisWrkIdLength,
547 kCpumMsrWrFn_AmdFam10hOsVisWrkStatus,
548 kCpumMsrWrFn_AmdFam16hL2IPerfCtlN,
549 kCpumMsrWrFn_AmdFam16hL2IPerfCtrN,
550 kCpumMsrWrFn_AmdFam15hNorthbridgePerfCtlN,
551 kCpumMsrWrFn_AmdFam15hNorthbridgePerfCtrN,
552 kCpumMsrWrFn_AmdK7MicrocodeCtl,
553 kCpumMsrWrFn_AmdK7ClusterIdMaybe,
554 kCpumMsrWrFn_AmdK8CpuIdCtlStd07hEbax,
555 kCpumMsrWrFn_AmdK8CpuIdCtlStd06hEcx,
556 kCpumMsrWrFn_AmdK8CpuIdCtlStd01hEdcx,
557 kCpumMsrWrFn_AmdK8CpuIdCtlExt01hEdcx,
558 kCpumMsrWrFn_AmdK8PatchLoader,
559 kCpumMsrWrFn_AmdK7DebugStatusMaybe,
560 kCpumMsrWrFn_AmdK7BHTraceBaseMaybe,
561 kCpumMsrWrFn_AmdK7BHTracePtrMaybe,
562 kCpumMsrWrFn_AmdK7BHTraceLimitMaybe,
563 kCpumMsrWrFn_AmdK7HardwareDebugToolCfgMaybe,
564 kCpumMsrWrFn_AmdK7FastFlushCountMaybe,
565 kCpumMsrWrFn_AmdK7NodeId,
566 kCpumMsrWrFn_AmdK7DrXAddrMaskN, /**< Takes register index. */
567 kCpumMsrWrFn_AmdK7Dr0DataMatchMaybe,
568 kCpumMsrWrFn_AmdK7Dr0DataMaskMaybe,
569 kCpumMsrWrFn_AmdK7LoadStoreCfg,
570 kCpumMsrWrFn_AmdK7InstrCacheCfg,
571 kCpumMsrWrFn_AmdK7DataCacheCfg,
572 kCpumMsrWrFn_AmdK7BusUnitCfg,
573 kCpumMsrWrFn_AmdK7DebugCtl2Maybe,
574 kCpumMsrWrFn_AmdFam15hFpuCfg,
575 kCpumMsrWrFn_AmdFam15hDecoderCfg,
576 kCpumMsrWrFn_AmdFam10hBusUnitCfg2,
577 kCpumMsrWrFn_AmdFam15hCombUnitCfg,
578 kCpumMsrWrFn_AmdFam15hCombUnitCfg2,
579 kCpumMsrWrFn_AmdFam15hCombUnitCfg3,
580 kCpumMsrWrFn_AmdFam15hExecUnitCfg,
581 kCpumMsrWrFn_AmdFam15hLoadStoreCfg2,
582 kCpumMsrWrFn_AmdFam10hIbsFetchCtl,
583 kCpumMsrWrFn_AmdFam10hIbsFetchLinAddr,
584 kCpumMsrWrFn_AmdFam10hIbsFetchPhysAddr,
585 kCpumMsrWrFn_AmdFam10hIbsOpExecCtl,
586 kCpumMsrWrFn_AmdFam10hIbsOpRip,
587 kCpumMsrWrFn_AmdFam10hIbsOpData,
588 kCpumMsrWrFn_AmdFam10hIbsOpData2,
589 kCpumMsrWrFn_AmdFam10hIbsOpData3,
590 kCpumMsrWrFn_AmdFam10hIbsDcLinAddr,
591 kCpumMsrWrFn_AmdFam10hIbsDcPhysAddr,
592 kCpumMsrWrFn_AmdFam10hIbsCtl,
593 kCpumMsrWrFn_AmdFam14hIbsBrTarget,
594
595 /** End of valid MSR write function indexes. */
596 kCpumMsrWrFn_End
597} CPUMMSRWRFN;
598
599/**
600 * MSR range.
601 */
602typedef struct CPUMMSRRANGE
603{
604 /** The first MSR. [0] */
605 uint32_t uFirst;
606 /** The last MSR. [4] */
607 uint32_t uLast;
608 /** The read function (CPUMMSRRDFN). [8] */
609 uint16_t enmRdFn;
610 /** The write function (CPUMMSRWRFN). [10] */
611 uint16_t enmWrFn;
612 /** The offset of the 64-bit MSR value relative to the start of CPUMCPU.
613 * UINT16_MAX if not used by the read and write functions. [12] */
614 uint16_t offCpumCpu;
615 /** Reserved for future hacks. [14] */
616 uint16_t fReserved;
617 /** The init/read value. [16]
618 * When enmRdFn is kCpumMsrRdFn_INIT_VALUE, this is the value returned on RDMSR.
619 * offCpumCpu must be UINT16_MAX in that case, otherwise it must be a valid
620 * offset into CPUM. */
621 uint64_t uValue;
622 /** The bits to ignore when writing. [24] */
623 uint64_t fWrIgnMask;
624 /** The bits that will cause a GP(0) when writing. [32]
625 * This is always checked prior to calling the write function. Using
626 * UINT64_MAX effectively marks the MSR as read-only. */
627 uint64_t fWrGpMask;
628 /** The register name, if applicable. [40] */
629 char szName[56];
630
631#ifdef VBOX_WITH_STATISTICS
632 /** The number of reads. */
633 STAMCOUNTER cReads;
634 /** The number of writes. */
635 STAMCOUNTER cWrites;
636 /** The number of times ignored bits were written. */
637 STAMCOUNTER cIgnoredBits;
638 /** The number of GPs generated. */
639 STAMCOUNTER cGps;
640#endif
641} CPUMMSRRANGE;
642#ifdef VBOX_WITH_STATISTICS
643AssertCompileSize(CPUMMSRRANGE, 128);
644#else
645AssertCompileSize(CPUMMSRRANGE, 96);
646#endif
647/** Pointer to an MSR range. */
648typedef CPUMMSRRANGE *PCPUMMSRRANGE;
649/** Pointer to a const MSR range. */
650typedef CPUMMSRRANGE const *PCCPUMMSRRANGE;
651
652
653
654
655/**
656 * CPU features and quirks.
657 * This is mostly exploded CPUID info.
658 */
659typedef struct CPUMFEATURES
660{
661 /** The CPU vendor (CPUMCPUVENDOR). */
662 uint8_t enmCpuVendor;
663 /** The CPU family. */
664 uint8_t uFamily;
665 /** The CPU model. */
666 uint8_t uModel;
667 /** The CPU stepping. */
668 uint8_t uStepping;
669 /** The microarchitecture. */
670 CPUMMICROARCH enmMicroarch;
671 /** The maximum physical address with of the CPU. */
672 uint8_t cMaxPhysAddrWidth;
673 /** Alignment padding. */
674 uint8_t abPadding[3];
675
676 /** Supports MSRs. */
677 uint32_t fMsr : 1;
678 /** Supports the page size extension (4/2 MB pages). */
679 uint32_t fPse : 1;
680 /** Supports 36-bit page size extension (4 MB pages can map memory above
681 * 4GB). */
682 uint32_t fPse36 : 1;
683 /** Supports physical address extension (PAE). */
684 uint32_t fPae : 1;
685 /** Page attribute table (PAT) support (page level cache control). */
686 uint32_t fPat : 1;
687 /** Supports the FXSAVE and FXRSTOR instructions. */
688 uint32_t fFxSaveRstor : 1;
689 /** Intel SYSENTER/SYSEXIT support */
690 uint32_t fSysEnter : 1;
691 /** First generation APIC. */
692 uint32_t fApic : 1;
693 /** Second generation APIC. */
694 uint32_t fX2Apic : 1;
695 /** Hypervisor present. */
696 uint32_t fHypervisorPresent : 1;
697 /** MWAIT & MONITOR instructions supported. */
698 uint32_t fMonitorMWait : 1;
699
700 /** AMD64: Supports long mode. */
701 uint32_t fLongMode : 1;
702 /** AMD64: SYSCALL/SYSRET support. */
703 uint32_t fSysCall : 1;
704 /** AMD64: No-execute page table bit. */
705 uint32_t fNoExecute : 1;
706 /** AMD64: Supports LAHF & SAHF instructions in 64-bit mode. */
707 uint32_t fLahfSahf : 1;
708 /** AMD64: Supports RDTSCP. */
709 uint32_t fRdTscP : 1;
710
711 /** Indicates that FPU instruction and data pointers may leak.
712 * This generally applies to recent AMD CPUs, where the FPU IP and DP pointer
713 * is only saved and restored if an exception is pending. */
714 uint32_t fLeakyFxSR : 1;
715
716 /** Alignment padding. */
717 uint32_t fPadding : 9;
718
719 uint64_t auPadding[2];
720} CPUMFEATURES;
721AssertCompileSize(CPUMFEATURES, 32);
722/** Pointer to a CPU feature structure. */
723typedef CPUMFEATURES *PCPUMFEATURES;
724/** Pointer to a const CPU feature structure. */
725typedef CPUMFEATURES const *PCCPUMFEATURES;
726
727
728/**
729 * CPU info
730 */
731typedef struct CPUMINFO
732{
733 /** The number of MSR ranges (CPUMMSRRANGE) in the array pointed to below. */
734 uint32_t cMsrRanges;
735 /** Mask applied to ECX before looking up the MSR for a RDMSR/WRMSR
736 * instruction. Older hardware has been observed to ignore higher bits. */
737 uint32_t fMsrMask;
738
739 /** The number of CPUID leaves (CPUMCPUIDLEAF) in the array pointed to below. */
740 uint32_t cCpuIdLeaves;
741 /** The index of the first extended CPUID leaf in the array.
742 * Set to cCpuIdLeaves if none present. */
743 uint32_t iFirstExtCpuIdLeaf;
744 /** How to handle unknown CPUID leaves. */
745 CPUMUKNOWNCPUID enmUnknownCpuIdMethod;
746 /** For use with CPUMUKNOWNCPUID_DEFAULTS. */
747 CPUMCPUID DefCpuId;
748
749 /** Alignment padding. */
750 uint32_t uPadding;
751
752 /** Pointer to the MSR ranges (ring-0 pointer). */
753 R0PTRTYPE(PCPUMMSRRANGE) paMsrRangesR0;
754 /** Pointer to the CPUID leaves (ring-0 pointer). */
755 R0PTRTYPE(PCPUMCPUIDLEAF) paCpuIdLeavesR0;
756
757 /** Pointer to the MSR ranges (ring-3 pointer). */
758 R3PTRTYPE(PCPUMMSRRANGE) paMsrRangesR3;
759 /** Pointer to the CPUID leaves (ring-3 pointer). */
760 R3PTRTYPE(PCPUMCPUIDLEAF) paCpuIdLeavesR3;
761
762 /** Pointer to the MSR ranges (raw-mode context pointer). */
763 RCPTRTYPE(PCPUMMSRRANGE) paMsrRangesRC;
764 /** Pointer to the CPUID leaves (raw-mode context pointer). */
765 RCPTRTYPE(PCPUMCPUIDLEAF) paCpuIdLeavesRC;
766} CPUMINFO;
767/** Pointer to a CPU info structure. */
768typedef CPUMINFO *PCPUMINFO;
769/** Pointer to a const CPU info structure. */
770typedef CPUMINFO const *CPCPUMINFO;
771
772
773/**
774 * The saved host CPU state.
775 *
776 * @remark The special VBOX_WITH_HYBRID_32BIT_KERNEL checks here are for the 10.4.x series
777 * of Mac OS X where the OS is essentially 32-bit but the cpu mode can be 64-bit.
778 */
779typedef struct CPUMHOSTCTX
780{
781 /** FPU state. (16-byte alignment)
782 * @remark On x86, the format isn't necessarily X86FXSTATE (not important). */
783 X86FXSTATE fpu;
784
785 /** General purpose register, selectors, flags and more
786 * @{ */
787#if HC_ARCH_BITS == 64 || defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
788 /** General purpose register ++
789 * { */
790 /*uint64_t rax; - scratch*/
791 uint64_t rbx;
792 /*uint64_t rcx; - scratch*/
793 /*uint64_t rdx; - scratch*/
794 uint64_t rdi;
795 uint64_t rsi;
796 uint64_t rbp;
797 uint64_t rsp;
798 /*uint64_t r8; - scratch*/
799 /*uint64_t r9; - scratch*/
800 uint64_t r10;
801 uint64_t r11;
802 uint64_t r12;
803 uint64_t r13;
804 uint64_t r14;
805 uint64_t r15;
806 /*uint64_t rip; - scratch*/
807 uint64_t rflags;
808#endif
809
810#if HC_ARCH_BITS == 32
811 /*uint32_t eax; - scratch*/
812 uint32_t ebx;
813 /*uint32_t ecx; - scratch*/
814 /*uint32_t edx; - scratch*/
815 uint32_t edi;
816 uint32_t esi;
817 uint32_t ebp;
818 X86EFLAGS eflags;
819 /*uint32_t eip; - scratch*/
820 /* lss pair! */
821 uint32_t esp;
822#endif
823 /** @} */
824
825 /** Selector registers
826 * @{ */
827 RTSEL ss;
828 RTSEL ssPadding;
829 RTSEL gs;
830 RTSEL gsPadding;
831 RTSEL fs;
832 RTSEL fsPadding;
833 RTSEL es;
834 RTSEL esPadding;
835 RTSEL ds;
836 RTSEL dsPadding;
837 RTSEL cs;
838 RTSEL csPadding;
839 /** @} */
840
841#if HC_ARCH_BITS == 32 && !defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
842 /** Control registers.
843 * @{ */
844 uint32_t cr0;
845 /*uint32_t cr2; - scratch*/
846 uint32_t cr3;
847 uint32_t cr4;
848 /** @} */
849
850 /** Debug registers.
851 * @{ */
852 uint32_t dr0;
853 uint32_t dr1;
854 uint32_t dr2;
855 uint32_t dr3;
856 uint32_t dr6;
857 uint32_t dr7;
858 /** @} */
859
860 /** Global Descriptor Table register. */
861 X86XDTR32 gdtr;
862 uint16_t gdtrPadding;
863 /** Interrupt Descriptor Table register. */
864 X86XDTR32 idtr;
865 uint16_t idtrPadding;
866 /** The task register. */
867 RTSEL ldtr;
868 RTSEL ldtrPadding;
869 /** The task register. */
870 RTSEL tr;
871 RTSEL trPadding;
872 uint32_t SysEnterPadding;
873
874 /** The sysenter msr registers.
875 * This member is not used by the hypervisor context. */
876 CPUMSYSENTER SysEnter;
877
878 /** MSRs
879 * @{ */
880 uint64_t efer;
881 /** @} */
882
883 /* padding to get 64byte aligned size */
884 uint8_t auPadding[16+32];
885
886#elif HC_ARCH_BITS == 64 || defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
887
888 /** Control registers.
889 * @{ */
890 uint64_t cr0;
891 /*uint64_t cr2; - scratch*/
892 uint64_t cr3;
893 uint64_t cr4;
894 uint64_t cr8;
895 /** @} */
896
897 /** Debug registers.
898 * @{ */
899 uint64_t dr0;
900 uint64_t dr1;
901 uint64_t dr2;
902 uint64_t dr3;
903 uint64_t dr6;
904 uint64_t dr7;
905 /** @} */
906
907 /** Global Descriptor Table register. */
908 X86XDTR64 gdtr;
909 uint16_t gdtrPadding;
910 /** Interrupt Descriptor Table register. */
911 X86XDTR64 idtr;
912 uint16_t idtrPadding;
913 /** The task register. */
914 RTSEL ldtr;
915 RTSEL ldtrPadding;
916 /** The task register. */
917 RTSEL tr;
918 RTSEL trPadding;
919
920 /** MSRs
921 * @{ */
922 CPUMSYSENTER SysEnter;
923 uint64_t FSbase;
924 uint64_t GSbase;
925 uint64_t efer;
926 /** @} */
927
928 /* padding to get 32byte aligned size */
929# ifdef VBOX_WITH_HYBRID_32BIT_KERNEL
930 uint8_t auPadding[16];
931# else
932 uint8_t auPadding[8+32];
933# endif
934
935#else
936# error HC_ARCH_BITS not defined
937#endif
938} CPUMHOSTCTX;
939/** Pointer to the saved host CPU state. */
940typedef CPUMHOSTCTX *PCPUMHOSTCTX;
941
942
943/**
944 * CPUM Data (part of VM)
945 */
946typedef struct CPUM
947{
948 /** Offset from CPUM to CPUMCPU for the first CPU. */
949 uint32_t offCPUMCPU0;
950
951 /** Use flags.
952 * These flags indicates which CPU features the host uses.
953 */
954 uint32_t fHostUseFlags;
955
956 /** Host CPU Features - ECX */
957 struct
958 {
959 /** edx part */
960 X86CPUIDFEATEDX edx;
961 /** ecx part */
962 X86CPUIDFEATECX ecx;
963 } CPUFeatures;
964 /** Host extended CPU features. */
965 struct
966 {
967 /** edx part */
968 uint32_t edx;
969 /** ecx part */
970 uint32_t ecx;
971 } CPUFeaturesExt;
972
973 /** CR4 mask */
974 struct
975 {
976 uint32_t AndMask; /**< @todo Move these to the per-CPU structure and fix the switchers. Saves a register! */
977 uint32_t OrMask;
978 } CR4;
979
980 /** The (more) portable CPUID level. */
981 uint8_t u8PortableCpuIdLevel;
982 /** Indicates that a state restore is pending.
983 * This is used to verify load order dependencies (PGM). */
984 bool fPendingRestore;
985 uint8_t abPadding[HC_ARCH_BITS == 64 ? 6 : 2];
986
987 /** The standard set of CpuId leaves. */
988 CPUMCPUID aGuestCpuIdStd[6];
989 /** The extended set of CpuId leaves. */
990 CPUMCPUID aGuestCpuIdExt[10];
991 /** The centaur set of CpuId leaves. */
992 CPUMCPUID aGuestCpuIdCentaur[4];
993 /** The hypervisor specific set of CpuId leaves. */
994 CPUMCPUID aGuestCpuIdHyper[4];
995 /** The default set of CpuId leaves. */
996 CPUMCPUID GuestCpuIdDef;
997
998#if HC_ARCH_BITS == 32
999 uint8_t abPadding2[4];
1000#endif
1001
1002 /** Guest CPU info. */
1003 CPUMINFO GuestInfo;
1004 /** Guest CPU feature information. */
1005 CPUMFEATURES GuestFeatures;
1006 /** Host CPU feature information. */
1007 CPUMFEATURES HostFeatures;
1008
1009 /** @name MSR statistics.
1010 * @{ */
1011 STAMCOUNTER cMsrWrites;
1012 STAMCOUNTER cMsrWritesToIgnoredBits;
1013 STAMCOUNTER cMsrWritesRaiseGp;
1014 STAMCOUNTER cMsrWritesUnknown;
1015 STAMCOUNTER cMsrReads;
1016 STAMCOUNTER cMsrReadsRaiseGp;
1017 STAMCOUNTER cMsrReadsUnknown;
1018 /** @} */
1019} CPUM;
1020/** Pointer to the CPUM instance data residing in the shared VM structure. */
1021typedef CPUM *PCPUM;
1022
1023/**
1024 * CPUM Data (part of VMCPU)
1025 */
1026typedef struct CPUMCPU
1027{
1028 /**
1029 * Hypervisor context.
1030 * Aligned on a 64-byte boundary.
1031 */
1032 CPUMCTX Hyper;
1033
1034 /**
1035 * Saved host context. Only valid while inside GC.
1036 * Aligned on a 64-byte boundary.
1037 */
1038 CPUMHOSTCTX Host;
1039
1040#ifdef VBOX_WITH_CRASHDUMP_MAGIC
1041 uint8_t aMagic[56];
1042 uint64_t uMagic;
1043#endif
1044
1045 /**
1046 * Guest context.
1047 * Aligned on a 64-byte boundary.
1048 */
1049 CPUMCTX Guest;
1050
1051 /**
1052 * Guest context - misc MSRs
1053 * Aligned on a 64-byte boundary.
1054 */
1055 CPUMCTXMSRS GuestMsrs;
1056
1057 /** Use flags.
1058 * These flags indicates both what is to be used and what has been used.
1059 */
1060 uint32_t fUseFlags;
1061
1062 /** Changed flags.
1063 * These flags indicates to REM (and others) which important guest
1064 * registers which has been changed since last time the flags were cleared.
1065 * See the CPUM_CHANGED_* defines for what we keep track of.
1066 */
1067 uint32_t fChanged;
1068
1069 /** Offset from CPUM to CPUMCPU. */
1070 uint32_t offCPUM;
1071
1072 /** Temporary storage for the return code of the function called in the
1073 * 32-64 switcher. */
1074 uint32_t u32RetCode;
1075
1076#ifdef VBOX_WITH_VMMR0_DISABLE_LAPIC_NMI
1077 /** The address of the APIC mapping, NULL if no APIC.
1078 * Call CPUMR0SetLApic to update this before doing a world switch. */
1079 RTHCPTR pvApicBase;
1080 /** Used by the world switcher code to store which vectors needs restoring on
1081 * the way back. */
1082 uint32_t fApicDisVectors;
1083 /** Set if the CPU has the X2APIC mode enabled.
1084 * Call CPUMR0SetLApic to update this before doing a world switch. */
1085 bool fX2Apic;
1086#else
1087 uint8_t abPadding3[(HC_ARCH_BITS == 64 ? 8 : 4) + 4 + 1];
1088#endif
1089
1090 /** Have we entered raw-mode? */
1091 bool fRawEntered;
1092 /** Have we entered the recompiler? */
1093 bool fRemEntered;
1094
1095 /** Align the structure on a 64-byte boundary. */
1096 uint8_t abPadding2[64 - 16 - (HC_ARCH_BITS == 64 ? 8 : 4) - 4 - 1 - 2];
1097} CPUMCPU;
1098/** Pointer to the CPUMCPU instance data residing in the shared VMCPU structure. */
1099typedef CPUMCPU *PCPUMCPU;
1100
1101#ifndef VBOX_FOR_DTRACE_LIB
1102RT_C_DECLS_BEGIN
1103
1104PCPUMCPUIDLEAF cpumCpuIdGetLeaf(PVM pVM, uint32_t uLeaf, uint32_t uSubLeaf);
1105
1106#ifdef IN_RING3
1107int cpumR3DbgInit(PVM pVM);
1108PCPUMCPUIDLEAF cpumR3CpuIdGetLeaf(PCPUMCPUIDLEAF paLeaves, uint32_t cLeaves, uint32_t uLeaf, uint32_t uSubLeaf);
1109bool cpumR3CpuIdGetLeafLegacy(PCPUMCPUIDLEAF paLeaves, uint32_t cLeaves, uint32_t uLeaf, uint32_t uSubLeaf,
1110 PCPUMCPUID pLeagcy);
1111int cpumR3CpuIdInsert(PCPUMCPUIDLEAF *ppaLeaves, uint32_t *pcLeaves, PCPUMCPUIDLEAF pNewLeaf);
1112void cpumR3CpuIdRemoveRange(PCPUMCPUIDLEAF paLeaves, uint32_t *pcLeaves, uint32_t uFirst, uint32_t uLast);
1113int cpumR3CpuIdExplodeFeatures(PCCPUMCPUIDLEAF paLeaves, uint32_t cLeaves, PCPUMFEATURES pFeatures);
1114int cpumR3DbGetCpuInfo(const char *pszName, PCPUMINFO pInfo);
1115int cpumR3MsrRangesInsert(PCPUMMSRRANGE *ppaMsrRanges, uint32_t *pcMsrRanges, PCCPUMMSRRANGE pNewRange);
1116int cpumR3MsrApplyFudge(PVM pVM);
1117int cpumR3MsrRegStats(PVM pVM);
1118int cpumR3MsrStrictInitChecks(void);
1119PCPUMMSRRANGE cpumLookupMsrRange(PVM pVM, uint32_t idMsr);
1120#endif
1121
1122#ifdef IN_RC
1123DECLASM(int) cpumHandleLazyFPUAsm(PCPUMCPU pCPUM);
1124#endif
1125
1126#ifdef IN_RING0
1127DECLASM(int) cpumR0SaveHostRestoreGuestFPUState(PCPUMCPU pCPUM);
1128DECLASM(int) cpumR0SaveGuestRestoreHostFPUState(PCPUMCPU pCPUM);
1129DECLASM(int) cpumR0SaveHostFPUState(PCPUMCPU pCPUM);
1130DECLASM(int) cpumR0RestoreHostFPUState(PCPUMCPU pCPUM);
1131DECLASM(void) cpumR0LoadFPU(PCPUMCTX pCtx);
1132DECLASM(void) cpumR0SaveFPU(PCPUMCTX pCtx);
1133DECLASM(void) cpumR0LoadXMM(PCPUMCTX pCtx);
1134DECLASM(void) cpumR0SaveXMM(PCPUMCTX pCtx);
1135DECLASM(void) cpumR0SetFCW(uint16_t u16FCW);
1136DECLASM(uint16_t) cpumR0GetFCW(void);
1137DECLASM(void) cpumR0SetMXCSR(uint32_t u32MXCSR);
1138DECLASM(uint32_t) cpumR0GetMXCSR(void);
1139DECLASM(void) cpumR0LoadDRx(uint64_t const *pa4Regs);
1140DECLASM(void) cpumR0SaveDRx(uint64_t *pa4Regs);
1141#endif
1142
1143RT_C_DECLS_END
1144#endif /* !VBOX_FOR_DTRACE_LIB */
1145
1146/** @} */
1147
1148#endif
1149
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