VirtualBox

source: vbox/trunk/src/VBox/VMM/include/CPUMInternal.h@ 51193

Last change on this file since 51193 was 50617, checked in by vboxsync, 11 years ago

Implemented MSR 0x00000035 on i7, it reports threads and core counts on intel.
  • Property svn:eol-style set to native
  • Property svn:keywords set to Id
File size: 42.0 KB
Line 
1/* $Id: CPUMInternal.h 50617 2014-02-26 19:34:46Z vboxsync $ */
2/** @file
3 * CPUM - Internal header file.
4 */
5
6/*
7 * Copyright (C) 2006-2012 Oracle Corporation
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 */
17
18#ifndef ___CPUMInternal_h
19#define ___CPUMInternal_h
20
21#ifndef VBOX_FOR_DTRACE_LIB
22# include <VBox/cdefs.h>
23# include <VBox/types.h>
24# include <VBox/vmm/stam.h>
25# include <iprt/x86.h>
26#else
27# pragma D depends_on library x86.d
28# pragma D depends_on library cpumctx.d
29#endif
30
31
32
33
34/** @defgroup grp_cpum_int Internals
35 * @ingroup grp_cpum
36 * @internal
37 * @{
38 */
39
40/** Flags and types for CPUM fault handlers
41 * @{ */
42/** Type: Load DS */
43#define CPUM_HANDLER_DS 1
44/** Type: Load ES */
45#define CPUM_HANDLER_ES 2
46/** Type: Load FS */
47#define CPUM_HANDLER_FS 3
48/** Type: Load GS */
49#define CPUM_HANDLER_GS 4
50/** Type: IRET */
51#define CPUM_HANDLER_IRET 5
52/** Type mask. */
53#define CPUM_HANDLER_TYPEMASK 0xff
54/** If set EBP points to the CPUMCTXCORE that's being used. */
55#define CPUM_HANDLER_CTXCORE_IN_EBP RT_BIT(31)
56/** @} */
57
58
59/** Use flags (CPUM::fUseFlags).
60 * (Don't forget to sync this with CPUMInternal.mac !)
61 * @{ */
62/** Used the FPU, SSE or such stuff. */
63#define CPUM_USED_FPU RT_BIT(0)
64/** Used the FPU, SSE or such stuff since last we were in REM.
65 * REM syncing is clearing this, lazy FPU is setting it. */
66#define CPUM_USED_FPU_SINCE_REM RT_BIT(1)
67/** The XMM state was manually restored. (AMD only) */
68#define CPUM_USED_MANUAL_XMM_RESTORE RT_BIT(2)
69
70/** Host OS is using SYSENTER and we must NULL the CS. */
71#define CPUM_USE_SYSENTER RT_BIT(3)
72/** Host OS is using SYSENTER and we must NULL the CS. */
73#define CPUM_USE_SYSCALL RT_BIT(4)
74
75/** Debug registers are used by host and that DR7 and DR6 must be saved and
76 * disabled when switching to raw-mode. */
77#define CPUM_USE_DEBUG_REGS_HOST RT_BIT(5)
78/** Records that we've saved the host DRx registers.
79 * In ring-0 this means all (DR0-7), while in raw-mode context this means DR0-3
80 * since DR6 and DR7 are covered by CPUM_USE_DEBUG_REGS_HOST. */
81#define CPUM_USED_DEBUG_REGS_HOST RT_BIT(6)
82/** Set to indicate that we should save host DR0-7 and load the hypervisor debug
83 * registers in the raw-mode world switchers. (See CPUMRecalcHyperDRx.) */
84#define CPUM_USE_DEBUG_REGS_HYPER RT_BIT(7)
85/** Used in ring-0 to indicate that we have loaded the hypervisor debug
86 * registers. */
87#define CPUM_USED_DEBUG_REGS_HYPER RT_BIT(8)
88/** Used in ring-0 to indicate that we have loaded the guest debug
89 * registers (DR0-3 and maybe DR6) for direct use by the guest.
90 * DR7 (and AMD-V DR6) are handled via the VMCB. */
91#define CPUM_USED_DEBUG_REGS_GUEST RT_BIT(9)
92
93
94/** Sync the FPU state on next entry (32->64 switcher only). */
95#define CPUM_SYNC_FPU_STATE RT_BIT(16)
96/** Sync the debug state on next entry (32->64 switcher only). */
97#define CPUM_SYNC_DEBUG_REGS_GUEST RT_BIT(17)
98/** Sync the debug state on next entry (32->64 switcher only).
99 * Almost the same as CPUM_USE_DEBUG_REGS_HYPER in the raw-mode switchers. */
100#define CPUM_SYNC_DEBUG_REGS_HYPER RT_BIT(18)
101/** Host CPU requires fxsave/fxrstor leaky bit handling. */
102#define CPUM_USE_FFXSR_LEAKY RT_BIT(19)
103/** @} */
104
105/* Sanity check. */
106#ifndef VBOX_FOR_DTRACE_LIB
107#if defined(VBOX_WITH_HYBRID_32BIT_KERNEL) && (HC_ARCH_BITS != 32 || R0_ARCH_BITS != 32)
108# error "VBOX_WITH_HYBRID_32BIT_KERNEL is only for 32 bit builds."
109#endif
110#endif
111
112
113/**
114 * MSR read functions.
115 */
116typedef enum CPUMMSRRDFN
117{
118 /** Invalid zero value. */
119 kCpumMsrRdFn_Invalid = 0,
120 /** Return the CPUMMSRRANGE::uValue. */
121 kCpumMsrRdFn_FixedValue,
122 /** Alias to the MSR range starting at the MSR given by
123 * CPUMMSRRANGE::uValue. Must be used in pair with
124 * kCpumMsrWrFn_MsrAlias. */
125 kCpumMsrRdFn_MsrAlias,
126 /** Write only register, GP all read attempts. */
127 kCpumMsrRdFn_WriteOnly,
128
129 kCpumMsrRdFn_Ia32P5McAddr,
130 kCpumMsrRdFn_Ia32P5McType,
131 kCpumMsrRdFn_Ia32TimestampCounter,
132 kCpumMsrRdFn_Ia32PlatformId, /**< Takes real CPU value for reference. */
133 kCpumMsrRdFn_Ia32ApicBase,
134 kCpumMsrRdFn_Ia32FeatureControl,
135 kCpumMsrRdFn_Ia32BiosSignId, /**< Range value returned. */
136 kCpumMsrRdFn_Ia32SmmMonitorCtl,
137 kCpumMsrRdFn_Ia32PmcN,
138 kCpumMsrRdFn_Ia32MonitorFilterLineSize,
139 kCpumMsrRdFn_Ia32MPerf,
140 kCpumMsrRdFn_Ia32APerf,
141 kCpumMsrRdFn_Ia32MtrrCap, /**< Takes real CPU value for reference. */
142 kCpumMsrRdFn_Ia32MtrrPhysBaseN, /**< Takes register number. */
143 kCpumMsrRdFn_Ia32MtrrPhysMaskN, /**< Takes register number. */
144 kCpumMsrRdFn_Ia32MtrrFixed, /**< Takes CPUMCPU offset. */
145 kCpumMsrRdFn_Ia32MtrrDefType,
146 kCpumMsrRdFn_Ia32Pat,
147 kCpumMsrRdFn_Ia32SysEnterCs,
148 kCpumMsrRdFn_Ia32SysEnterEsp,
149 kCpumMsrRdFn_Ia32SysEnterEip,
150 kCpumMsrRdFn_Ia32McgCap,
151 kCpumMsrRdFn_Ia32McgStatus,
152 kCpumMsrRdFn_Ia32McgCtl,
153 kCpumMsrRdFn_Ia32DebugCtl,
154 kCpumMsrRdFn_Ia32SmrrPhysBase,
155 kCpumMsrRdFn_Ia32SmrrPhysMask,
156 kCpumMsrRdFn_Ia32PlatformDcaCap,
157 kCpumMsrRdFn_Ia32CpuDcaCap,
158 kCpumMsrRdFn_Ia32Dca0Cap,
159 kCpumMsrRdFn_Ia32PerfEvtSelN, /**< Range value indicates the register number. */
160 kCpumMsrRdFn_Ia32PerfStatus, /**< Range value returned. */
161 kCpumMsrRdFn_Ia32PerfCtl, /**< Range value returned. */
162 kCpumMsrRdFn_Ia32FixedCtrN, /**< Takes register number of start of range. */
163 kCpumMsrRdFn_Ia32PerfCapabilities, /**< Takes reference value. */
164 kCpumMsrRdFn_Ia32FixedCtrCtrl,
165 kCpumMsrRdFn_Ia32PerfGlobalStatus, /**< Takes reference value. */
166 kCpumMsrRdFn_Ia32PerfGlobalCtrl,
167 kCpumMsrRdFn_Ia32PerfGlobalOvfCtrl,
168 kCpumMsrRdFn_Ia32PebsEnable,
169 kCpumMsrRdFn_Ia32ClockModulation, /**< Range value returned. */
170 kCpumMsrRdFn_Ia32ThermInterrupt, /**< Range value returned. */
171 kCpumMsrRdFn_Ia32ThermStatus, /**< Range value returned. */
172 kCpumMsrRdFn_Ia32Therm2Ctl, /**< Range value returned. */
173 kCpumMsrRdFn_Ia32MiscEnable, /**< Range value returned. */
174 kCpumMsrRdFn_Ia32McCtlStatusAddrMiscN, /**< Takes bank number. */
175 kCpumMsrRdFn_Ia32McNCtl2, /**< Takes register number of start of range. */
176 kCpumMsrRdFn_Ia32DsArea,
177 kCpumMsrRdFn_Ia32TscDeadline,
178 kCpumMsrRdFn_Ia32X2ApicN,
179 kCpumMsrRdFn_Ia32DebugInterface,
180 kCpumMsrRdFn_Ia32VmxBase, /**< Takes real value as reference. */
181 kCpumMsrRdFn_Ia32VmxPinbasedCtls, /**< Takes real value as reference. */
182 kCpumMsrRdFn_Ia32VmxProcbasedCtls, /**< Takes real value as reference. */
183 kCpumMsrRdFn_Ia32VmxExitCtls, /**< Takes real value as reference. */
184 kCpumMsrRdFn_Ia32VmxEntryCtls, /**< Takes real value as reference. */
185 kCpumMsrRdFn_Ia32VmxMisc, /**< Takes real value as reference. */
186 kCpumMsrRdFn_Ia32VmxCr0Fixed0, /**< Takes real value as reference. */
187 kCpumMsrRdFn_Ia32VmxCr0Fixed1, /**< Takes real value as reference. */
188 kCpumMsrRdFn_Ia32VmxCr4Fixed0, /**< Takes real value as reference. */
189 kCpumMsrRdFn_Ia32VmxCr4Fixed1, /**< Takes real value as reference. */
190 kCpumMsrRdFn_Ia32VmxVmcsEnum, /**< Takes real value as reference. */
191 kCpumMsrRdFn_Ia32VmxProcBasedCtls2, /**< Takes real value as reference. */
192 kCpumMsrRdFn_Ia32VmxEptVpidCap, /**< Takes real value as reference. */
193 kCpumMsrRdFn_Ia32VmxTruePinbasedCtls, /**< Takes real value as reference. */
194 kCpumMsrRdFn_Ia32VmxTrueProcbasedCtls, /**< Takes real value as reference. */
195 kCpumMsrRdFn_Ia32VmxTrueExitCtls, /**< Takes real value as reference. */
196 kCpumMsrRdFn_Ia32VmxTrueEntryCtls, /**< Takes real value as reference. */
197
198 kCpumMsrRdFn_Amd64Efer,
199 kCpumMsrRdFn_Amd64SyscallTarget,
200 kCpumMsrRdFn_Amd64LongSyscallTarget,
201 kCpumMsrRdFn_Amd64CompSyscallTarget,
202 kCpumMsrRdFn_Amd64SyscallFlagMask,
203 kCpumMsrRdFn_Amd64FsBase,
204 kCpumMsrRdFn_Amd64GsBase,
205 kCpumMsrRdFn_Amd64KernelGsBase,
206 kCpumMsrRdFn_Amd64TscAux,
207
208 kCpumMsrRdFn_IntelEblCrPowerOn,
209 kCpumMsrRdFn_IntelI7CoreThreadCount,
210 kCpumMsrRdFn_IntelP4EbcHardPowerOn,
211 kCpumMsrRdFn_IntelP4EbcSoftPowerOn,
212 kCpumMsrRdFn_IntelP4EbcFrequencyId,
213 kCpumMsrRdFn_IntelP6FsbFrequency, /**< Takes real value as reference. */
214 kCpumMsrRdFn_IntelPlatformInfo,
215 kCpumMsrRdFn_IntelFlexRatio, /**< Takes real value as reference. */
216 kCpumMsrRdFn_IntelPkgCStConfigControl,
217 kCpumMsrRdFn_IntelPmgIoCaptureBase,
218 kCpumMsrRdFn_IntelLastBranchFromToN,
219 kCpumMsrRdFn_IntelLastBranchFromN,
220 kCpumMsrRdFn_IntelLastBranchToN,
221 kCpumMsrRdFn_IntelLastBranchTos,
222 kCpumMsrRdFn_IntelBblCrCtl,
223 kCpumMsrRdFn_IntelBblCrCtl3,
224 kCpumMsrRdFn_IntelI7TemperatureTarget, /**< Range value returned. */
225 kCpumMsrRdFn_IntelI7MsrOffCoreResponseN,/**< Takes register number. */
226 kCpumMsrRdFn_IntelI7MiscPwrMgmt,
227 kCpumMsrRdFn_IntelP6CrN,
228 kCpumMsrRdFn_IntelCpuId1FeatureMaskEcdx,
229 kCpumMsrRdFn_IntelCpuId1FeatureMaskEax,
230 kCpumMsrRdFn_IntelCpuId80000001FeatureMaskEcdx,
231 kCpumMsrRdFn_IntelI7SandyAesNiCtl,
232 kCpumMsrRdFn_IntelI7TurboRatioLimit, /**< Returns range value. */
233 kCpumMsrRdFn_IntelI7LbrSelect,
234 kCpumMsrRdFn_IntelI7SandyErrorControl,
235 kCpumMsrRdFn_IntelI7VirtualLegacyWireCap,/**< Returns range value. */
236 kCpumMsrRdFn_IntelI7PowerCtl,
237 kCpumMsrRdFn_IntelI7SandyPebsNumAlt,
238 kCpumMsrRdFn_IntelI7PebsLdLat,
239 kCpumMsrRdFn_IntelI7PkgCnResidencyN, /**< Takes C-state number. */
240 kCpumMsrRdFn_IntelI7CoreCnResidencyN, /**< Takes C-state number. */
241 kCpumMsrRdFn_IntelI7SandyVrCurrentConfig,/**< Takes real value as reference. */
242 kCpumMsrRdFn_IntelI7SandyVrMiscConfig, /**< Takes real value as reference. */
243 kCpumMsrRdFn_IntelI7SandyRaplPowerUnit, /**< Takes real value as reference. */
244 kCpumMsrRdFn_IntelI7SandyPkgCnIrtlN, /**< Takes real value as reference. */
245 kCpumMsrRdFn_IntelI7SandyPkgC2Residency, /**< Takes real value as reference. */
246 kCpumMsrRdFn_IntelI7RaplPkgPowerLimit, /**< Takes real value as reference. */
247 kCpumMsrRdFn_IntelI7RaplPkgEnergyStatus, /**< Takes real value as reference. */
248 kCpumMsrRdFn_IntelI7RaplPkgPerfStatus, /**< Takes real value as reference. */
249 kCpumMsrRdFn_IntelI7RaplPkgPowerInfo, /**< Takes real value as reference. */
250 kCpumMsrRdFn_IntelI7RaplDramPowerLimit, /**< Takes real value as reference. */
251 kCpumMsrRdFn_IntelI7RaplDramEnergyStatus,/**< Takes real value as reference. */
252 kCpumMsrRdFn_IntelI7RaplDramPerfStatus, /**< Takes real value as reference. */
253 kCpumMsrRdFn_IntelI7RaplDramPowerInfo, /**< Takes real value as reference. */
254 kCpumMsrRdFn_IntelI7RaplPp0PowerLimit, /**< Takes real value as reference. */
255 kCpumMsrRdFn_IntelI7RaplPp0EnergyStatus, /**< Takes real value as reference. */
256 kCpumMsrRdFn_IntelI7RaplPp0Policy, /**< Takes real value as reference. */
257 kCpumMsrRdFn_IntelI7RaplPp0PerfStatus, /**< Takes real value as reference. */
258 kCpumMsrRdFn_IntelI7RaplPp1PowerLimit, /**< Takes real value as reference. */
259 kCpumMsrRdFn_IntelI7RaplPp1EnergyStatus, /**< Takes real value as reference. */
260 kCpumMsrRdFn_IntelI7RaplPp1Policy, /**< Takes real value as reference. */
261 kCpumMsrRdFn_IntelI7IvyConfigTdpNominal, /**< Takes real value as reference. */
262 kCpumMsrRdFn_IntelI7IvyConfigTdpLevel1, /**< Takes real value as reference. */
263 kCpumMsrRdFn_IntelI7IvyConfigTdpLevel2, /**< Takes real value as reference. */
264 kCpumMsrRdFn_IntelI7IvyConfigTdpControl,
265 kCpumMsrRdFn_IntelI7IvyTurboActivationRatio,
266 kCpumMsrRdFn_IntelI7UncPerfGlobalCtrl,
267 kCpumMsrRdFn_IntelI7UncPerfGlobalStatus,
268 kCpumMsrRdFn_IntelI7UncPerfGlobalOvfCtrl,
269 kCpumMsrRdFn_IntelI7UncPerfFixedCtrCtrl,
270 kCpumMsrRdFn_IntelI7UncPerfFixedCtr,
271 kCpumMsrRdFn_IntelI7UncCBoxConfig,
272 kCpumMsrRdFn_IntelI7UncArbPerfCtrN,
273 kCpumMsrRdFn_IntelI7UncArbPerfEvtSelN,
274 kCpumMsrRdFn_IntelCore2EmttmCrTablesN, /**< Range value returned. */
275 kCpumMsrRdFn_IntelCore2SmmCStMiscInfo,
276 kCpumMsrRdFn_IntelCore1ExtConfig,
277 kCpumMsrRdFn_IntelCore1DtsCalControl,
278 kCpumMsrRdFn_IntelCore2PeciControl,
279
280 kCpumMsrRdFn_P6LastBranchFromIp,
281 kCpumMsrRdFn_P6LastBranchToIp,
282 kCpumMsrRdFn_P6LastIntFromIp,
283 kCpumMsrRdFn_P6LastIntToIp,
284
285 kCpumMsrRdFn_AmdFam15hTscRate,
286 kCpumMsrRdFn_AmdFam15hLwpCfg,
287 kCpumMsrRdFn_AmdFam15hLwpCbAddr,
288 kCpumMsrRdFn_AmdFam10hMc4MiscN,
289 kCpumMsrRdFn_AmdK8PerfCtlN,
290 kCpumMsrRdFn_AmdK8PerfCtrN,
291 kCpumMsrRdFn_AmdK8SysCfg, /**< Range value returned. */
292 kCpumMsrRdFn_AmdK8HwCr,
293 kCpumMsrRdFn_AmdK8IorrBaseN,
294 kCpumMsrRdFn_AmdK8IorrMaskN,
295 kCpumMsrRdFn_AmdK8TopOfMemN,
296 kCpumMsrRdFn_AmdK8NbCfg1,
297 kCpumMsrRdFn_AmdK8McXcptRedir,
298 kCpumMsrRdFn_AmdK8CpuNameN,
299 kCpumMsrRdFn_AmdK8HwThermalCtrl, /**< Range value returned. */
300 kCpumMsrRdFn_AmdK8SwThermalCtrl,
301 kCpumMsrRdFn_AmdK8FidVidControl, /**< Range value returned. */
302 kCpumMsrRdFn_AmdK8FidVidStatus, /**< Range value returned. */
303 kCpumMsrRdFn_AmdK8McCtlMaskN,
304 kCpumMsrRdFn_AmdK8SmiOnIoTrapN,
305 kCpumMsrRdFn_AmdK8SmiOnIoTrapCtlSts,
306 kCpumMsrRdFn_AmdK8IntPendingMessage,
307 kCpumMsrRdFn_AmdK8SmiTriggerIoCycle,
308 kCpumMsrRdFn_AmdFam10hMmioCfgBaseAddr,
309 kCpumMsrRdFn_AmdFam10hTrapCtlMaybe,
310 kCpumMsrRdFn_AmdFam10hPStateCurLimit, /**< Returns range value. */
311 kCpumMsrRdFn_AmdFam10hPStateControl, /**< Returns range value. */
312 kCpumMsrRdFn_AmdFam10hPStateStatus, /**< Returns range value. */
313 kCpumMsrRdFn_AmdFam10hPStateN, /**< Returns range value. This isn't an register index! */
314 kCpumMsrRdFn_AmdFam10hCofVidControl, /**< Returns range value. */
315 kCpumMsrRdFn_AmdFam10hCofVidStatus, /**< Returns range value. */
316 kCpumMsrRdFn_AmdFam10hCStateIoBaseAddr,
317 kCpumMsrRdFn_AmdFam10hCpuWatchdogTimer,
318 kCpumMsrRdFn_AmdK8SmmBase,
319 kCpumMsrRdFn_AmdK8SmmAddr,
320 kCpumMsrRdFn_AmdK8SmmMask,
321 kCpumMsrRdFn_AmdK8VmCr,
322 kCpumMsrRdFn_AmdK8IgnNe,
323 kCpumMsrRdFn_AmdK8SmmCtl,
324 kCpumMsrRdFn_AmdK8VmHSavePa,
325 kCpumMsrRdFn_AmdFam10hVmLockKey,
326 kCpumMsrRdFn_AmdFam10hSmmLockKey,
327 kCpumMsrRdFn_AmdFam10hLocalSmiStatus,
328 kCpumMsrRdFn_AmdFam10hOsVisWrkIdLength,
329 kCpumMsrRdFn_AmdFam10hOsVisWrkStatus,
330 kCpumMsrRdFn_AmdFam16hL2IPerfCtlN,
331 kCpumMsrRdFn_AmdFam16hL2IPerfCtrN,
332 kCpumMsrRdFn_AmdFam15hNorthbridgePerfCtlN,
333 kCpumMsrRdFn_AmdFam15hNorthbridgePerfCtrN,
334 kCpumMsrRdFn_AmdK7MicrocodeCtl, /**< Returns range value. */
335 kCpumMsrRdFn_AmdK7ClusterIdMaybe, /**< Returns range value. */
336 kCpumMsrRdFn_AmdK8CpuIdCtlStd07hEbax,
337 kCpumMsrRdFn_AmdK8CpuIdCtlStd06hEcx,
338 kCpumMsrRdFn_AmdK8CpuIdCtlStd01hEdcx,
339 kCpumMsrRdFn_AmdK8CpuIdCtlExt01hEdcx,
340 kCpumMsrRdFn_AmdK8PatchLevel, /**< Returns range value. */
341 kCpumMsrRdFn_AmdK7DebugStatusMaybe,
342 kCpumMsrRdFn_AmdK7BHTraceBaseMaybe,
343 kCpumMsrRdFn_AmdK7BHTracePtrMaybe,
344 kCpumMsrRdFn_AmdK7BHTraceLimitMaybe,
345 kCpumMsrRdFn_AmdK7HardwareDebugToolCfgMaybe,
346 kCpumMsrRdFn_AmdK7FastFlushCountMaybe,
347 kCpumMsrRdFn_AmdK7NodeId,
348 kCpumMsrRdFn_AmdK7DrXAddrMaskN, /**< Takes register index. */
349 kCpumMsrRdFn_AmdK7Dr0DataMatchMaybe,
350 kCpumMsrRdFn_AmdK7Dr0DataMaskMaybe,
351 kCpumMsrRdFn_AmdK7LoadStoreCfg,
352 kCpumMsrRdFn_AmdK7InstrCacheCfg,
353 kCpumMsrRdFn_AmdK7DataCacheCfg,
354 kCpumMsrRdFn_AmdK7BusUnitCfg,
355 kCpumMsrRdFn_AmdK7DebugCtl2Maybe,
356 kCpumMsrRdFn_AmdFam15hFpuCfg,
357 kCpumMsrRdFn_AmdFam15hDecoderCfg,
358 kCpumMsrRdFn_AmdFam10hBusUnitCfg2,
359 kCpumMsrRdFn_AmdFam15hCombUnitCfg,
360 kCpumMsrRdFn_AmdFam15hCombUnitCfg2,
361 kCpumMsrRdFn_AmdFam15hCombUnitCfg3,
362 kCpumMsrRdFn_AmdFam15hExecUnitCfg,
363 kCpumMsrRdFn_AmdFam15hLoadStoreCfg2,
364 kCpumMsrRdFn_AmdFam10hIbsFetchCtl,
365 kCpumMsrRdFn_AmdFam10hIbsFetchLinAddr,
366 kCpumMsrRdFn_AmdFam10hIbsFetchPhysAddr,
367 kCpumMsrRdFn_AmdFam10hIbsOpExecCtl,
368 kCpumMsrRdFn_AmdFam10hIbsOpRip,
369 kCpumMsrRdFn_AmdFam10hIbsOpData,
370 kCpumMsrRdFn_AmdFam10hIbsOpData2,
371 kCpumMsrRdFn_AmdFam10hIbsOpData3,
372 kCpumMsrRdFn_AmdFam10hIbsDcLinAddr,
373 kCpumMsrRdFn_AmdFam10hIbsDcPhysAddr,
374 kCpumMsrRdFn_AmdFam10hIbsCtl,
375 kCpumMsrRdFn_AmdFam14hIbsBrTarget,
376
377 /** End of valid MSR read function indexes. */
378 kCpumMsrRdFn_End
379} CPUMMSRRDFN;
380
381/**
382 * MSR write functions.
383 */
384typedef enum CPUMMSRWRFN
385{
386 /** Invalid zero value. */
387 kCpumMsrWrFn_Invalid = 0,
388 /** Writes are ignored, the fWrGpMask is observed though. */
389 kCpumMsrWrFn_IgnoreWrite,
390 /** Writes cause GP(0) to be raised, the fWrGpMask should be UINT64_MAX. */
391 kCpumMsrWrFn_ReadOnly,
392 /** Alias to the MSR range starting at the MSR given by
393 * CPUMMSRRANGE::uValue. Must be used in pair with
394 * kCpumMsrRdFn_MsrAlias. */
395 kCpumMsrWrFn_MsrAlias,
396
397 kCpumMsrWrFn_Ia32P5McAddr,
398 kCpumMsrWrFn_Ia32P5McType,
399 kCpumMsrWrFn_Ia32TimestampCounter,
400 kCpumMsrWrFn_Ia32ApicBase,
401 kCpumMsrWrFn_Ia32FeatureControl,
402 kCpumMsrWrFn_Ia32BiosSignId,
403 kCpumMsrWrFn_Ia32BiosUpdateTrigger,
404 kCpumMsrWrFn_Ia32SmmMonitorCtl,
405 kCpumMsrWrFn_Ia32PmcN,
406 kCpumMsrWrFn_Ia32MonitorFilterLineSize,
407 kCpumMsrWrFn_Ia32MPerf,
408 kCpumMsrWrFn_Ia32APerf,
409 kCpumMsrWrFn_Ia32MtrrPhysBaseN, /**< Takes register number. */
410 kCpumMsrWrFn_Ia32MtrrPhysMaskN, /**< Takes register number. */
411 kCpumMsrWrFn_Ia32MtrrFixed, /**< Takes CPUMCPU offset. */
412 kCpumMsrWrFn_Ia32MtrrDefType,
413 kCpumMsrWrFn_Ia32Pat,
414 kCpumMsrWrFn_Ia32SysEnterCs,
415 kCpumMsrWrFn_Ia32SysEnterEsp,
416 kCpumMsrWrFn_Ia32SysEnterEip,
417 kCpumMsrWrFn_Ia32McgStatus,
418 kCpumMsrWrFn_Ia32McgCtl,
419 kCpumMsrWrFn_Ia32DebugCtl,
420 kCpumMsrWrFn_Ia32SmrrPhysBase,
421 kCpumMsrWrFn_Ia32SmrrPhysMask,
422 kCpumMsrWrFn_Ia32PlatformDcaCap,
423 kCpumMsrWrFn_Ia32Dca0Cap,
424 kCpumMsrWrFn_Ia32PerfEvtSelN, /**< Range value indicates the register number. */
425 kCpumMsrWrFn_Ia32PerfStatus,
426 kCpumMsrWrFn_Ia32PerfCtl,
427 kCpumMsrWrFn_Ia32FixedCtrN, /**< Takes register number of start of range. */
428 kCpumMsrWrFn_Ia32PerfCapabilities,
429 kCpumMsrWrFn_Ia32FixedCtrCtrl,
430 kCpumMsrWrFn_Ia32PerfGlobalStatus,
431 kCpumMsrWrFn_Ia32PerfGlobalCtrl,
432 kCpumMsrWrFn_Ia32PerfGlobalOvfCtrl,
433 kCpumMsrWrFn_Ia32PebsEnable,
434 kCpumMsrWrFn_Ia32ClockModulation,
435 kCpumMsrWrFn_Ia32ThermInterrupt,
436 kCpumMsrWrFn_Ia32ThermStatus,
437 kCpumMsrWrFn_Ia32Therm2Ctl,
438 kCpumMsrWrFn_Ia32MiscEnable,
439 kCpumMsrWrFn_Ia32McCtlStatusAddrMiscN, /**< Takes bank number. */
440 kCpumMsrWrFn_Ia32McNCtl2, /**< Takes register number of start of range. */
441 kCpumMsrWrFn_Ia32DsArea,
442 kCpumMsrWrFn_Ia32TscDeadline,
443 kCpumMsrWrFn_Ia32X2ApicN,
444 kCpumMsrWrFn_Ia32DebugInterface,
445
446 kCpumMsrWrFn_Amd64Efer,
447 kCpumMsrWrFn_Amd64SyscallTarget,
448 kCpumMsrWrFn_Amd64LongSyscallTarget,
449 kCpumMsrWrFn_Amd64CompSyscallTarget,
450 kCpumMsrWrFn_Amd64SyscallFlagMask,
451 kCpumMsrWrFn_Amd64FsBase,
452 kCpumMsrWrFn_Amd64GsBase,
453 kCpumMsrWrFn_Amd64KernelGsBase,
454 kCpumMsrWrFn_Amd64TscAux,
455 kCpumMsrWrFn_IntelEblCrPowerOn,
456 kCpumMsrWrFn_IntelP4EbcHardPowerOn,
457 kCpumMsrWrFn_IntelP4EbcSoftPowerOn,
458 kCpumMsrWrFn_IntelP4EbcFrequencyId,
459 kCpumMsrWrFn_IntelFlexRatio,
460 kCpumMsrWrFn_IntelPkgCStConfigControl,
461 kCpumMsrWrFn_IntelPmgIoCaptureBase,
462 kCpumMsrWrFn_IntelLastBranchFromToN,
463 kCpumMsrWrFn_IntelLastBranchFromN,
464 kCpumMsrWrFn_IntelLastBranchToN,
465 kCpumMsrWrFn_IntelLastBranchTos,
466 kCpumMsrWrFn_IntelBblCrCtl,
467 kCpumMsrWrFn_IntelBblCrCtl3,
468 kCpumMsrWrFn_IntelI7TemperatureTarget,
469 kCpumMsrWrFn_IntelI7MsrOffCoreResponseN, /**< Takes register number. */
470 kCpumMsrWrFn_IntelI7MiscPwrMgmt,
471 kCpumMsrWrFn_IntelP6CrN,
472 kCpumMsrWrFn_IntelCpuId1FeatureMaskEcdx,
473 kCpumMsrWrFn_IntelCpuId1FeatureMaskEax,
474 kCpumMsrWrFn_IntelCpuId80000001FeatureMaskEcdx,
475 kCpumMsrWrFn_IntelI7SandyAesNiCtl,
476 kCpumMsrWrFn_IntelI7TurboRatioLimit,
477 kCpumMsrWrFn_IntelI7LbrSelect,
478 kCpumMsrWrFn_IntelI7SandyErrorControl,
479 kCpumMsrWrFn_IntelI7PowerCtl,
480 kCpumMsrWrFn_IntelI7SandyPebsNumAlt,
481 kCpumMsrWrFn_IntelI7PebsLdLat,
482 kCpumMsrWrFn_IntelI7SandyVrCurrentConfig,
483 kCpumMsrWrFn_IntelI7SandyVrMiscConfig,
484 kCpumMsrWrFn_IntelI7SandyPkgCnIrtlN,
485 kCpumMsrWrFn_IntelI7RaplPkgPowerLimit,
486 kCpumMsrWrFn_IntelI7RaplDramPowerLimit,
487 kCpumMsrWrFn_IntelI7RaplPp0PowerLimit,
488 kCpumMsrWrFn_IntelI7RaplPp0Policy,
489 kCpumMsrWrFn_IntelI7RaplPp1PowerLimit,
490 kCpumMsrWrFn_IntelI7RaplPp1Policy,
491 kCpumMsrWrFn_IntelI7IvyConfigTdpControl,
492 kCpumMsrWrFn_IntelI7IvyTurboActivationRatio,
493 kCpumMsrWrFn_IntelI7UncPerfGlobalCtrl,
494 kCpumMsrWrFn_IntelI7UncPerfGlobalStatus,
495 kCpumMsrWrFn_IntelI7UncPerfGlobalOvfCtrl,
496 kCpumMsrWrFn_IntelI7UncPerfFixedCtrCtrl,
497 kCpumMsrWrFn_IntelI7UncPerfFixedCtr,
498 kCpumMsrWrFn_IntelI7UncArbPerfCtrN,
499 kCpumMsrWrFn_IntelI7UncArbPerfEvtSelN,
500 kCpumMsrWrFn_IntelCore2EmttmCrTablesN,
501 kCpumMsrWrFn_IntelCore2SmmCStMiscInfo,
502 kCpumMsrWrFn_IntelCore1ExtConfig,
503 kCpumMsrWrFn_IntelCore1DtsCalControl,
504 kCpumMsrWrFn_IntelCore2PeciControl,
505
506 kCpumMsrWrFn_P6LastIntFromIp,
507 kCpumMsrWrFn_P6LastIntToIp,
508
509 kCpumMsrWrFn_AmdFam15hTscRate,
510 kCpumMsrWrFn_AmdFam15hLwpCfg,
511 kCpumMsrWrFn_AmdFam15hLwpCbAddr,
512 kCpumMsrWrFn_AmdFam10hMc4MiscN,
513 kCpumMsrWrFn_AmdK8PerfCtlN,
514 kCpumMsrWrFn_AmdK8PerfCtrN,
515 kCpumMsrWrFn_AmdK8SysCfg,
516 kCpumMsrWrFn_AmdK8HwCr,
517 kCpumMsrWrFn_AmdK8IorrBaseN,
518 kCpumMsrWrFn_AmdK8IorrMaskN,
519 kCpumMsrWrFn_AmdK8TopOfMemN,
520 kCpumMsrWrFn_AmdK8NbCfg1,
521 kCpumMsrWrFn_AmdK8McXcptRedir,
522 kCpumMsrWrFn_AmdK8CpuNameN,
523 kCpumMsrWrFn_AmdK8HwThermalCtrl,
524 kCpumMsrWrFn_AmdK8SwThermalCtrl,
525 kCpumMsrWrFn_AmdK8FidVidControl,
526 kCpumMsrWrFn_AmdK8McCtlMaskN,
527 kCpumMsrWrFn_AmdK8SmiOnIoTrapN,
528 kCpumMsrWrFn_AmdK8SmiOnIoTrapCtlSts,
529 kCpumMsrWrFn_AmdK8IntPendingMessage,
530 kCpumMsrWrFn_AmdK8SmiTriggerIoCycle,
531 kCpumMsrWrFn_AmdFam10hMmioCfgBaseAddr,
532 kCpumMsrWrFn_AmdFam10hTrapCtlMaybe,
533 kCpumMsrWrFn_AmdFam10hPStateControl,
534 kCpumMsrWrFn_AmdFam10hPStateStatus,
535 kCpumMsrWrFn_AmdFam10hPStateN,
536 kCpumMsrWrFn_AmdFam10hCofVidControl,
537 kCpumMsrWrFn_AmdFam10hCofVidStatus,
538 kCpumMsrWrFn_AmdFam10hCStateIoBaseAddr,
539 kCpumMsrWrFn_AmdFam10hCpuWatchdogTimer,
540 kCpumMsrWrFn_AmdK8SmmBase,
541 kCpumMsrWrFn_AmdK8SmmAddr,
542 kCpumMsrWrFn_AmdK8SmmMask,
543 kCpumMsrWrFn_AmdK8VmCr,
544 kCpumMsrWrFn_AmdK8IgnNe,
545 kCpumMsrWrFn_AmdK8SmmCtl,
546 kCpumMsrWrFn_AmdK8VmHSavePa,
547 kCpumMsrWrFn_AmdFam10hVmLockKey,
548 kCpumMsrWrFn_AmdFam10hSmmLockKey,
549 kCpumMsrWrFn_AmdFam10hLocalSmiStatus,
550 kCpumMsrWrFn_AmdFam10hOsVisWrkIdLength,
551 kCpumMsrWrFn_AmdFam10hOsVisWrkStatus,
552 kCpumMsrWrFn_AmdFam16hL2IPerfCtlN,
553 kCpumMsrWrFn_AmdFam16hL2IPerfCtrN,
554 kCpumMsrWrFn_AmdFam15hNorthbridgePerfCtlN,
555 kCpumMsrWrFn_AmdFam15hNorthbridgePerfCtrN,
556 kCpumMsrWrFn_AmdK7MicrocodeCtl,
557 kCpumMsrWrFn_AmdK7ClusterIdMaybe,
558 kCpumMsrWrFn_AmdK8CpuIdCtlStd07hEbax,
559 kCpumMsrWrFn_AmdK8CpuIdCtlStd06hEcx,
560 kCpumMsrWrFn_AmdK8CpuIdCtlStd01hEdcx,
561 kCpumMsrWrFn_AmdK8CpuIdCtlExt01hEdcx,
562 kCpumMsrWrFn_AmdK8PatchLoader,
563 kCpumMsrWrFn_AmdK7DebugStatusMaybe,
564 kCpumMsrWrFn_AmdK7BHTraceBaseMaybe,
565 kCpumMsrWrFn_AmdK7BHTracePtrMaybe,
566 kCpumMsrWrFn_AmdK7BHTraceLimitMaybe,
567 kCpumMsrWrFn_AmdK7HardwareDebugToolCfgMaybe,
568 kCpumMsrWrFn_AmdK7FastFlushCountMaybe,
569 kCpumMsrWrFn_AmdK7NodeId,
570 kCpumMsrWrFn_AmdK7DrXAddrMaskN, /**< Takes register index. */
571 kCpumMsrWrFn_AmdK7Dr0DataMatchMaybe,
572 kCpumMsrWrFn_AmdK7Dr0DataMaskMaybe,
573 kCpumMsrWrFn_AmdK7LoadStoreCfg,
574 kCpumMsrWrFn_AmdK7InstrCacheCfg,
575 kCpumMsrWrFn_AmdK7DataCacheCfg,
576 kCpumMsrWrFn_AmdK7BusUnitCfg,
577 kCpumMsrWrFn_AmdK7DebugCtl2Maybe,
578 kCpumMsrWrFn_AmdFam15hFpuCfg,
579 kCpumMsrWrFn_AmdFam15hDecoderCfg,
580 kCpumMsrWrFn_AmdFam10hBusUnitCfg2,
581 kCpumMsrWrFn_AmdFam15hCombUnitCfg,
582 kCpumMsrWrFn_AmdFam15hCombUnitCfg2,
583 kCpumMsrWrFn_AmdFam15hCombUnitCfg3,
584 kCpumMsrWrFn_AmdFam15hExecUnitCfg,
585 kCpumMsrWrFn_AmdFam15hLoadStoreCfg2,
586 kCpumMsrWrFn_AmdFam10hIbsFetchCtl,
587 kCpumMsrWrFn_AmdFam10hIbsFetchLinAddr,
588 kCpumMsrWrFn_AmdFam10hIbsFetchPhysAddr,
589 kCpumMsrWrFn_AmdFam10hIbsOpExecCtl,
590 kCpumMsrWrFn_AmdFam10hIbsOpRip,
591 kCpumMsrWrFn_AmdFam10hIbsOpData,
592 kCpumMsrWrFn_AmdFam10hIbsOpData2,
593 kCpumMsrWrFn_AmdFam10hIbsOpData3,
594 kCpumMsrWrFn_AmdFam10hIbsDcLinAddr,
595 kCpumMsrWrFn_AmdFam10hIbsDcPhysAddr,
596 kCpumMsrWrFn_AmdFam10hIbsCtl,
597 kCpumMsrWrFn_AmdFam14hIbsBrTarget,
598
599 /** End of valid MSR write function indexes. */
600 kCpumMsrWrFn_End
601} CPUMMSRWRFN;
602
603/**
604 * MSR range.
605 */
606typedef struct CPUMMSRRANGE
607{
608 /** The first MSR. [0] */
609 uint32_t uFirst;
610 /** The last MSR. [4] */
611 uint32_t uLast;
612 /** The read function (CPUMMSRRDFN). [8] */
613 uint16_t enmRdFn;
614 /** The write function (CPUMMSRWRFN). [10] */
615 uint16_t enmWrFn;
616 /** The offset of the 64-bit MSR value relative to the start of CPUMCPU.
617 * UINT16_MAX if not used by the read and write functions. [12] */
618 uint16_t offCpumCpu;
619 /** Reserved for future hacks. [14] */
620 uint16_t fReserved;
621 /** The init/read value. [16]
622 * When enmRdFn is kCpumMsrRdFn_INIT_VALUE, this is the value returned on RDMSR.
623 * offCpumCpu must be UINT16_MAX in that case, otherwise it must be a valid
624 * offset into CPUM. */
625 uint64_t uValue;
626 /** The bits to ignore when writing. [24] */
627 uint64_t fWrIgnMask;
628 /** The bits that will cause a GP(0) when writing. [32]
629 * This is always checked prior to calling the write function. Using
630 * UINT64_MAX effectively marks the MSR as read-only. */
631 uint64_t fWrGpMask;
632 /** The register name, if applicable. [40] */
633 char szName[56];
634
635#ifdef VBOX_WITH_STATISTICS
636 /** The number of reads. */
637 STAMCOUNTER cReads;
638 /** The number of writes. */
639 STAMCOUNTER cWrites;
640 /** The number of times ignored bits were written. */
641 STAMCOUNTER cIgnoredBits;
642 /** The number of GPs generated. */
643 STAMCOUNTER cGps;
644#endif
645} CPUMMSRRANGE;
646#ifdef VBOX_WITH_STATISTICS
647AssertCompileSize(CPUMMSRRANGE, 128);
648#else
649AssertCompileSize(CPUMMSRRANGE, 96);
650#endif
651/** Pointer to an MSR range. */
652typedef CPUMMSRRANGE *PCPUMMSRRANGE;
653/** Pointer to a const MSR range. */
654typedef CPUMMSRRANGE const *PCCPUMMSRRANGE;
655
656
657
658
659/**
660 * CPU features and quirks.
661 * This is mostly exploded CPUID info.
662 */
663typedef struct CPUMFEATURES
664{
665 /** The CPU vendor (CPUMCPUVENDOR). */
666 uint8_t enmCpuVendor;
667 /** The CPU family. */
668 uint8_t uFamily;
669 /** The CPU model. */
670 uint8_t uModel;
671 /** The CPU stepping. */
672 uint8_t uStepping;
673 /** The microarchitecture. */
674 CPUMMICROARCH enmMicroarch;
675 /** The maximum physical address with of the CPU. */
676 uint8_t cMaxPhysAddrWidth;
677 /** Alignment padding. */
678 uint8_t abPadding[3];
679
680 /** Supports MSRs. */
681 uint32_t fMsr : 1;
682 /** Supports the page size extension (4/2 MB pages). */
683 uint32_t fPse : 1;
684 /** Supports 36-bit page size extension (4 MB pages can map memory above
685 * 4GB). */
686 uint32_t fPse36 : 1;
687 /** Supports physical address extension (PAE). */
688 uint32_t fPae : 1;
689 /** Page attribute table (PAT) support (page level cache control). */
690 uint32_t fPat : 1;
691 /** Supports the FXSAVE and FXRSTOR instructions. */
692 uint32_t fFxSaveRstor : 1;
693 /** Intel SYSENTER/SYSEXIT support */
694 uint32_t fSysEnter : 1;
695 /** First generation APIC. */
696 uint32_t fApic : 1;
697 /** Second generation APIC. */
698 uint32_t fX2Apic : 1;
699 /** Hypervisor present. */
700 uint32_t fHypervisorPresent : 1;
701 /** MWAIT & MONITOR instructions supported. */
702 uint32_t fMonitorMWait : 1;
703
704 /** AMD64: Supports long mode. */
705 uint32_t fLongMode : 1;
706 /** AMD64: SYSCALL/SYSRET support. */
707 uint32_t fSysCall : 1;
708 /** AMD64: No-execute page table bit. */
709 uint32_t fNoExecute : 1;
710 /** AMD64: Supports LAHF & SAHF instructions in 64-bit mode. */
711 uint32_t fLahfSahf : 1;
712 /** AMD64: Supports RDTSCP. */
713 uint32_t fRdTscP : 1;
714
715 /** Indicates that FPU instruction and data pointers may leak.
716 * This generally applies to recent AMD CPUs, where the FPU IP and DP pointer
717 * is only saved and restored if an exception is pending. */
718 uint32_t fLeakyFxSR : 1;
719
720 /** Alignment padding. */
721 uint32_t fPadding : 9;
722
723 uint64_t auPadding[2];
724} CPUMFEATURES;
725AssertCompileSize(CPUMFEATURES, 32);
726/** Pointer to a CPU feature structure. */
727typedef CPUMFEATURES *PCPUMFEATURES;
728/** Pointer to a const CPU feature structure. */
729typedef CPUMFEATURES const *PCCPUMFEATURES;
730
731
732/**
733 * CPU info
734 */
735typedef struct CPUMINFO
736{
737 /** The number of MSR ranges (CPUMMSRRANGE) in the array pointed to below. */
738 uint32_t cMsrRanges;
739 /** Mask applied to ECX before looking up the MSR for a RDMSR/WRMSR
740 * instruction. Older hardware has been observed to ignore higher bits. */
741 uint32_t fMsrMask;
742
743 /** The number of CPUID leaves (CPUMCPUIDLEAF) in the array pointed to below. */
744 uint32_t cCpuIdLeaves;
745 /** The index of the first extended CPUID leaf in the array.
746 * Set to cCpuIdLeaves if none present. */
747 uint32_t iFirstExtCpuIdLeaf;
748 /** Alignment padding. */
749 uint32_t uPadding;
750 /** How to handle unknown CPUID leaves. */
751 CPUMUKNOWNCPUID enmUnknownCpuIdMethod;
752 /** For use with CPUMUKNOWNCPUID_DEFAULTS. */
753 CPUMCPUID DefCpuId;
754
755 /** Scalable bus frequency used for reporting other frequencies. */
756 uint64_t uScalableBusFreq;
757
758 /** Pointer to the MSR ranges (ring-0 pointer). */
759 R0PTRTYPE(PCPUMMSRRANGE) paMsrRangesR0;
760 /** Pointer to the CPUID leaves (ring-0 pointer). */
761 R0PTRTYPE(PCPUMCPUIDLEAF) paCpuIdLeavesR0;
762
763 /** Pointer to the MSR ranges (ring-3 pointer). */
764 R3PTRTYPE(PCPUMMSRRANGE) paMsrRangesR3;
765 /** Pointer to the CPUID leaves (ring-3 pointer). */
766 R3PTRTYPE(PCPUMCPUIDLEAF) paCpuIdLeavesR3;
767
768 /** Pointer to the MSR ranges (raw-mode context pointer). */
769 RCPTRTYPE(PCPUMMSRRANGE) paMsrRangesRC;
770 /** Pointer to the CPUID leaves (raw-mode context pointer). */
771 RCPTRTYPE(PCPUMCPUIDLEAF) paCpuIdLeavesRC;
772} CPUMINFO;
773/** Pointer to a CPU info structure. */
774typedef CPUMINFO *PCPUMINFO;
775/** Pointer to a const CPU info structure. */
776typedef CPUMINFO const *CPCPUMINFO;
777
778
779/**
780 * The saved host CPU state.
781 *
782 * @remark The special VBOX_WITH_HYBRID_32BIT_KERNEL checks here are for the 10.4.x series
783 * of Mac OS X where the OS is essentially 32-bit but the cpu mode can be 64-bit.
784 */
785typedef struct CPUMHOSTCTX
786{
787 /** FPU state. (16-byte alignment)
788 * @remark On x86, the format isn't necessarily X86FXSTATE (not important). */
789 X86FXSTATE fpu;
790
791 /** General purpose register, selectors, flags and more
792 * @{ */
793#if HC_ARCH_BITS == 64 || defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
794 /** General purpose register ++
795 * { */
796 /*uint64_t rax; - scratch*/
797 uint64_t rbx;
798 /*uint64_t rcx; - scratch*/
799 /*uint64_t rdx; - scratch*/
800 uint64_t rdi;
801 uint64_t rsi;
802 uint64_t rbp;
803 uint64_t rsp;
804 /*uint64_t r8; - scratch*/
805 /*uint64_t r9; - scratch*/
806 uint64_t r10;
807 uint64_t r11;
808 uint64_t r12;
809 uint64_t r13;
810 uint64_t r14;
811 uint64_t r15;
812 /*uint64_t rip; - scratch*/
813 uint64_t rflags;
814#endif
815
816#if HC_ARCH_BITS == 32
817 /*uint32_t eax; - scratch*/
818 uint32_t ebx;
819 /*uint32_t ecx; - scratch*/
820 /*uint32_t edx; - scratch*/
821 uint32_t edi;
822 uint32_t esi;
823 uint32_t ebp;
824 X86EFLAGS eflags;
825 /*uint32_t eip; - scratch*/
826 /* lss pair! */
827 uint32_t esp;
828#endif
829 /** @} */
830
831 /** Selector registers
832 * @{ */
833 RTSEL ss;
834 RTSEL ssPadding;
835 RTSEL gs;
836 RTSEL gsPadding;
837 RTSEL fs;
838 RTSEL fsPadding;
839 RTSEL es;
840 RTSEL esPadding;
841 RTSEL ds;
842 RTSEL dsPadding;
843 RTSEL cs;
844 RTSEL csPadding;
845 /** @} */
846
847#if HC_ARCH_BITS == 32 && !defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
848 /** Control registers.
849 * @{ */
850 uint32_t cr0;
851 /*uint32_t cr2; - scratch*/
852 uint32_t cr3;
853 uint32_t cr4;
854 /** @} */
855
856 /** Debug registers.
857 * @{ */
858 uint32_t dr0;
859 uint32_t dr1;
860 uint32_t dr2;
861 uint32_t dr3;
862 uint32_t dr6;
863 uint32_t dr7;
864 /** @} */
865
866 /** Global Descriptor Table register. */
867 X86XDTR32 gdtr;
868 uint16_t gdtrPadding;
869 /** Interrupt Descriptor Table register. */
870 X86XDTR32 idtr;
871 uint16_t idtrPadding;
872 /** The task register. */
873 RTSEL ldtr;
874 RTSEL ldtrPadding;
875 /** The task register. */
876 RTSEL tr;
877 RTSEL trPadding;
878 uint32_t SysEnterPadding;
879
880 /** The sysenter msr registers.
881 * This member is not used by the hypervisor context. */
882 CPUMSYSENTER SysEnter;
883
884 /** MSRs
885 * @{ */
886 uint64_t efer;
887 /** @} */
888
889 /* padding to get 64byte aligned size */
890 uint8_t auPadding[16+32];
891
892#elif HC_ARCH_BITS == 64 || defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
893
894 /** Control registers.
895 * @{ */
896 uint64_t cr0;
897 /*uint64_t cr2; - scratch*/
898 uint64_t cr3;
899 uint64_t cr4;
900 uint64_t cr8;
901 /** @} */
902
903 /** Debug registers.
904 * @{ */
905 uint64_t dr0;
906 uint64_t dr1;
907 uint64_t dr2;
908 uint64_t dr3;
909 uint64_t dr6;
910 uint64_t dr7;
911 /** @} */
912
913 /** Global Descriptor Table register. */
914 X86XDTR64 gdtr;
915 uint16_t gdtrPadding;
916 /** Interrupt Descriptor Table register. */
917 X86XDTR64 idtr;
918 uint16_t idtrPadding;
919 /** The task register. */
920 RTSEL ldtr;
921 RTSEL ldtrPadding;
922 /** The task register. */
923 RTSEL tr;
924 RTSEL trPadding;
925
926 /** MSRs
927 * @{ */
928 CPUMSYSENTER SysEnter;
929 uint64_t FSbase;
930 uint64_t GSbase;
931 uint64_t efer;
932 /** @} */
933
934 /* padding to get 32byte aligned size */
935# ifdef VBOX_WITH_HYBRID_32BIT_KERNEL
936 uint8_t auPadding[16];
937# else
938 uint8_t auPadding[8+32];
939# endif
940
941#else
942# error HC_ARCH_BITS not defined
943#endif
944} CPUMHOSTCTX;
945/** Pointer to the saved host CPU state. */
946typedef CPUMHOSTCTX *PCPUMHOSTCTX;
947
948
949/**
950 * CPUM Data (part of VM)
951 */
952typedef struct CPUM
953{
954 /** Offset from CPUM to CPUMCPU for the first CPU. */
955 uint32_t offCPUMCPU0;
956
957 /** Use flags.
958 * These flags indicates which CPU features the host uses.
959 */
960 uint32_t fHostUseFlags;
961
962 /** Host CPU Features - ECX */
963 struct
964 {
965 /** edx part */
966 X86CPUIDFEATEDX edx;
967 /** ecx part */
968 X86CPUIDFEATECX ecx;
969 } CPUFeatures;
970 /** Host extended CPU features. */
971 struct
972 {
973 /** edx part */
974 uint32_t edx;
975 /** ecx part */
976 uint32_t ecx;
977 } CPUFeaturesExt;
978
979 /** CR4 mask */
980 struct
981 {
982 uint32_t AndMask; /**< @todo Move these to the per-CPU structure and fix the switchers. Saves a register! */
983 uint32_t OrMask;
984 } CR4;
985
986 /** The (more) portable CPUID level. */
987 uint8_t u8PortableCpuIdLevel;
988 /** Indicates that a state restore is pending.
989 * This is used to verify load order dependencies (PGM). */
990 bool fPendingRestore;
991 uint8_t abPadding[HC_ARCH_BITS == 64 ? 6 : 2];
992
993 /** The standard set of CpuId leaves. */
994 CPUMCPUID aGuestCpuIdStd[6];
995 /** The extended set of CpuId leaves. */
996 CPUMCPUID aGuestCpuIdExt[10];
997 /** The centaur set of CpuId leaves. */
998 CPUMCPUID aGuestCpuIdCentaur[4];
999 /** The hypervisor specific set of CpuId leaves. */
1000 CPUMCPUID aGuestCpuIdHyper[4];
1001 /** The default set of CpuId leaves. */
1002 CPUMCPUID GuestCpuIdDef;
1003
1004#if HC_ARCH_BITS == 32
1005 uint8_t abPadding2[4];
1006#endif
1007
1008 /** Guest CPU info. */
1009 CPUMINFO GuestInfo;
1010 /** Guest CPU feature information. */
1011 CPUMFEATURES GuestFeatures;
1012 /** Host CPU feature information. */
1013 CPUMFEATURES HostFeatures;
1014
1015 /** @name MSR statistics.
1016 * @{ */
1017 STAMCOUNTER cMsrWrites;
1018 STAMCOUNTER cMsrWritesToIgnoredBits;
1019 STAMCOUNTER cMsrWritesRaiseGp;
1020 STAMCOUNTER cMsrWritesUnknown;
1021 STAMCOUNTER cMsrReads;
1022 STAMCOUNTER cMsrReadsRaiseGp;
1023 STAMCOUNTER cMsrReadsUnknown;
1024 /** @} */
1025} CPUM;
1026/** Pointer to the CPUM instance data residing in the shared VM structure. */
1027typedef CPUM *PCPUM;
1028
1029/**
1030 * CPUM Data (part of VMCPU)
1031 */
1032typedef struct CPUMCPU
1033{
1034 /**
1035 * Hypervisor context.
1036 * Aligned on a 64-byte boundary.
1037 */
1038 CPUMCTX Hyper;
1039
1040 /**
1041 * Saved host context. Only valid while inside GC.
1042 * Aligned on a 64-byte boundary.
1043 */
1044 CPUMHOSTCTX Host;
1045
1046#ifdef VBOX_WITH_CRASHDUMP_MAGIC
1047 uint8_t aMagic[56];
1048 uint64_t uMagic;
1049#endif
1050
1051 /**
1052 * Guest context.
1053 * Aligned on a 64-byte boundary.
1054 */
1055 CPUMCTX Guest;
1056
1057 /**
1058 * Guest context - misc MSRs
1059 * Aligned on a 64-byte boundary.
1060 */
1061 CPUMCTXMSRS GuestMsrs;
1062
1063 /** Use flags.
1064 * These flags indicates both what is to be used and what has been used.
1065 */
1066 uint32_t fUseFlags;
1067
1068 /** Changed flags.
1069 * These flags indicates to REM (and others) which important guest
1070 * registers which has been changed since last time the flags were cleared.
1071 * See the CPUM_CHANGED_* defines for what we keep track of.
1072 */
1073 uint32_t fChanged;
1074
1075 /** Offset from CPUM to CPUMCPU. */
1076 uint32_t offCPUM;
1077
1078 /** Temporary storage for the return code of the function called in the
1079 * 32-64 switcher. */
1080 uint32_t u32RetCode;
1081
1082#ifdef VBOX_WITH_VMMR0_DISABLE_LAPIC_NMI
1083 /** The address of the APIC mapping, NULL if no APIC.
1084 * Call CPUMR0SetLApic to update this before doing a world switch. */
1085 RTHCPTR pvApicBase;
1086 /** Used by the world switcher code to store which vectors needs restoring on
1087 * the way back. */
1088 uint32_t fApicDisVectors;
1089 /** Set if the CPU has the X2APIC mode enabled.
1090 * Call CPUMR0SetLApic to update this before doing a world switch. */
1091 bool fX2Apic;
1092#else
1093 uint8_t abPadding3[(HC_ARCH_BITS == 64 ? 8 : 4) + 4 + 1];
1094#endif
1095
1096 /** Have we entered raw-mode? */
1097 bool fRawEntered;
1098 /** Have we entered the recompiler? */
1099 bool fRemEntered;
1100
1101 /** Align the structure on a 64-byte boundary. */
1102 uint8_t abPadding2[64 - 16 - (HC_ARCH_BITS == 64 ? 8 : 4) - 4 - 1 - 2];
1103} CPUMCPU;
1104/** Pointer to the CPUMCPU instance data residing in the shared VMCPU structure. */
1105typedef CPUMCPU *PCPUMCPU;
1106
1107#ifndef VBOX_FOR_DTRACE_LIB
1108RT_C_DECLS_BEGIN
1109
1110PCPUMCPUIDLEAF cpumCpuIdGetLeaf(PVM pVM, uint32_t uLeaf, uint32_t uSubLeaf);
1111
1112#ifdef IN_RING3
1113int cpumR3DbgInit(PVM pVM);
1114PCPUMCPUIDLEAF cpumR3CpuIdGetLeaf(PCPUMCPUIDLEAF paLeaves, uint32_t cLeaves, uint32_t uLeaf, uint32_t uSubLeaf);
1115bool cpumR3CpuIdGetLeafLegacy(PCPUMCPUIDLEAF paLeaves, uint32_t cLeaves, uint32_t uLeaf, uint32_t uSubLeaf,
1116 PCPUMCPUID pLeagcy);
1117int cpumR3CpuIdInsert(PCPUMCPUIDLEAF *ppaLeaves, uint32_t *pcLeaves, PCPUMCPUIDLEAF pNewLeaf);
1118void cpumR3CpuIdRemoveRange(PCPUMCPUIDLEAF paLeaves, uint32_t *pcLeaves, uint32_t uFirst, uint32_t uLast);
1119int cpumR3CpuIdExplodeFeatures(PCCPUMCPUIDLEAF paLeaves, uint32_t cLeaves, PCPUMFEATURES pFeatures);
1120int cpumR3DbGetCpuInfo(const char *pszName, PCPUMINFO pInfo);
1121int cpumR3MsrRangesInsert(PCPUMMSRRANGE *ppaMsrRanges, uint32_t *pcMsrRanges, PCCPUMMSRRANGE pNewRange);
1122int cpumR3MsrApplyFudge(PVM pVM);
1123int cpumR3MsrRegStats(PVM pVM);
1124int cpumR3MsrStrictInitChecks(void);
1125PCPUMMSRRANGE cpumLookupMsrRange(PVM pVM, uint32_t idMsr);
1126#endif
1127
1128#ifdef IN_RC
1129DECLASM(int) cpumHandleLazyFPUAsm(PCPUMCPU pCPUM);
1130#endif
1131
1132#ifdef IN_RING0
1133DECLASM(int) cpumR0SaveHostRestoreGuestFPUState(PCPUMCPU pCPUM);
1134DECLASM(int) cpumR0SaveGuestRestoreHostFPUState(PCPUMCPU pCPUM);
1135DECLASM(int) cpumR0SaveHostFPUState(PCPUMCPU pCPUM);
1136DECLASM(int) cpumR0RestoreHostFPUState(PCPUMCPU pCPUM);
1137DECLASM(void) cpumR0LoadFPU(PCPUMCTX pCtx);
1138DECLASM(void) cpumR0SaveFPU(PCPUMCTX pCtx);
1139DECLASM(void) cpumR0LoadXMM(PCPUMCTX pCtx);
1140DECLASM(void) cpumR0SaveXMM(PCPUMCTX pCtx);
1141DECLASM(void) cpumR0SetFCW(uint16_t u16FCW);
1142DECLASM(uint16_t) cpumR0GetFCW(void);
1143DECLASM(void) cpumR0SetMXCSR(uint32_t u32MXCSR);
1144DECLASM(uint32_t) cpumR0GetMXCSR(void);
1145DECLASM(void) cpumR0LoadDRx(uint64_t const *pa4Regs);
1146DECLASM(void) cpumR0SaveDRx(uint64_t *pa4Regs);
1147#endif
1148
1149RT_C_DECLS_END
1150#endif /* !VBOX_FOR_DTRACE_LIB */
1151
1152/** @} */
1153
1154#endif
1155
Note: See TracBrowser for help on using the repository browser.

© 2024 Oracle Support Privacy / Do Not Sell My Info Terms of Use Trademark Policy Automated Access Etiquette