CPUMInternal.h@ 51285

Last change on this file since 51285 was 51285, checked in by vboxsync, 11 years ago
VMM: Expose the MSR read/write function index enums.
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1	/* $Id: CPUMInternal.h 51285 2014-05-19 11:00:11Z vboxsync $ */
2	/** @file
3	* CPUM - Internal header file.
4	*/
5
6	/*
7	* Copyright (C) 2006-2012 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*/
17
18	#ifndef ___CPUMInternal_h
19	#define ___CPUMInternal_h
20
21	#ifndef VBOX_FOR_DTRACE_LIB
22	# include <VBox/cdefs.h>
23	# include <VBox/types.h>
24	# include <VBox/vmm/stam.h>
25	# include <iprt/x86.h>
26	#else
27	# pragma D depends_on library x86.d
28	# pragma D depends_on library cpumctx.d
29	#endif
30
31
32
33
34	/** @defgroup grp_cpum_int Internals
35	* @ingroup grp_cpum
36	* @internal
37	* @{
38	*/
39
40	/** Flags and types for CPUM fault handlers
41	* @{ */
42	/** Type: Load DS */
43	#define CPUM_HANDLER_DS 1
44	/** Type: Load ES */
45	#define CPUM_HANDLER_ES 2
46	/** Type: Load FS */
47	#define CPUM_HANDLER_FS 3
48	/** Type: Load GS */
49	#define CPUM_HANDLER_GS 4
50	/** Type: IRET */
51	#define CPUM_HANDLER_IRET 5
52	/** Type mask. */
53	#define CPUM_HANDLER_TYPEMASK 0xff
54	/** If set EBP points to the CPUMCTXCORE that's being used. */
55	#define CPUM_HANDLER_CTXCORE_IN_EBP RT_BIT(31)
56	/** @} */
57
58
59	/** Use flags (CPUM::fUseFlags).
60	* (Don't forget to sync this with CPUMInternal.mac !)
61	* @{ */
62	/** Used the FPU, SSE or such stuff. */
63	#define CPUM_USED_FPU RT_BIT(0)
64	/** Used the FPU, SSE or such stuff since last we were in REM.
65	* REM syncing is clearing this, lazy FPU is setting it. */
66	#define CPUM_USED_FPU_SINCE_REM RT_BIT(1)
67	/** The XMM state was manually restored. (AMD only) */
68	#define CPUM_USED_MANUAL_XMM_RESTORE RT_BIT(2)
69
70	/** Host OS is using SYSENTER and we must NULL the CS. */
71	#define CPUM_USE_SYSENTER RT_BIT(3)
72	/** Host OS is using SYSENTER and we must NULL the CS. */
73	#define CPUM_USE_SYSCALL RT_BIT(4)
74
75	/** Debug registers are used by host and that DR7 and DR6 must be saved and
76	* disabled when switching to raw-mode. */
77	#define CPUM_USE_DEBUG_REGS_HOST RT_BIT(5)
78	/** Records that we've saved the host DRx registers.
79	* In ring-0 this means all (DR0-7), while in raw-mode context this means DR0-3
80	* since DR6 and DR7 are covered by CPUM_USE_DEBUG_REGS_HOST. */
81	#define CPUM_USED_DEBUG_REGS_HOST RT_BIT(6)
82	/** Set to indicate that we should save host DR0-7 and load the hypervisor debug
83	* registers in the raw-mode world switchers. (See CPUMRecalcHyperDRx.) */
84	#define CPUM_USE_DEBUG_REGS_HYPER RT_BIT(7)
85	/** Used in ring-0 to indicate that we have loaded the hypervisor debug
86	* registers. */
87	#define CPUM_USED_DEBUG_REGS_HYPER RT_BIT(8)
88	/** Used in ring-0 to indicate that we have loaded the guest debug
89	* registers (DR0-3 and maybe DR6) for direct use by the guest.
90	* DR7 (and AMD-V DR6) are handled via the VMCB. */
91	#define CPUM_USED_DEBUG_REGS_GUEST RT_BIT(9)
92
93
94	/** Sync the FPU state on next entry (32->64 switcher only). */
95	#define CPUM_SYNC_FPU_STATE RT_BIT(16)
96	/** Sync the debug state on next entry (32->64 switcher only). */
97	#define CPUM_SYNC_DEBUG_REGS_GUEST RT_BIT(17)
98	/** Sync the debug state on next entry (32->64 switcher only).
99	* Almost the same as CPUM_USE_DEBUG_REGS_HYPER in the raw-mode switchers. */
100	#define CPUM_SYNC_DEBUG_REGS_HYPER RT_BIT(18)
101	/** Host CPU requires fxsave/fxrstor leaky bit handling. */
102	#define CPUM_USE_FFXSR_LEAKY RT_BIT(19)
103	/** @} */
104
105	/* Sanity check. */
106	#ifndef VBOX_FOR_DTRACE_LIB
107	#if defined(VBOX_WITH_HYBRID_32BIT_KERNEL) && (HC_ARCH_BITS != 32 \|\| R0_ARCH_BITS != 32)
108	# error "VBOX_WITH_HYBRID_32BIT_KERNEL is only for 32 bit builds."
109	#endif
110	#endif
111
112
113	/**
114	* CPU features and quirks.
115	* This is mostly exploded CPUID info.
116	*/
117	typedef struct CPUMFEATURES
118	{
119	/** The CPU vendor (CPUMCPUVENDOR). */
120	uint8_t enmCpuVendor;
121	/** The CPU family. */
122	uint8_t uFamily;
123	/** The CPU model. */
124	uint8_t uModel;
125	/** The CPU stepping. */
126	uint8_t uStepping;
127	/** The microarchitecture. */
128	CPUMMICROARCH enmMicroarch;
129	/** The maximum physical address with of the CPU. */
130	uint8_t cMaxPhysAddrWidth;
131	/** Alignment padding. */
132	uint8_t abPadding[3];
133
134	/** Supports MSRs. */
135	uint32_t fMsr : 1;
136	/** Supports the page size extension (4/2 MB pages). */
137	uint32_t fPse : 1;
138	/** Supports 36-bit page size extension (4 MB pages can map memory above
139	* 4GB). */
140	uint32_t fPse36 : 1;
141	/** Supports physical address extension (PAE). */
142	uint32_t fPae : 1;
143	/** Page attribute table (PAT) support (page level cache control). */
144	uint32_t fPat : 1;
145	/** Supports the FXSAVE and FXRSTOR instructions. */
146	uint32_t fFxSaveRstor : 1;
147	/** Intel SYSENTER/SYSEXIT support */
148	uint32_t fSysEnter : 1;
149	/** First generation APIC. */
150	uint32_t fApic : 1;
151	/** Second generation APIC. */
152	uint32_t fX2Apic : 1;
153	/** Hypervisor present. */
154	uint32_t fHypervisorPresent : 1;
155	/** MWAIT & MONITOR instructions supported. */
156	uint32_t fMonitorMWait : 1;
157
158	/** AMD64: Supports long mode. */
159	uint32_t fLongMode : 1;
160	/** AMD64: SYSCALL/SYSRET support. */
161	uint32_t fSysCall : 1;
162	/** AMD64: No-execute page table bit. */
163	uint32_t fNoExecute : 1;
164	/** AMD64: Supports LAHF & SAHF instructions in 64-bit mode. */
165	uint32_t fLahfSahf : 1;
166	/** AMD64: Supports RDTSCP. */
167	uint32_t fRdTscP : 1;
168
169	/** Indicates that FPU instruction and data pointers may leak.
170	* This generally applies to recent AMD CPUs, where the FPU IP and DP pointer
171	* is only saved and restored if an exception is pending. */
172	uint32_t fLeakyFxSR : 1;
173
174	/** Alignment padding. */
175	uint32_t fPadding : 9;
176
177	uint64_t auPadding[2];
178	} CPUMFEATURES;
179	AssertCompileSize(CPUMFEATURES, 32);
180	/** Pointer to a CPU feature structure. */
181	typedef CPUMFEATURES *PCPUMFEATURES;
182	/** Pointer to a const CPU feature structure. */
183	typedef CPUMFEATURES const *PCCPUMFEATURES;
184
185
186	/**
187	* CPU info
188	*/
189	typedef struct CPUMINFO
190	{
191	/** The number of MSR ranges (CPUMMSRRANGE) in the array pointed to below. */
192	uint32_t cMsrRanges;
193	/** Mask applied to ECX before looking up the MSR for a RDMSR/WRMSR
194	* instruction. Older hardware has been observed to ignore higher bits. */
195	uint32_t fMsrMask;
196
197	/** The number of CPUID leaves (CPUMCPUIDLEAF) in the array pointed to below. */
198	uint32_t cCpuIdLeaves;
199	/** The index of the first extended CPUID leaf in the array.
200	* Set to cCpuIdLeaves if none present. */
201	uint32_t iFirstExtCpuIdLeaf;
202	/** Alignment padding. */
203	uint32_t uPadding;
204	/** How to handle unknown CPUID leaves. */
205	CPUMUKNOWNCPUID enmUnknownCpuIdMethod;
206	/** For use with CPUMUKNOWNCPUID_DEFAULTS. */
207	CPUMCPUID DefCpuId;
208
209	/** Scalable bus frequency used for reporting other frequencies. */
210	uint64_t uScalableBusFreq;
211
212	/** Pointer to the MSR ranges (ring-0 pointer). */
213	R0PTRTYPE(PCPUMMSRRANGE) paMsrRangesR0;
214	/** Pointer to the CPUID leaves (ring-0 pointer). */
215	R0PTRTYPE(PCPUMCPUIDLEAF) paCpuIdLeavesR0;
216
217	/** Pointer to the MSR ranges (ring-3 pointer). */
218	R3PTRTYPE(PCPUMMSRRANGE) paMsrRangesR3;
219	/** Pointer to the CPUID leaves (ring-3 pointer). */
220	R3PTRTYPE(PCPUMCPUIDLEAF) paCpuIdLeavesR3;
221
222	/** Pointer to the MSR ranges (raw-mode context pointer). */
223	RCPTRTYPE(PCPUMMSRRANGE) paMsrRangesRC;
224	/** Pointer to the CPUID leaves (raw-mode context pointer). */
225	RCPTRTYPE(PCPUMCPUIDLEAF) paCpuIdLeavesRC;
226	} CPUMINFO;
227	/** Pointer to a CPU info structure. */
228	typedef CPUMINFO *PCPUMINFO;
229	/** Pointer to a const CPU info structure. */
230	typedef CPUMINFO const *CPCPUMINFO;
231
232
233	/**
234	* The saved host CPU state.
235	*
236	* @remark The special VBOX_WITH_HYBRID_32BIT_KERNEL checks here are for the 10.4.x series
237	* of Mac OS X where the OS is essentially 32-bit but the cpu mode can be 64-bit.
238	*/
239	typedef struct CPUMHOSTCTX
240	{
241	/** FPU state. (16-byte alignment)
242	* @remark On x86, the format isn't necessarily X86FXSTATE (not important). */
243	X86FXSTATE fpu;
244
245	/** General purpose register, selectors, flags and more
246	* @{ */
247	#if HC_ARCH_BITS == 64 \|\| defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
248	/** General purpose register ++
249	* { */
250	/uint64_t rax; - scratch/
251	uint64_t rbx;
252	/uint64_t rcx; - scratch/
253	/uint64_t rdx; - scratch/
254	uint64_t rdi;
255	uint64_t rsi;
256	uint64_t rbp;
257	uint64_t rsp;
258	/uint64_t r8; - scratch/
259	/uint64_t r9; - scratch/
260	uint64_t r10;
261	uint64_t r11;
262	uint64_t r12;
263	uint64_t r13;
264	uint64_t r14;
265	uint64_t r15;
266	/uint64_t rip; - scratch/
267	uint64_t rflags;
268	#endif
269
270	#if HC_ARCH_BITS == 32
271	/uint32_t eax; - scratch/
272	uint32_t ebx;
273	/uint32_t ecx; - scratch/
274	/uint32_t edx; - scratch/
275	uint32_t edi;
276	uint32_t esi;
277	uint32_t ebp;
278	X86EFLAGS eflags;
279	/uint32_t eip; - scratch/
280	/* lss pair! */
281	uint32_t esp;
282	#endif
283	/** @} */
284
285	/** Selector registers
286	* @{ */
287	RTSEL ss;
288	RTSEL ssPadding;
289	RTSEL gs;
290	RTSEL gsPadding;
291	RTSEL fs;
292	RTSEL fsPadding;
293	RTSEL es;
294	RTSEL esPadding;
295	RTSEL ds;
296	RTSEL dsPadding;
297	RTSEL cs;
298	RTSEL csPadding;
299	/** @} */
300
301	#if HC_ARCH_BITS == 32 && !defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
302	/** Control registers.
303	* @{ */
304	uint32_t cr0;
305	/uint32_t cr2; - scratch/
306	uint32_t cr3;
307	uint32_t cr4;
308	/** @} */
309
310	/** Debug registers.
311	* @{ */
312	uint32_t dr0;
313	uint32_t dr1;
314	uint32_t dr2;
315	uint32_t dr3;
316	uint32_t dr6;
317	uint32_t dr7;
318	/** @} */
319
320	/** Global Descriptor Table register. */
321	X86XDTR32 gdtr;
322	uint16_t gdtrPadding;
323	/** Interrupt Descriptor Table register. */
324	X86XDTR32 idtr;
325	uint16_t idtrPadding;
326	/** The task register. */
327	RTSEL ldtr;
328	RTSEL ldtrPadding;
329	/** The task register. */
330	RTSEL tr;
331	RTSEL trPadding;
332	uint32_t SysEnterPadding;
333
334	/** The sysenter msr registers.
335	* This member is not used by the hypervisor context. */
336	CPUMSYSENTER SysEnter;
337
338	/** MSRs
339	* @{ */
340	uint64_t efer;
341	/** @} */
342
343	/* padding to get 64byte aligned size */
344	uint8_t auPadding[16+32];
345
346	#elif HC_ARCH_BITS == 64 \|\| defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
347
348	/** Control registers.
349	* @{ */
350	uint64_t cr0;
351	/uint64_t cr2; - scratch/
352	uint64_t cr3;
353	uint64_t cr4;
354	uint64_t cr8;
355	/** @} */
356
357	/** Debug registers.
358	* @{ */
359	uint64_t dr0;
360	uint64_t dr1;
361	uint64_t dr2;
362	uint64_t dr3;
363	uint64_t dr6;
364	uint64_t dr7;
365	/** @} */
366
367	/** Global Descriptor Table register. */
368	X86XDTR64 gdtr;
369	uint16_t gdtrPadding;
370	/** Interrupt Descriptor Table register. */
371	X86XDTR64 idtr;
372	uint16_t idtrPadding;
373	/** The task register. */
374	RTSEL ldtr;
375	RTSEL ldtrPadding;
376	/** The task register. */
377	RTSEL tr;
378	RTSEL trPadding;
379
380	/** MSRs
381	* @{ */
382	CPUMSYSENTER SysEnter;
383	uint64_t FSbase;
384	uint64_t GSbase;
385	uint64_t efer;
386	/** @} */
387
388	/* padding to get 32byte aligned size */
389	# ifdef VBOX_WITH_HYBRID_32BIT_KERNEL
390	uint8_t auPadding[16];
391	# else
392	uint8_t auPadding[8+32];
393	# endif
394
395	#else
396	# error HC_ARCH_BITS not defined
397	#endif
398	} CPUMHOSTCTX;
399	/** Pointer to the saved host CPU state. */
400	typedef CPUMHOSTCTX *PCPUMHOSTCTX;
401
402
403	/**
404	* CPUM Data (part of VM)
405	*/
406	typedef struct CPUM
407	{
408	/** Offset from CPUM to CPUMCPU for the first CPU. */
409	uint32_t offCPUMCPU0;
410
411	/** Use flags.
412	* These flags indicates which CPU features the host uses.
413	*/
414	uint32_t fHostUseFlags;
415
416	/** Host CPU Features - ECX */
417	struct
418	{
419	/** edx part */
420	X86CPUIDFEATEDX edx;
421	/** ecx part */
422	X86CPUIDFEATECX ecx;
423	} CPUFeatures;
424	/** Host extended CPU features. */
425	struct
426	{
427	/** edx part */
428	uint32_t edx;
429	/** ecx part */
430	uint32_t ecx;
431	} CPUFeaturesExt;
432
433	/** CR4 mask */
434	struct
435	{
436	uint32_t AndMask; /*< @todo Move these to the per-CPU structure and fix the switchers. Saves a register! /
437	uint32_t OrMask;
438	} CR4;
439
440	/** The (more) portable CPUID level. */
441	uint8_t u8PortableCpuIdLevel;
442	/** Indicates that a state restore is pending.
443	* This is used to verify load order dependencies (PGM). */
444	bool fPendingRestore;
445	uint8_t abPadding[HC_ARCH_BITS == 64 ? 6 : 2];
446
447	/** The standard set of CpuId leaves. */
448	CPUMCPUID aGuestCpuIdStd[6];
449	/** The extended set of CpuId leaves. */
450	CPUMCPUID aGuestCpuIdExt[10];
451	/** The centaur set of CpuId leaves. */
452	CPUMCPUID aGuestCpuIdCentaur[4];
453	/** The hypervisor specific set of CpuId leaves. */
454	CPUMCPUID aGuestCpuIdHyper[4];
455	/** The default set of CpuId leaves. */
456	CPUMCPUID GuestCpuIdDef;
457
458	#if HC_ARCH_BITS == 32
459	uint8_t abPadding2[4];
460	#endif
461
462	/** Guest CPU info. */
463	CPUMINFO GuestInfo;
464	/** Guest CPU feature information. */
465	CPUMFEATURES GuestFeatures;
466	/** Host CPU feature information. */
467	CPUMFEATURES HostFeatures;
468
469	/** @name MSR statistics.
470	* @{ */
471	STAMCOUNTER cMsrWrites;
472	STAMCOUNTER cMsrWritesToIgnoredBits;
473	STAMCOUNTER cMsrWritesRaiseGp;
474	STAMCOUNTER cMsrWritesUnknown;
475	STAMCOUNTER cMsrReads;
476	STAMCOUNTER cMsrReadsRaiseGp;
477	STAMCOUNTER cMsrReadsUnknown;
478	/** @} */
479	} CPUM;
480	/** Pointer to the CPUM instance data residing in the shared VM structure. */
481	typedef CPUM *PCPUM;
482
483	/**
484	* CPUM Data (part of VMCPU)
485	*/
486	typedef struct CPUMCPU
487	{
488	/**
489	* Hypervisor context.
490	* Aligned on a 64-byte boundary.
491	*/
492	CPUMCTX Hyper;
493
494	/**
495	* Saved host context. Only valid while inside GC.
496	* Aligned on a 64-byte boundary.
497	*/
498	CPUMHOSTCTX Host;
499
500	#ifdef VBOX_WITH_CRASHDUMP_MAGIC
501	uint8_t aMagic[56];
502	uint64_t uMagic;
503	#endif
504
505	/**
506	* Guest context.
507	* Aligned on a 64-byte boundary.
508	*/
509	CPUMCTX Guest;
510
511	/**
512	* Guest context - misc MSRs
513	* Aligned on a 64-byte boundary.
514	*/
515	CPUMCTXMSRS GuestMsrs;
516
517	/** Use flags.
518	* These flags indicates both what is to be used and what has been used.
519	*/
520	uint32_t fUseFlags;
521
522	/** Changed flags.
523	* These flags indicates to REM (and others) which important guest
524	* registers which has been changed since last time the flags were cleared.
525	* See the CPUM_CHANGED_* defines for what we keep track of.
526	*/
527	uint32_t fChanged;
528
529	/** Offset from CPUM to CPUMCPU. */
530	uint32_t offCPUM;
531
532	/** Temporary storage for the return code of the function called in the
533	* 32-64 switcher. */
534	uint32_t u32RetCode;
535
536	#ifdef VBOX_WITH_VMMR0_DISABLE_LAPIC_NMI
537	/** The address of the APIC mapping, NULL if no APIC.
538	* Call CPUMR0SetLApic to update this before doing a world switch. */
539	RTHCPTR pvApicBase;
540	/** Used by the world switcher code to store which vectors needs restoring on
541	* the way back. */
542	uint32_t fApicDisVectors;
543	/** Set if the CPU has the X2APIC mode enabled.
544	* Call CPUMR0SetLApic to update this before doing a world switch. */
545	bool fX2Apic;
546	#else
547	uint8_t abPadding3[(HC_ARCH_BITS == 64 ? 8 : 4) + 4 + 1];
548	#endif
549
550	/** Have we entered raw-mode? */
551	bool fRawEntered;
552	/** Have we entered the recompiler? */
553	bool fRemEntered;
554
555	/** Align the structure on a 64-byte boundary. */
556	uint8_t abPadding2[64 - 16 - (HC_ARCH_BITS == 64 ? 8 : 4) - 4 - 1 - 2];
557	} CPUMCPU;
558	/** Pointer to the CPUMCPU instance data residing in the shared VMCPU structure. */
559	typedef CPUMCPU *PCPUMCPU;
560
561	#ifndef VBOX_FOR_DTRACE_LIB
562	RT_C_DECLS_BEGIN
563
564	PCPUMCPUIDLEAF cpumCpuIdGetLeaf(PVM pVM, uint32_t uLeaf, uint32_t uSubLeaf);
565
566	#ifdef IN_RING3
567	int cpumR3DbgInit(PVM pVM);
568	PCPUMCPUIDLEAF cpumR3CpuIdGetLeaf(PCPUMCPUIDLEAF paLeaves, uint32_t cLeaves, uint32_t uLeaf, uint32_t uSubLeaf);
569	bool cpumR3CpuIdGetLeafLegacy(PCPUMCPUIDLEAF paLeaves, uint32_t cLeaves, uint32_t uLeaf, uint32_t uSubLeaf,
570	PCPUMCPUID pLeagcy);
571	int cpumR3CpuIdInsert(PVM pVM, PCPUMCPUIDLEAF ppaLeaves, uint32_t pcLeaves, PCPUMCPUIDLEAF pNewLeaf);
572	void cpumR3CpuIdRemoveRange(PCPUMCPUIDLEAF paLeaves, uint32_t *pcLeaves, uint32_t uFirst, uint32_t uLast);
573	int cpumR3CpuIdExplodeFeatures(PCCPUMCPUIDLEAF paLeaves, uint32_t cLeaves, PCPUMFEATURES pFeatures);
574	int cpumR3DbGetCpuInfo(const char *pszName, PCPUMINFO pInfo);
575	int cpumR3MsrRangesInsert(PVM pVM, PCPUMMSRRANGE ppaMsrRanges, uint32_t pcMsrRanges, PCCPUMMSRRANGE pNewRange);
576	int cpumR3MsrApplyFudge(PVM pVM);
577	int cpumR3MsrRegStats(PVM pVM);
578	int cpumR3MsrStrictInitChecks(void);
579	PCPUMMSRRANGE cpumLookupMsrRange(PVM pVM, uint32_t idMsr);
580	#endif
581
582	#ifdef IN_RC
583	DECLASM(int) cpumHandleLazyFPUAsm(PCPUMCPU pCPUM);
584	#endif
585
586	#ifdef IN_RING0
587	DECLASM(int) cpumR0SaveHostRestoreGuestFPUState(PCPUMCPU pCPUM);
588	DECLASM(int) cpumR0SaveGuestRestoreHostFPUState(PCPUMCPU pCPUM);
589	DECLASM(int) cpumR0SaveHostFPUState(PCPUMCPU pCPUM);
590	DECLASM(int) cpumR0RestoreHostFPUState(PCPUMCPU pCPUM);
591	DECLASM(void) cpumR0LoadFPU(PCPUMCTX pCtx);
592	DECLASM(void) cpumR0SaveFPU(PCPUMCTX pCtx);
593	DECLASM(void) cpumR0LoadXMM(PCPUMCTX pCtx);
594	DECLASM(void) cpumR0SaveXMM(PCPUMCTX pCtx);
595	DECLASM(void) cpumR0SetFCW(uint16_t u16FCW);
596	DECLASM(uint16_t) cpumR0GetFCW(void);
597	DECLASM(void) cpumR0SetMXCSR(uint32_t u32MXCSR);
598	DECLASM(uint32_t) cpumR0GetMXCSR(void);
599	DECLASM(void) cpumR0LoadDRx(uint64_t const *pa4Regs);
600	DECLASM(void) cpumR0SaveDRx(uint64_t *pa4Regs);
601	#endif
602
603	RT_C_DECLS_END
604	#endif /* !VBOX_FOR_DTRACE_LIB */
605
606	/** @} */
607
608	#endif
609

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source: vbox/trunk/src/VBox/VMM/include/CPUMInternal.h@ 51285

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