| 1 | /* $Id: CPUMInternal.h 52419 2014-08-19 16:12:46Z vboxsync $ */
|
|---|
| 2 | /** @file
|
|---|
| 3 | * CPUM - Internal header file.
|
|---|
| 4 | */
|
|---|
| 5 |
|
|---|
| 6 | /*
|
|---|
| 7 | * Copyright (C) 2006-2014 Oracle Corporation
|
|---|
| 8 | *
|
|---|
| 9 | * This file is part of VirtualBox Open Source Edition (OSE), as
|
|---|
| 10 | * available from http://www.virtualbox.org. This file is free software;
|
|---|
| 11 | * you can redistribute it and/or modify it under the terms of the GNU
|
|---|
| 12 | * General Public License (GPL) as published by the Free Software
|
|---|
| 13 | * Foundation, in version 2 as it comes in the "COPYING" file of the
|
|---|
| 14 | * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
|
|---|
| 15 | * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
|
|---|
| 16 | */
|
|---|
| 17 |
|
|---|
| 18 | #ifndef ___CPUMInternal_h
|
|---|
| 19 | #define ___CPUMInternal_h
|
|---|
| 20 |
|
|---|
| 21 | #ifndef VBOX_FOR_DTRACE_LIB
|
|---|
| 22 | # include <VBox/cdefs.h>
|
|---|
| 23 | # include <VBox/types.h>
|
|---|
| 24 | # include <VBox/vmm/stam.h>
|
|---|
| 25 | # include <iprt/x86.h>
|
|---|
| 26 | #else
|
|---|
| 27 | # pragma D depends_on library x86.d
|
|---|
| 28 | # pragma D depends_on library cpumctx.d
|
|---|
| 29 | #endif
|
|---|
| 30 |
|
|---|
| 31 |
|
|---|
| 32 |
|
|---|
| 33 |
|
|---|
| 34 | /** @defgroup grp_cpum_int Internals
|
|---|
| 35 | * @ingroup grp_cpum
|
|---|
| 36 | * @internal
|
|---|
| 37 | * @{
|
|---|
| 38 | */
|
|---|
| 39 |
|
|---|
| 40 | /** Flags and types for CPUM fault handlers
|
|---|
| 41 | * @{ */
|
|---|
| 42 | /** Type: Load DS */
|
|---|
| 43 | #define CPUM_HANDLER_DS 1
|
|---|
| 44 | /** Type: Load ES */
|
|---|
| 45 | #define CPUM_HANDLER_ES 2
|
|---|
| 46 | /** Type: Load FS */
|
|---|
| 47 | #define CPUM_HANDLER_FS 3
|
|---|
| 48 | /** Type: Load GS */
|
|---|
| 49 | #define CPUM_HANDLER_GS 4
|
|---|
| 50 | /** Type: IRET */
|
|---|
| 51 | #define CPUM_HANDLER_IRET 5
|
|---|
| 52 | /** Type mask. */
|
|---|
| 53 | #define CPUM_HANDLER_TYPEMASK 0xff
|
|---|
| 54 | /** If set EBP points to the CPUMCTXCORE that's being used. */
|
|---|
| 55 | #define CPUM_HANDLER_CTXCORE_IN_EBP RT_BIT(31)
|
|---|
| 56 | /** @} */
|
|---|
| 57 |
|
|---|
| 58 |
|
|---|
| 59 | /** Use flags (CPUM::fUseFlags).
|
|---|
| 60 | * (Don't forget to sync this with CPUMInternal.mac !)
|
|---|
| 61 | * @{ */
|
|---|
| 62 | /** Used the FPU, SSE or such stuff. */
|
|---|
| 63 | #define CPUM_USED_FPU RT_BIT(0)
|
|---|
| 64 | /** Used the FPU, SSE or such stuff since last we were in REM.
|
|---|
| 65 | * REM syncing is clearing this, lazy FPU is setting it. */
|
|---|
| 66 | #define CPUM_USED_FPU_SINCE_REM RT_BIT(1)
|
|---|
| 67 | /** The XMM state was manually restored. (AMD only) */
|
|---|
| 68 | #define CPUM_USED_MANUAL_XMM_RESTORE RT_BIT(2)
|
|---|
| 69 |
|
|---|
| 70 | /** Host OS is using SYSENTER and we must NULL the CS. */
|
|---|
| 71 | #define CPUM_USE_SYSENTER RT_BIT(3)
|
|---|
| 72 | /** Host OS is using SYSENTER and we must NULL the CS. */
|
|---|
| 73 | #define CPUM_USE_SYSCALL RT_BIT(4)
|
|---|
| 74 |
|
|---|
| 75 | /** Debug registers are used by host and that DR7 and DR6 must be saved and
|
|---|
| 76 | * disabled when switching to raw-mode. */
|
|---|
| 77 | #define CPUM_USE_DEBUG_REGS_HOST RT_BIT(5)
|
|---|
| 78 | /** Records that we've saved the host DRx registers.
|
|---|
| 79 | * In ring-0 this means all (DR0-7), while in raw-mode context this means DR0-3
|
|---|
| 80 | * since DR6 and DR7 are covered by CPUM_USE_DEBUG_REGS_HOST. */
|
|---|
| 81 | #define CPUM_USED_DEBUG_REGS_HOST RT_BIT(6)
|
|---|
| 82 | /** Set to indicate that we should save host DR0-7 and load the hypervisor debug
|
|---|
| 83 | * registers in the raw-mode world switchers. (See CPUMRecalcHyperDRx.) */
|
|---|
| 84 | #define CPUM_USE_DEBUG_REGS_HYPER RT_BIT(7)
|
|---|
| 85 | /** Used in ring-0 to indicate that we have loaded the hypervisor debug
|
|---|
| 86 | * registers. */
|
|---|
| 87 | #define CPUM_USED_DEBUG_REGS_HYPER RT_BIT(8)
|
|---|
| 88 | /** Used in ring-0 to indicate that we have loaded the guest debug
|
|---|
| 89 | * registers (DR0-3 and maybe DR6) for direct use by the guest.
|
|---|
| 90 | * DR7 (and AMD-V DR6) are handled via the VMCB. */
|
|---|
| 91 | #define CPUM_USED_DEBUG_REGS_GUEST RT_BIT(9)
|
|---|
| 92 |
|
|---|
| 93 |
|
|---|
| 94 | /** Sync the FPU state on next entry (32->64 switcher only). */
|
|---|
| 95 | #define CPUM_SYNC_FPU_STATE RT_BIT(16)
|
|---|
| 96 | /** Sync the debug state on next entry (32->64 switcher only). */
|
|---|
| 97 | #define CPUM_SYNC_DEBUG_REGS_GUEST RT_BIT(17)
|
|---|
| 98 | /** Sync the debug state on next entry (32->64 switcher only).
|
|---|
| 99 | * Almost the same as CPUM_USE_DEBUG_REGS_HYPER in the raw-mode switchers. */
|
|---|
| 100 | #define CPUM_SYNC_DEBUG_REGS_HYPER RT_BIT(18)
|
|---|
| 101 | /** Host CPU requires fxsave/fxrstor leaky bit handling. */
|
|---|
| 102 | #define CPUM_USE_FFXSR_LEAKY RT_BIT(19)
|
|---|
| 103 | /** Set if the VM supports long-mode. */
|
|---|
| 104 | #define CPUM_USE_SUPPORTS_LONGMODE RT_BIT(20)
|
|---|
| 105 | /** @} */
|
|---|
| 106 |
|
|---|
| 107 | /* Sanity check. */
|
|---|
| 108 | #ifndef VBOX_FOR_DTRACE_LIB
|
|---|
| 109 | #if defined(VBOX_WITH_HYBRID_32BIT_KERNEL) && (HC_ARCH_BITS != 32 || R0_ARCH_BITS != 32)
|
|---|
| 110 | # error "VBOX_WITH_HYBRID_32BIT_KERNEL is only for 32 bit builds."
|
|---|
| 111 | #endif
|
|---|
| 112 | #endif
|
|---|
| 113 |
|
|---|
| 114 |
|
|---|
| 115 | /**
|
|---|
| 116 | * CPU features and quirks.
|
|---|
| 117 | * This is mostly exploded CPUID info.
|
|---|
| 118 | */
|
|---|
| 119 | typedef struct CPUMFEATURES
|
|---|
| 120 | {
|
|---|
| 121 | /** The CPU vendor (CPUMCPUVENDOR). */
|
|---|
| 122 | uint8_t enmCpuVendor;
|
|---|
| 123 | /** The CPU family. */
|
|---|
| 124 | uint8_t uFamily;
|
|---|
| 125 | /** The CPU model. */
|
|---|
| 126 | uint8_t uModel;
|
|---|
| 127 | /** The CPU stepping. */
|
|---|
| 128 | uint8_t uStepping;
|
|---|
| 129 | /** The microarchitecture. */
|
|---|
| 130 | CPUMMICROARCH enmMicroarch;
|
|---|
| 131 | /** The maximum physical address with of the CPU. */
|
|---|
| 132 | uint8_t cMaxPhysAddrWidth;
|
|---|
| 133 | /** Alignment padding. */
|
|---|
| 134 | uint8_t abPadding[3];
|
|---|
| 135 |
|
|---|
| 136 | /** Supports MSRs. */
|
|---|
| 137 | uint32_t fMsr : 1;
|
|---|
| 138 | /** Supports the page size extension (4/2 MB pages). */
|
|---|
| 139 | uint32_t fPse : 1;
|
|---|
| 140 | /** Supports 36-bit page size extension (4 MB pages can map memory above
|
|---|
| 141 | * 4GB). */
|
|---|
| 142 | uint32_t fPse36 : 1;
|
|---|
| 143 | /** Supports physical address extension (PAE). */
|
|---|
| 144 | uint32_t fPae : 1;
|
|---|
| 145 | /** Page attribute table (PAT) support (page level cache control). */
|
|---|
| 146 | uint32_t fPat : 1;
|
|---|
| 147 | /** Supports the FXSAVE and FXRSTOR instructions. */
|
|---|
| 148 | uint32_t fFxSaveRstor : 1;
|
|---|
| 149 | /** Intel SYSENTER/SYSEXIT support */
|
|---|
| 150 | uint32_t fSysEnter : 1;
|
|---|
| 151 | /** First generation APIC. */
|
|---|
| 152 | uint32_t fApic : 1;
|
|---|
| 153 | /** Second generation APIC. */
|
|---|
| 154 | uint32_t fX2Apic : 1;
|
|---|
| 155 | /** Hypervisor present. */
|
|---|
| 156 | uint32_t fHypervisorPresent : 1;
|
|---|
| 157 | /** MWAIT & MONITOR instructions supported. */
|
|---|
| 158 | uint32_t fMonitorMWait : 1;
|
|---|
| 159 | /** MWAIT Extensions present. */
|
|---|
| 160 | uint32_t fMWaitExtensions : 1;
|
|---|
| 161 |
|
|---|
| 162 | /** AMD64: Supports long mode. */
|
|---|
| 163 | uint32_t fLongMode : 1;
|
|---|
| 164 | /** AMD64: SYSCALL/SYSRET support. */
|
|---|
| 165 | uint32_t fSysCall : 1;
|
|---|
| 166 | /** AMD64: No-execute page table bit. */
|
|---|
| 167 | uint32_t fNoExecute : 1;
|
|---|
| 168 | /** AMD64: Supports LAHF & SAHF instructions in 64-bit mode. */
|
|---|
| 169 | uint32_t fLahfSahf : 1;
|
|---|
| 170 | /** AMD64: Supports RDTSCP. */
|
|---|
| 171 | uint32_t fRdTscP : 1;
|
|---|
| 172 |
|
|---|
| 173 | /** Indicates that FPU instruction and data pointers may leak.
|
|---|
| 174 | * This generally applies to recent AMD CPUs, where the FPU IP and DP pointer
|
|---|
| 175 | * is only saved and restored if an exception is pending. */
|
|---|
| 176 | uint32_t fLeakyFxSR : 1;
|
|---|
| 177 |
|
|---|
| 178 | /** Alignment padding. */
|
|---|
| 179 | uint32_t fPadding : 8;
|
|---|
| 180 |
|
|---|
| 181 | uint64_t auPadding[2];
|
|---|
| 182 | } CPUMFEATURES;
|
|---|
| 183 | AssertCompileSize(CPUMFEATURES, 32);
|
|---|
| 184 | /** Pointer to a CPU feature structure. */
|
|---|
| 185 | typedef CPUMFEATURES *PCPUMFEATURES;
|
|---|
| 186 | /** Pointer to a const CPU feature structure. */
|
|---|
| 187 | typedef CPUMFEATURES const *PCCPUMFEATURES;
|
|---|
| 188 |
|
|---|
| 189 |
|
|---|
| 190 | /**
|
|---|
| 191 | * CPU info
|
|---|
| 192 | */
|
|---|
| 193 | typedef struct CPUMINFO
|
|---|
| 194 | {
|
|---|
| 195 | /** The number of MSR ranges (CPUMMSRRANGE) in the array pointed to below. */
|
|---|
| 196 | uint32_t cMsrRanges;
|
|---|
| 197 | /** Mask applied to ECX before looking up the MSR for a RDMSR/WRMSR
|
|---|
| 198 | * instruction. Older hardware has been observed to ignore higher bits. */
|
|---|
| 199 | uint32_t fMsrMask;
|
|---|
| 200 |
|
|---|
| 201 | /** The number of CPUID leaves (CPUMCPUIDLEAF) in the array pointed to below. */
|
|---|
| 202 | uint32_t cCpuIdLeaves;
|
|---|
| 203 | /** The index of the first extended CPUID leaf in the array.
|
|---|
| 204 | * Set to cCpuIdLeaves if none present. */
|
|---|
| 205 | uint32_t iFirstExtCpuIdLeaf;
|
|---|
| 206 | /** Alignment padding. */
|
|---|
| 207 | uint32_t uPadding;
|
|---|
| 208 | /** How to handle unknown CPUID leaves. */
|
|---|
| 209 | CPUMUKNOWNCPUID enmUnknownCpuIdMethod;
|
|---|
| 210 | /** For use with CPUMUKNOWNCPUID_DEFAULTS. */
|
|---|
| 211 | CPUMCPUID DefCpuId;
|
|---|
| 212 |
|
|---|
| 213 | /** Scalable bus frequency used for reporting other frequencies. */
|
|---|
| 214 | uint64_t uScalableBusFreq;
|
|---|
| 215 |
|
|---|
| 216 | /** Pointer to the MSR ranges (ring-0 pointer). */
|
|---|
| 217 | R0PTRTYPE(PCPUMMSRRANGE) paMsrRangesR0;
|
|---|
| 218 | /** Pointer to the CPUID leaves (ring-0 pointer). */
|
|---|
| 219 | R0PTRTYPE(PCPUMCPUIDLEAF) paCpuIdLeavesR0;
|
|---|
| 220 |
|
|---|
| 221 | /** Pointer to the MSR ranges (ring-3 pointer). */
|
|---|
| 222 | R3PTRTYPE(PCPUMMSRRANGE) paMsrRangesR3;
|
|---|
| 223 | /** Pointer to the CPUID leaves (ring-3 pointer). */
|
|---|
| 224 | R3PTRTYPE(PCPUMCPUIDLEAF) paCpuIdLeavesR3;
|
|---|
| 225 |
|
|---|
| 226 | /** Pointer to the MSR ranges (raw-mode context pointer). */
|
|---|
| 227 | RCPTRTYPE(PCPUMMSRRANGE) paMsrRangesRC;
|
|---|
| 228 | /** Pointer to the CPUID leaves (raw-mode context pointer). */
|
|---|
| 229 | RCPTRTYPE(PCPUMCPUIDLEAF) paCpuIdLeavesRC;
|
|---|
| 230 | } CPUMINFO;
|
|---|
| 231 | /** Pointer to a CPU info structure. */
|
|---|
| 232 | typedef CPUMINFO *PCPUMINFO;
|
|---|
| 233 | /** Pointer to a const CPU info structure. */
|
|---|
| 234 | typedef CPUMINFO const *CPCPUMINFO;
|
|---|
| 235 |
|
|---|
| 236 |
|
|---|
| 237 | /**
|
|---|
| 238 | * The saved host CPU state.
|
|---|
| 239 | *
|
|---|
| 240 | * @remark The special VBOX_WITH_HYBRID_32BIT_KERNEL checks here are for the 10.4.x series
|
|---|
| 241 | * of Mac OS X where the OS is essentially 32-bit but the cpu mode can be 64-bit.
|
|---|
| 242 | */
|
|---|
| 243 | typedef struct CPUMHOSTCTX
|
|---|
| 244 | {
|
|---|
| 245 | /** FPU state. (16-byte alignment)
|
|---|
| 246 | * @remark On x86, the format isn't necessarily X86FXSTATE (not important). */
|
|---|
| 247 | X86FXSTATE fpu;
|
|---|
| 248 |
|
|---|
| 249 | /** General purpose register, selectors, flags and more
|
|---|
| 250 | * @{ */
|
|---|
| 251 | #if HC_ARCH_BITS == 64 || defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
|
|---|
| 252 | /** General purpose register ++
|
|---|
| 253 | * { */
|
|---|
| 254 | /*uint64_t rax; - scratch*/
|
|---|
| 255 | uint64_t rbx;
|
|---|
| 256 | /*uint64_t rcx; - scratch*/
|
|---|
| 257 | /*uint64_t rdx; - scratch*/
|
|---|
| 258 | uint64_t rdi;
|
|---|
| 259 | uint64_t rsi;
|
|---|
| 260 | uint64_t rbp;
|
|---|
| 261 | uint64_t rsp;
|
|---|
| 262 | /*uint64_t r8; - scratch*/
|
|---|
| 263 | /*uint64_t r9; - scratch*/
|
|---|
| 264 | uint64_t r10;
|
|---|
| 265 | uint64_t r11;
|
|---|
| 266 | uint64_t r12;
|
|---|
| 267 | uint64_t r13;
|
|---|
| 268 | uint64_t r14;
|
|---|
| 269 | uint64_t r15;
|
|---|
| 270 | /*uint64_t rip; - scratch*/
|
|---|
| 271 | uint64_t rflags;
|
|---|
| 272 | #endif
|
|---|
| 273 |
|
|---|
| 274 | #if HC_ARCH_BITS == 32
|
|---|
| 275 | /*uint32_t eax; - scratch*/
|
|---|
| 276 | uint32_t ebx;
|
|---|
| 277 | /*uint32_t ecx; - scratch*/
|
|---|
| 278 | /*uint32_t edx; - scratch*/
|
|---|
| 279 | uint32_t edi;
|
|---|
| 280 | uint32_t esi;
|
|---|
| 281 | uint32_t ebp;
|
|---|
| 282 | X86EFLAGS eflags;
|
|---|
| 283 | /*uint32_t eip; - scratch*/
|
|---|
| 284 | /* lss pair! */
|
|---|
| 285 | uint32_t esp;
|
|---|
| 286 | #endif
|
|---|
| 287 | /** @} */
|
|---|
| 288 |
|
|---|
| 289 | /** Selector registers
|
|---|
| 290 | * @{ */
|
|---|
| 291 | RTSEL ss;
|
|---|
| 292 | RTSEL ssPadding;
|
|---|
| 293 | RTSEL gs;
|
|---|
| 294 | RTSEL gsPadding;
|
|---|
| 295 | RTSEL fs;
|
|---|
| 296 | RTSEL fsPadding;
|
|---|
| 297 | RTSEL es;
|
|---|
| 298 | RTSEL esPadding;
|
|---|
| 299 | RTSEL ds;
|
|---|
| 300 | RTSEL dsPadding;
|
|---|
| 301 | RTSEL cs;
|
|---|
| 302 | RTSEL csPadding;
|
|---|
| 303 | /** @} */
|
|---|
| 304 |
|
|---|
| 305 | #if HC_ARCH_BITS == 32 && !defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
|
|---|
| 306 | /** Control registers.
|
|---|
| 307 | * @{ */
|
|---|
| 308 | uint32_t cr0;
|
|---|
| 309 | /*uint32_t cr2; - scratch*/
|
|---|
| 310 | uint32_t cr3;
|
|---|
| 311 | uint32_t cr4;
|
|---|
| 312 | /** @} */
|
|---|
| 313 |
|
|---|
| 314 | /** Debug registers.
|
|---|
| 315 | * @{ */
|
|---|
| 316 | uint32_t dr0;
|
|---|
| 317 | uint32_t dr1;
|
|---|
| 318 | uint32_t dr2;
|
|---|
| 319 | uint32_t dr3;
|
|---|
| 320 | uint32_t dr6;
|
|---|
| 321 | uint32_t dr7;
|
|---|
| 322 | /** @} */
|
|---|
| 323 |
|
|---|
| 324 | /** Global Descriptor Table register. */
|
|---|
| 325 | X86XDTR32 gdtr;
|
|---|
| 326 | uint16_t gdtrPadding;
|
|---|
| 327 | /** Interrupt Descriptor Table register. */
|
|---|
| 328 | X86XDTR32 idtr;
|
|---|
| 329 | uint16_t idtrPadding;
|
|---|
| 330 | /** The task register. */
|
|---|
| 331 | RTSEL ldtr;
|
|---|
| 332 | RTSEL ldtrPadding;
|
|---|
| 333 | /** The task register. */
|
|---|
| 334 | RTSEL tr;
|
|---|
| 335 | RTSEL trPadding;
|
|---|
| 336 | uint32_t SysEnterPadding;
|
|---|
| 337 |
|
|---|
| 338 | /** The sysenter msr registers.
|
|---|
| 339 | * This member is not used by the hypervisor context. */
|
|---|
| 340 | CPUMSYSENTER SysEnter;
|
|---|
| 341 |
|
|---|
| 342 | /** MSRs
|
|---|
| 343 | * @{ */
|
|---|
| 344 | uint64_t efer;
|
|---|
| 345 | /** @} */
|
|---|
| 346 |
|
|---|
| 347 | /* padding to get 64byte aligned size */
|
|---|
| 348 | uint8_t auPadding[16+32];
|
|---|
| 349 |
|
|---|
| 350 | #elif HC_ARCH_BITS == 64 || defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
|
|---|
| 351 |
|
|---|
| 352 | /** Control registers.
|
|---|
| 353 | * @{ */
|
|---|
| 354 | uint64_t cr0;
|
|---|
| 355 | /*uint64_t cr2; - scratch*/
|
|---|
| 356 | uint64_t cr3;
|
|---|
| 357 | uint64_t cr4;
|
|---|
| 358 | uint64_t cr8;
|
|---|
| 359 | /** @} */
|
|---|
| 360 |
|
|---|
| 361 | /** Debug registers.
|
|---|
| 362 | * @{ */
|
|---|
| 363 | uint64_t dr0;
|
|---|
| 364 | uint64_t dr1;
|
|---|
| 365 | uint64_t dr2;
|
|---|
| 366 | uint64_t dr3;
|
|---|
| 367 | uint64_t dr6;
|
|---|
| 368 | uint64_t dr7;
|
|---|
| 369 | /** @} */
|
|---|
| 370 |
|
|---|
| 371 | /** Global Descriptor Table register. */
|
|---|
| 372 | X86XDTR64 gdtr;
|
|---|
| 373 | uint16_t gdtrPadding;
|
|---|
| 374 | /** Interrupt Descriptor Table register. */
|
|---|
| 375 | X86XDTR64 idtr;
|
|---|
| 376 | uint16_t idtrPadding;
|
|---|
| 377 | /** The task register. */
|
|---|
| 378 | RTSEL ldtr;
|
|---|
| 379 | RTSEL ldtrPadding;
|
|---|
| 380 | /** The task register. */
|
|---|
| 381 | RTSEL tr;
|
|---|
| 382 | RTSEL trPadding;
|
|---|
| 383 |
|
|---|
| 384 | /** MSRs
|
|---|
| 385 | * @{ */
|
|---|
| 386 | CPUMSYSENTER SysEnter;
|
|---|
| 387 | uint64_t FSbase;
|
|---|
| 388 | uint64_t GSbase;
|
|---|
| 389 | uint64_t efer;
|
|---|
| 390 | /** @} */
|
|---|
| 391 |
|
|---|
| 392 | /* padding to get 32byte aligned size */
|
|---|
| 393 | # ifdef VBOX_WITH_HYBRID_32BIT_KERNEL
|
|---|
| 394 | uint8_t auPadding[16];
|
|---|
| 395 | # else
|
|---|
| 396 | uint8_t auPadding[8+32];
|
|---|
| 397 | # endif
|
|---|
| 398 |
|
|---|
| 399 | #else
|
|---|
| 400 | # error HC_ARCH_BITS not defined
|
|---|
| 401 | #endif
|
|---|
| 402 | } CPUMHOSTCTX;
|
|---|
| 403 | /** Pointer to the saved host CPU state. */
|
|---|
| 404 | typedef CPUMHOSTCTX *PCPUMHOSTCTX;
|
|---|
| 405 |
|
|---|
| 406 |
|
|---|
| 407 | /**
|
|---|
| 408 | * CPUM Data (part of VM)
|
|---|
| 409 | */
|
|---|
| 410 | typedef struct CPUM
|
|---|
| 411 | {
|
|---|
| 412 | /** Offset from CPUM to CPUMCPU for the first CPU. */
|
|---|
| 413 | uint32_t offCPUMCPU0;
|
|---|
| 414 |
|
|---|
| 415 | /** Use flags.
|
|---|
| 416 | * These flags indicates which CPU features the host uses.
|
|---|
| 417 | */
|
|---|
| 418 | uint32_t fHostUseFlags;
|
|---|
| 419 |
|
|---|
| 420 | /** Host CPU Features - ECX */
|
|---|
| 421 | struct
|
|---|
| 422 | {
|
|---|
| 423 | /** edx part */
|
|---|
| 424 | X86CPUIDFEATEDX edx;
|
|---|
| 425 | /** ecx part */
|
|---|
| 426 | X86CPUIDFEATECX ecx;
|
|---|
| 427 | } CPUFeatures;
|
|---|
| 428 | /** Host extended CPU features. */
|
|---|
| 429 | struct
|
|---|
| 430 | {
|
|---|
| 431 | /** edx part */
|
|---|
| 432 | uint32_t edx;
|
|---|
| 433 | /** ecx part */
|
|---|
| 434 | uint32_t ecx;
|
|---|
| 435 | } CPUFeaturesExt;
|
|---|
| 436 |
|
|---|
| 437 | /** CR4 mask */
|
|---|
| 438 | struct
|
|---|
| 439 | {
|
|---|
| 440 | uint32_t AndMask; /**< @todo Move these to the per-CPU structure and fix the switchers. Saves a register! */
|
|---|
| 441 | uint32_t OrMask;
|
|---|
| 442 | } CR4;
|
|---|
| 443 |
|
|---|
| 444 | /** The (more) portable CPUID level. */
|
|---|
| 445 | uint8_t u8PortableCpuIdLevel;
|
|---|
| 446 | /** Indicates that a state restore is pending.
|
|---|
| 447 | * This is used to verify load order dependencies (PGM). */
|
|---|
| 448 | bool fPendingRestore;
|
|---|
| 449 | uint8_t abPadding[HC_ARCH_BITS == 64 ? 6 : 2];
|
|---|
| 450 |
|
|---|
| 451 | /** The standard set of CpuId leaves. */
|
|---|
| 452 | CPUMCPUID aGuestCpuIdStd[6];
|
|---|
| 453 | /** The extended set of CpuId leaves. */
|
|---|
| 454 | CPUMCPUID aGuestCpuIdExt[10];
|
|---|
| 455 | /** The centaur set of CpuId leaves. */
|
|---|
| 456 | CPUMCPUID aGuestCpuIdCentaur[4];
|
|---|
| 457 | /** The default set of CpuId leaves. */
|
|---|
| 458 | CPUMCPUID GuestCpuIdDef;
|
|---|
| 459 |
|
|---|
| 460 | #if HC_ARCH_BITS == 32
|
|---|
| 461 | uint8_t abPadding2[4];
|
|---|
| 462 | #endif
|
|---|
| 463 |
|
|---|
| 464 | /** Guest CPU info. */
|
|---|
| 465 | CPUMINFO GuestInfo;
|
|---|
| 466 | /** Guest CPU feature information. */
|
|---|
| 467 | CPUMFEATURES GuestFeatures;
|
|---|
| 468 | /** Host CPU feature information. */
|
|---|
| 469 | CPUMFEATURES HostFeatures;
|
|---|
| 470 |
|
|---|
| 471 | /** @name MSR statistics.
|
|---|
| 472 | * @{ */
|
|---|
| 473 | STAMCOUNTER cMsrWrites;
|
|---|
| 474 | STAMCOUNTER cMsrWritesToIgnoredBits;
|
|---|
| 475 | STAMCOUNTER cMsrWritesRaiseGp;
|
|---|
| 476 | STAMCOUNTER cMsrWritesUnknown;
|
|---|
| 477 | STAMCOUNTER cMsrReads;
|
|---|
| 478 | STAMCOUNTER cMsrReadsRaiseGp;
|
|---|
| 479 | STAMCOUNTER cMsrReadsUnknown;
|
|---|
| 480 | /** @} */
|
|---|
| 481 | } CPUM;
|
|---|
| 482 | /** Pointer to the CPUM instance data residing in the shared VM structure. */
|
|---|
| 483 | typedef CPUM *PCPUM;
|
|---|
| 484 |
|
|---|
| 485 | /**
|
|---|
| 486 | * CPUM Data (part of VMCPU)
|
|---|
| 487 | */
|
|---|
| 488 | typedef struct CPUMCPU
|
|---|
| 489 | {
|
|---|
| 490 | /**
|
|---|
| 491 | * Hypervisor context.
|
|---|
| 492 | * Aligned on a 64-byte boundary.
|
|---|
| 493 | */
|
|---|
| 494 | CPUMCTX Hyper;
|
|---|
| 495 |
|
|---|
| 496 | /**
|
|---|
| 497 | * Saved host context. Only valid while inside GC.
|
|---|
| 498 | * Aligned on a 64-byte boundary.
|
|---|
| 499 | */
|
|---|
| 500 | CPUMHOSTCTX Host;
|
|---|
| 501 |
|
|---|
| 502 | #ifdef VBOX_WITH_CRASHDUMP_MAGIC
|
|---|
| 503 | uint8_t aMagic[56];
|
|---|
| 504 | uint64_t uMagic;
|
|---|
| 505 | #endif
|
|---|
| 506 |
|
|---|
| 507 | /**
|
|---|
| 508 | * Guest context.
|
|---|
| 509 | * Aligned on a 64-byte boundary.
|
|---|
| 510 | */
|
|---|
| 511 | CPUMCTX Guest;
|
|---|
| 512 |
|
|---|
| 513 | /**
|
|---|
| 514 | * Guest context - misc MSRs
|
|---|
| 515 | * Aligned on a 64-byte boundary.
|
|---|
| 516 | */
|
|---|
| 517 | CPUMCTXMSRS GuestMsrs;
|
|---|
| 518 |
|
|---|
| 519 | /** Use flags.
|
|---|
| 520 | * These flags indicates both what is to be used and what has been used.
|
|---|
| 521 | */
|
|---|
| 522 | uint32_t fUseFlags;
|
|---|
| 523 |
|
|---|
| 524 | /** Changed flags.
|
|---|
| 525 | * These flags indicates to REM (and others) which important guest
|
|---|
| 526 | * registers which has been changed since last time the flags were cleared.
|
|---|
| 527 | * See the CPUM_CHANGED_* defines for what we keep track of.
|
|---|
| 528 | */
|
|---|
| 529 | uint32_t fChanged;
|
|---|
| 530 |
|
|---|
| 531 | /** Offset from CPUM to CPUMCPU. */
|
|---|
| 532 | uint32_t offCPUM;
|
|---|
| 533 |
|
|---|
| 534 | /** Temporary storage for the return code of the function called in the
|
|---|
| 535 | * 32-64 switcher. */
|
|---|
| 536 | uint32_t u32RetCode;
|
|---|
| 537 |
|
|---|
| 538 | #ifdef VBOX_WITH_VMMR0_DISABLE_LAPIC_NMI
|
|---|
| 539 | /** The address of the APIC mapping, NULL if no APIC.
|
|---|
| 540 | * Call CPUMR0SetLApic to update this before doing a world switch. */
|
|---|
| 541 | RTHCPTR pvApicBase;
|
|---|
| 542 | /** Used by the world switcher code to store which vectors needs restoring on
|
|---|
| 543 | * the way back. */
|
|---|
| 544 | uint32_t fApicDisVectors;
|
|---|
| 545 | /** Set if the CPU has the X2APIC mode enabled.
|
|---|
| 546 | * Call CPUMR0SetLApic to update this before doing a world switch. */
|
|---|
| 547 | bool fX2Apic;
|
|---|
| 548 | #else
|
|---|
| 549 | uint8_t abPadding3[(HC_ARCH_BITS == 64 ? 8 : 4) + 4 + 1];
|
|---|
| 550 | #endif
|
|---|
| 551 |
|
|---|
| 552 | /** Have we entered raw-mode? */
|
|---|
| 553 | bool fRawEntered;
|
|---|
| 554 | /** Have we entered the recompiler? */
|
|---|
| 555 | bool fRemEntered;
|
|---|
| 556 |
|
|---|
| 557 | /** Align the structure on a 64-byte boundary. */
|
|---|
| 558 | uint8_t abPadding2[64 - 16 - (HC_ARCH_BITS == 64 ? 8 : 4) - 4 - 1 - 2];
|
|---|
| 559 | } CPUMCPU;
|
|---|
| 560 | /** Pointer to the CPUMCPU instance data residing in the shared VMCPU structure. */
|
|---|
| 561 | typedef CPUMCPU *PCPUMCPU;
|
|---|
| 562 |
|
|---|
| 563 | #ifndef VBOX_FOR_DTRACE_LIB
|
|---|
| 564 | RT_C_DECLS_BEGIN
|
|---|
| 565 |
|
|---|
| 566 | PCPUMCPUIDLEAF cpumCpuIdGetLeaf(PVM pVM, uint32_t uLeaf, uint32_t uSubLeaf);
|
|---|
| 567 |
|
|---|
| 568 | #ifdef IN_RING3
|
|---|
| 569 | int cpumR3DbgInit(PVM pVM);
|
|---|
| 570 | PCPUMCPUIDLEAF cpumR3CpuIdGetLeaf(PCPUMCPUIDLEAF paLeaves, uint32_t cLeaves, uint32_t uLeaf, uint32_t uSubLeaf);
|
|---|
| 571 | bool cpumR3CpuIdGetLeafLegacy(PCPUMCPUIDLEAF paLeaves, uint32_t cLeaves, uint32_t uLeaf, uint32_t uSubLeaf,
|
|---|
| 572 | PCPUMCPUID pLeagcy);
|
|---|
| 573 | int cpumR3CpuIdInsert(PVM pVM, PCPUMCPUIDLEAF *ppaLeaves, uint32_t *pcLeaves, PCPUMCPUIDLEAF pNewLeaf);
|
|---|
| 574 | void cpumR3CpuIdRemoveRange(PCPUMCPUIDLEAF paLeaves, uint32_t *pcLeaves, uint32_t uFirst, uint32_t uLast);
|
|---|
| 575 | int cpumR3CpuIdExplodeFeatures(PCCPUMCPUIDLEAF paLeaves, uint32_t cLeaves, PCPUMFEATURES pFeatures);
|
|---|
| 576 | int cpumR3DbGetCpuInfo(const char *pszName, PCPUMINFO pInfo);
|
|---|
| 577 | int cpumR3MsrRangesInsert(PVM pVM, PCPUMMSRRANGE *ppaMsrRanges, uint32_t *pcMsrRanges, PCCPUMMSRRANGE pNewRange);
|
|---|
| 578 | int cpumR3MsrApplyFudge(PVM pVM);
|
|---|
| 579 | int cpumR3MsrRegStats(PVM pVM);
|
|---|
| 580 | int cpumR3MsrStrictInitChecks(void);
|
|---|
| 581 | PCPUMMSRRANGE cpumLookupMsrRange(PVM pVM, uint32_t idMsr);
|
|---|
| 582 | #endif
|
|---|
| 583 |
|
|---|
| 584 | #ifdef IN_RC
|
|---|
| 585 | DECLASM(int) cpumHandleLazyFPUAsm(PCPUMCPU pCPUM);
|
|---|
| 586 | #endif
|
|---|
| 587 |
|
|---|
| 588 | #ifdef IN_RING0
|
|---|
| 589 | DECLASM(int) cpumR0SaveHostRestoreGuestFPUState(PCPUMCPU pCPUM);
|
|---|
| 590 | DECLASM(int) cpumR0SaveGuestRestoreHostFPUState(PCPUMCPU pCPUM);
|
|---|
| 591 | DECLASM(int) cpumR0SaveHostFPUState(PCPUMCPU pCPUM);
|
|---|
| 592 | DECLASM(int) cpumR0RestoreHostFPUState(PCPUMCPU pCPUM);
|
|---|
| 593 | DECLASM(void) cpumR0LoadFPU(PCPUMCTX pCtx);
|
|---|
| 594 | DECLASM(void) cpumR0SaveFPU(PCPUMCTX pCtx);
|
|---|
| 595 | DECLASM(void) cpumR0LoadXMM(PCPUMCTX pCtx);
|
|---|
| 596 | DECLASM(void) cpumR0SaveXMM(PCPUMCTX pCtx);
|
|---|
| 597 | DECLASM(void) cpumR0SetFCW(uint16_t u16FCW);
|
|---|
| 598 | DECLASM(uint16_t) cpumR0GetFCW(void);
|
|---|
| 599 | DECLASM(void) cpumR0SetMXCSR(uint32_t u32MXCSR);
|
|---|
| 600 | DECLASM(uint32_t) cpumR0GetMXCSR(void);
|
|---|
| 601 | DECLASM(void) cpumR0LoadDRx(uint64_t const *pa4Regs);
|
|---|
| 602 | DECLASM(void) cpumR0SaveDRx(uint64_t *pa4Regs);
|
|---|
| 603 | #endif
|
|---|
| 604 |
|
|---|
| 605 | RT_C_DECLS_END
|
|---|
| 606 | #endif /* !VBOX_FOR_DTRACE_LIB */
|
|---|
| 607 |
|
|---|
| 608 | /** @} */
|
|---|
| 609 |
|
|---|
| 610 | #endif
|
|---|
| 611 |
|
|---|
