CPUMInternal.h@ 54733

Last change on this file since 54733 was 54674, checked in by vboxsync, 10 years ago
CPUM: Working on refactoring the guest CPUID handling.
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1	/* $Id: CPUMInternal.h 54674 2015-03-06 18:02:31Z vboxsync $ */
2	/** @file
3	* CPUM - Internal header file.
4	*/
5
6	/*
7	* Copyright (C) 2006-2015 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*/
17
18	#ifndef ___CPUMInternal_h
19	#define ___CPUMInternal_h
20
21	#ifndef VBOX_FOR_DTRACE_LIB
22	# include <VBox/cdefs.h>
23	# include <VBox/types.h>
24	# include <VBox/vmm/stam.h>
25	# include <iprt/x86.h>
26	#else
27	# pragma D depends_on library x86.d
28	# pragma D depends_on library cpumctx.d
29
30	/* Some fudging. */
31	typedef uint32_t CPUMMICROARCH;
32	typedef uint32_t CPUMUKNOWNCPUID;
33	typedef struct CPUMCPUIDLEAF *PCPUMCPUIDLEAF;
34	typedef struct CPUMMSRRANGE *PCPUMMSRRANGE;
35	typedef uint64_t STAMCOUNTER;
36	#endif
37
38
39
40
41	/** @defgroup grp_cpum_int Internals
42	* @ingroup grp_cpum
43	* @internal
44	* @{
45	*/
46
47	/** Flags and types for CPUM fault handlers
48	* @{ */
49	/** Type: Load DS */
50	#define CPUM_HANDLER_DS 1
51	/** Type: Load ES */
52	#define CPUM_HANDLER_ES 2
53	/** Type: Load FS */
54	#define CPUM_HANDLER_FS 3
55	/** Type: Load GS */
56	#define CPUM_HANDLER_GS 4
57	/** Type: IRET */
58	#define CPUM_HANDLER_IRET 5
59	/** Type mask. */
60	#define CPUM_HANDLER_TYPEMASK 0xff
61	/** If set EBP points to the CPUMCTXCORE that's being used. */
62	#define CPUM_HANDLER_CTXCORE_IN_EBP RT_BIT(31)
63	/** @} */
64
65
66	/** Use flags (CPUM::fUseFlags).
67	* (Don't forget to sync this with CPUMInternal.mac !)
68	* @{ */
69	/** Used the FPU, SSE or such stuff. */
70	#define CPUM_USED_FPU RT_BIT(0)
71	/** Used the FPU, SSE or such stuff since last we were in REM.
72	* REM syncing is clearing this, lazy FPU is setting it. */
73	#define CPUM_USED_FPU_SINCE_REM RT_BIT(1)
74	/** The XMM state was manually restored. (AMD only) */
75	#define CPUM_USED_MANUAL_XMM_RESTORE RT_BIT(2)
76
77	/** Host OS is using SYSENTER and we must NULL the CS. */
78	#define CPUM_USE_SYSENTER RT_BIT(3)
79	/** Host OS is using SYSENTER and we must NULL the CS. */
80	#define CPUM_USE_SYSCALL RT_BIT(4)
81
82	/** Debug registers are used by host and that DR7 and DR6 must be saved and
83	* disabled when switching to raw-mode. */
84	#define CPUM_USE_DEBUG_REGS_HOST RT_BIT(5)
85	/** Records that we've saved the host DRx registers.
86	* In ring-0 this means all (DR0-7), while in raw-mode context this means DR0-3
87	* since DR6 and DR7 are covered by CPUM_USE_DEBUG_REGS_HOST. */
88	#define CPUM_USED_DEBUG_REGS_HOST RT_BIT(6)
89	/** Set to indicate that we should save host DR0-7 and load the hypervisor debug
90	* registers in the raw-mode world switchers. (See CPUMRecalcHyperDRx.) */
91	#define CPUM_USE_DEBUG_REGS_HYPER RT_BIT(7)
92	/** Used in ring-0 to indicate that we have loaded the hypervisor debug
93	* registers. */
94	#define CPUM_USED_DEBUG_REGS_HYPER RT_BIT(8)
95	/** Used in ring-0 to indicate that we have loaded the guest debug
96	* registers (DR0-3 and maybe DR6) for direct use by the guest.
97	* DR7 (and AMD-V DR6) are handled via the VMCB. */
98	#define CPUM_USED_DEBUG_REGS_GUEST RT_BIT(9)
99
100
101	/** Sync the FPU state on next entry (32->64 switcher only). */
102	#define CPUM_SYNC_FPU_STATE RT_BIT(16)
103	/** Sync the debug state on next entry (32->64 switcher only). */
104	#define CPUM_SYNC_DEBUG_REGS_GUEST RT_BIT(17)
105	/** Sync the debug state on next entry (32->64 switcher only).
106	* Almost the same as CPUM_USE_DEBUG_REGS_HYPER in the raw-mode switchers. */
107	#define CPUM_SYNC_DEBUG_REGS_HYPER RT_BIT(18)
108	/** Host CPU requires fxsave/fxrstor leaky bit handling. */
109	#define CPUM_USE_FFXSR_LEAKY RT_BIT(19)
110	/** Set if the VM supports long-mode. */
111	#define CPUM_USE_SUPPORTS_LONGMODE RT_BIT(20)
112	/** @} */
113
114	/* Sanity check. */
115	#ifndef VBOX_FOR_DTRACE_LIB
116	#if defined(VBOX_WITH_HYBRID_32BIT_KERNEL) && (HC_ARCH_BITS != 32 \|\| R0_ARCH_BITS != 32)
117	# error "VBOX_WITH_HYBRID_32BIT_KERNEL is only for 32 bit builds."
118	#endif
119	#endif
120
121
122	/** @name CPUM Saved State Version.
123	* @{ */
124	/** The current saved state version. */
125	#define CPUM_SAVED_STATE_VERSION 14
126	/** The current saved state version before using SSMR3PutStruct. */
127	#define CPUM_SAVED_STATE_VERSION_MEM 13
128	/** The saved state version before introducing the MSR size field. */
129	#define CPUM_SAVED_STATE_VERSION_NO_MSR_SIZE 12
130	/** The saved state version of 3.2, 3.1 and 3.3 trunk before the hidden
131	* selector register change (CPUM_CHANGED_HIDDEN_SEL_REGS_INVALID). */
132	#define CPUM_SAVED_STATE_VERSION_VER3_2 11
133	/** The saved state version of 3.0 and 3.1 trunk before the teleportation
134	* changes. */
135	#define CPUM_SAVED_STATE_VERSION_VER3_0 10
136	/** The saved state version for the 2.1 trunk before the MSR changes. */
137	#define CPUM_SAVED_STATE_VERSION_VER2_1_NOMSR 9
138	/** The saved state version of 2.0, used for backwards compatibility. */
139	#define CPUM_SAVED_STATE_VERSION_VER2_0 8
140	/** The saved state version of 1.6, used for backwards compatibility. */
141	#define CPUM_SAVED_STATE_VERSION_VER1_6 6
142	/** @} */
143
144
145
146	/**
147	* CPU features and quirks.
148	* This is mostly exploded CPUID info.
149	*/
150	typedef struct CPUMFEATURES
151	{
152	/** The CPU vendor (CPUMCPUVENDOR). */
153	uint8_t enmCpuVendor;
154	/** The CPU family. */
155	uint8_t uFamily;
156	/** The CPU model. */
157	uint8_t uModel;
158	/** The CPU stepping. */
159	uint8_t uStepping;
160	/** The microarchitecture. */
161	#ifndef VBOX_FOR_DTRACE_LIB
162	CPUMMICROARCH enmMicroarch;
163	#else
164	uint32_t enmMicroarch;
165	#endif
166	/** The maximum physical address with of the CPU. */
167	uint8_t cMaxPhysAddrWidth;
168	/** Alignment padding. */
169	uint8_t abPadding[3];
170
171	/** Supports MSRs. */
172	uint32_t fMsr : 1;
173	/** Supports the page size extension (4/2 MB pages). */
174	uint32_t fPse : 1;
175	/** Supports 36-bit page size extension (4 MB pages can map memory above
176	* 4GB). */
177	uint32_t fPse36 : 1;
178	/** Supports physical address extension (PAE). */
179	uint32_t fPae : 1;
180	/** Page attribute table (PAT) support (page level cache control). */
181	uint32_t fPat : 1;
182	/** Supports the FXSAVE and FXRSTOR instructions. */
183	uint32_t fFxSaveRstor : 1;
184	/** Intel SYSENTER/SYSEXIT support */
185	uint32_t fSysEnter : 1;
186	/** First generation APIC. */
187	uint32_t fApic : 1;
188	/** Second generation APIC. */
189	uint32_t fX2Apic : 1;
190	/** Hypervisor present. */
191	uint32_t fHypervisorPresent : 1;
192	/** MWAIT & MONITOR instructions supported. */
193	uint32_t fMonitorMWait : 1;
194	/** MWAIT Extensions present. */
195	uint32_t fMWaitExtensions : 1;
196
197	/** AMD64: Supports long mode. */
198	uint32_t fLongMode : 1;
199	/** AMD64: SYSCALL/SYSRET support. */
200	uint32_t fSysCall : 1;
201	/** AMD64: No-execute page table bit. */
202	uint32_t fNoExecute : 1;
203	/** AMD64: Supports LAHF & SAHF instructions in 64-bit mode. */
204	uint32_t fLahfSahf : 1;
205	/** AMD64: Supports RDTSCP. */
206	uint32_t fRdTscP : 1;
207
208	/** Indicates that FPU instruction and data pointers may leak.
209	* This generally applies to recent AMD CPUs, where the FPU IP and DP pointer
210	* is only saved and restored if an exception is pending. */
211	uint32_t fLeakyFxSR : 1;
212
213	/** Alignment padding. */
214	uint32_t fPadding : 8;
215
216	uint64_t auPadding[2];
217	} CPUMFEATURES;
218	#ifndef VBOX_FOR_DTRACE_LIB
219	AssertCompileSize(CPUMFEATURES, 32);
220	#endif
221	/** Pointer to a CPU feature structure. */
222	typedef CPUMFEATURES *PCPUMFEATURES;
223	/** Pointer to a const CPU feature structure. */
224	typedef CPUMFEATURES const *PCCPUMFEATURES;
225
226
227	/**
228	* CPU info
229	*/
230	typedef struct CPUMINFO
231	{
232	/** The number of MSR ranges (CPUMMSRRANGE) in the array pointed to below. */
233	uint32_t cMsrRanges;
234	/** Mask applied to ECX before looking up the MSR for a RDMSR/WRMSR
235	* instruction. Older hardware has been observed to ignore higher bits. */
236	uint32_t fMsrMask;
237
238	/** The number of CPUID leaves (CPUMCPUIDLEAF) in the array pointed to below. */
239	uint32_t cCpuIdLeaves;
240	/** The index of the first extended CPUID leaf in the array.
241	* Set to cCpuIdLeaves if none present. */
242	uint32_t iFirstExtCpuIdLeaf;
243	/** Alignment padding. */
244	uint32_t uPadding;
245	/** How to handle unknown CPUID leaves. */
246	CPUMUKNOWNCPUID enmUnknownCpuIdMethod;
247	/** For use with CPUMUKNOWNCPUID_DEFAULTS. */
248	CPUMCPUID DefCpuId;
249
250	/** Scalable bus frequency used for reporting other frequencies. */
251	uint64_t uScalableBusFreq;
252
253	/** Pointer to the MSR ranges (ring-0 pointer). */
254	R0PTRTYPE(PCPUMMSRRANGE) paMsrRangesR0;
255	/** Pointer to the CPUID leaves (ring-0 pointer). */
256	R0PTRTYPE(PCPUMCPUIDLEAF) paCpuIdLeavesR0;
257
258	/** Pointer to the MSR ranges (ring-3 pointer). */
259	R3PTRTYPE(PCPUMMSRRANGE) paMsrRangesR3;
260	/** Pointer to the CPUID leaves (ring-3 pointer). */
261	R3PTRTYPE(PCPUMCPUIDLEAF) paCpuIdLeavesR3;
262
263	/** Pointer to the MSR ranges (raw-mode context pointer). */
264	RCPTRTYPE(PCPUMMSRRANGE) paMsrRangesRC;
265	/** Pointer to the CPUID leaves (raw-mode context pointer). */
266	RCPTRTYPE(PCPUMCPUIDLEAF) paCpuIdLeavesRC;
267	} CPUMINFO;
268	/** Pointer to a CPU info structure. */
269	typedef CPUMINFO *PCPUMINFO;
270	/** Pointer to a const CPU info structure. */
271	typedef CPUMINFO const *CPCPUMINFO;
272
273
274	/**
275	* The saved host CPU state.
276	*
277	* @remark The special VBOX_WITH_HYBRID_32BIT_KERNEL checks here are for the 10.4.x series
278	* of Mac OS X where the OS is essentially 32-bit but the cpu mode can be 64-bit.
279	*/
280	typedef struct CPUMHOSTCTX
281	{
282	/** FPU state. (16-byte alignment)
283	* @remark On x86, the format isn't necessarily X86FXSTATE (not important). */
284	X86FXSTATE fpu;
285
286	/** General purpose register, selectors, flags and more
287	* @{ */
288	#if HC_ARCH_BITS == 64 \|\| defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
289	/** General purpose register ++
290	* { */
291	/uint64_t rax; - scratch/
292	uint64_t rbx;
293	/uint64_t rcx; - scratch/
294	/uint64_t rdx; - scratch/
295	uint64_t rdi;
296	uint64_t rsi;
297	uint64_t rbp;
298	uint64_t rsp;
299	/uint64_t r8; - scratch/
300	/uint64_t r9; - scratch/
301	uint64_t r10;
302	uint64_t r11;
303	uint64_t r12;
304	uint64_t r13;
305	uint64_t r14;
306	uint64_t r15;
307	/uint64_t rip; - scratch/
308	uint64_t rflags;
309	#endif
310
311	#if HC_ARCH_BITS == 32
312	/uint32_t eax; - scratch/
313	uint32_t ebx;
314	/uint32_t ecx; - scratch/
315	/uint32_t edx; - scratch/
316	uint32_t edi;
317	uint32_t esi;
318	uint32_t ebp;
319	X86EFLAGS eflags;
320	/uint32_t eip; - scratch/
321	/* lss pair! */
322	uint32_t esp;
323	#endif
324	/** @} */
325
326	/** Selector registers
327	* @{ */
328	RTSEL ss;
329	RTSEL ssPadding;
330	RTSEL gs;
331	RTSEL gsPadding;
332	RTSEL fs;
333	RTSEL fsPadding;
334	RTSEL es;
335	RTSEL esPadding;
336	RTSEL ds;
337	RTSEL dsPadding;
338	RTSEL cs;
339	RTSEL csPadding;
340	/** @} */
341
342	#if HC_ARCH_BITS == 32 && !defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
343	/** Control registers.
344	* @{ */
345	uint32_t cr0;
346	/uint32_t cr2; - scratch/
347	uint32_t cr3;
348	uint32_t cr4;
349	/** @} */
350
351	/** Debug registers.
352	* @{ */
353	uint32_t dr0;
354	uint32_t dr1;
355	uint32_t dr2;
356	uint32_t dr3;
357	uint32_t dr6;
358	uint32_t dr7;
359	/** @} */
360
361	/** Global Descriptor Table register. */
362	X86XDTR32 gdtr;
363	uint16_t gdtrPadding;
364	/** Interrupt Descriptor Table register. */
365	X86XDTR32 idtr;
366	uint16_t idtrPadding;
367	/** The task register. */
368	RTSEL ldtr;
369	RTSEL ldtrPadding;
370	/** The task register. */
371	RTSEL tr;
372	RTSEL trPadding;
373	uint32_t SysEnterPadding;
374
375	/** The sysenter msr registers.
376	* This member is not used by the hypervisor context. */
377	CPUMSYSENTER SysEnter;
378
379	/** MSRs
380	* @{ */
381	uint64_t efer;
382	/** @} */
383
384	/* padding to get 64byte aligned size */
385	uint8_t auPadding[16+32];
386
387	#elif HC_ARCH_BITS == 64 \|\| defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
388
389	/** Control registers.
390	* @{ */
391	uint64_t cr0;
392	/uint64_t cr2; - scratch/
393	uint64_t cr3;
394	uint64_t cr4;
395	uint64_t cr8;
396	/** @} */
397
398	/** Debug registers.
399	* @{ */
400	uint64_t dr0;
401	uint64_t dr1;
402	uint64_t dr2;
403	uint64_t dr3;
404	uint64_t dr6;
405	uint64_t dr7;
406	/** @} */
407
408	/** Global Descriptor Table register. */
409	X86XDTR64 gdtr;
410	uint16_t gdtrPadding;
411	/** Interrupt Descriptor Table register. */
412	X86XDTR64 idtr;
413	uint16_t idtrPadding;
414	/** The task register. */
415	RTSEL ldtr;
416	RTSEL ldtrPadding;
417	/** The task register. */
418	RTSEL tr;
419	RTSEL trPadding;
420
421	/** MSRs
422	* @{ */
423	CPUMSYSENTER SysEnter;
424	uint64_t FSbase;
425	uint64_t GSbase;
426	uint64_t efer;
427	/** @} */
428
429	/* padding to get 32byte aligned size */
430	# ifdef VBOX_WITH_HYBRID_32BIT_KERNEL
431	uint8_t auPadding[16];
432	# else
433	uint8_t auPadding[8+32];
434	# endif
435
436	#else
437	# error HC_ARCH_BITS not defined
438	#endif
439	} CPUMHOSTCTX;
440	/** Pointer to the saved host CPU state. */
441	typedef CPUMHOSTCTX *PCPUMHOSTCTX;
442
443
444	/**
445	* CPUM Data (part of VM)
446	*/
447	typedef struct CPUM
448	{
449	/** Offset from CPUM to CPUMCPU for the first CPU. */
450	uint32_t offCPUMCPU0;
451
452	/** Use flags.
453	* These flags indicates which CPU features the host uses.
454	*/
455	uint32_t fHostUseFlags;
456
457	/** Host CPU Features - ECX */
458	struct
459	{
460	/** edx part */
461	X86CPUIDFEATEDX edx;
462	/** ecx part */
463	X86CPUIDFEATECX ecx;
464	} CPUFeatures;
465	/** Host extended CPU features. */
466	struct
467	{
468	/** edx part */
469	uint32_t edx;
470	/** ecx part */
471	uint32_t ecx;
472	} CPUFeaturesExt;
473
474	/** CR4 mask */
475	struct
476	{
477	uint32_t AndMask; /*< @todo Move these to the per-CPU structure and fix the switchers. Saves a register! /
478	uint32_t OrMask;
479	} CR4;
480
481	/** The (more) portable CPUID level. */
482	uint8_t u8PortableCpuIdLevel;
483	/** Indicates that a state restore is pending.
484	* This is used to verify load order dependencies (PGM). */
485	bool fPendingRestore;
486	uint8_t abPadding[HC_ARCH_BITS == 64 ? 6 : 2];
487
488	/** The standard set of CpuId leaves. */
489	CPUMCPUID aGuestCpuIdPatmStd[6];
490	/** The extended set of CpuId leaves. */
491	CPUMCPUID aGuestCpuIdPatmExt[10];
492	/** The centaur set of CpuId leaves. */
493	CPUMCPUID aGuestCpuIdPatmCentaur[4];
494	/** The default set of CpuId leaves. */
495	CPUMCPUID GuestCpuIdPatmDef;
496
497	#if HC_ARCH_BITS == 32
498	uint8_t abPadding2[4];
499	#endif
500
501	/** Guest CPU info. */
502	CPUMINFO GuestInfo;
503	/** Guest CPU feature information. */
504	CPUMFEATURES GuestFeatures;
505	/** Host CPU feature information. */
506	CPUMFEATURES HostFeatures;
507
508	/** @name MSR statistics.
509	* @{ */
510	STAMCOUNTER cMsrWrites;
511	STAMCOUNTER cMsrWritesToIgnoredBits;
512	STAMCOUNTER cMsrWritesRaiseGp;
513	STAMCOUNTER cMsrWritesUnknown;
514	STAMCOUNTER cMsrReads;
515	STAMCOUNTER cMsrReadsRaiseGp;
516	STAMCOUNTER cMsrReadsUnknown;
517	/** @} */
518	} CPUM;
519	/** Pointer to the CPUM instance data residing in the shared VM structure. */
520	typedef CPUM *PCPUM;
521
522	/**
523	* CPUM Data (part of VMCPU)
524	*/
525	typedef struct CPUMCPU
526	{
527	/**
528	* Hypervisor context.
529	* Aligned on a 64-byte boundary.
530	*/
531	CPUMCTX Hyper;
532
533	/**
534	* Saved host context. Only valid while inside GC.
535	* Aligned on a 64-byte boundary.
536	*/
537	CPUMHOSTCTX Host;
538
539	#ifdef VBOX_WITH_CRASHDUMP_MAGIC
540	uint8_t aMagic[56];
541	uint64_t uMagic;
542	#endif
543
544	/**
545	* Guest context.
546	* Aligned on a 64-byte boundary.
547	*/
548	CPUMCTX Guest;
549
550	/**
551	* Guest context - misc MSRs
552	* Aligned on a 64-byte boundary.
553	*/
554	CPUMCTXMSRS GuestMsrs;
555
556	/** Use flags.
557	* These flags indicates both what is to be used and what has been used.
558	*/
559	uint32_t fUseFlags;
560
561	/** Changed flags.
562	* These flags indicates to REM (and others) which important guest
563	* registers which has been changed since last time the flags were cleared.
564	* See the CPUM_CHANGED_* defines for what we keep track of.
565	*/
566	uint32_t fChanged;
567
568	/** Offset from CPUM to CPUMCPU. */
569	uint32_t offCPUM;
570
571	/** Temporary storage for the return code of the function called in the
572	* 32-64 switcher. */
573	uint32_t u32RetCode;
574
575	#ifdef VBOX_WITH_VMMR0_DISABLE_LAPIC_NMI
576	/** The address of the APIC mapping, NULL if no APIC.
577	* Call CPUMR0SetLApic to update this before doing a world switch. */
578	RTHCPTR pvApicBase;
579	/** Used by the world switcher code to store which vectors needs restoring on
580	* the way back. */
581	uint32_t fApicDisVectors;
582	/** Set if the CPU has the X2APIC mode enabled.
583	* Call CPUMR0SetLApic to update this before doing a world switch. */
584	bool fX2Apic;
585	#else
586	uint8_t abPadding3[(HC_ARCH_BITS == 64 ? 8 : 4) + 4 + 1];
587	#endif
588
589	/** Have we entered raw-mode? */
590	bool fRawEntered;
591	/** Have we entered the recompiler? */
592	bool fRemEntered;
593
594	/** Align the structure on a 64-byte boundary. */
595	uint8_t abPadding2[64 - 16 - (HC_ARCH_BITS == 64 ? 8 : 4) - 4 - 1 - 2];
596	} CPUMCPU;
597	/** Pointer to the CPUMCPU instance data residing in the shared VMCPU structure. */
598	typedef CPUMCPU *PCPUMCPU;
599
600	#ifndef VBOX_FOR_DTRACE_LIB
601	RT_C_DECLS_BEGIN
602
603	PCPUMCPUIDLEAF cpumCpuIdGetLeaf(PVM pVM, uint32_t uLeaf, uint32_t uSubLeaf);
604
605	#ifdef IN_RING3
606	int cpumR3DbgInit(PVM pVM);
607	PCPUMCPUIDLEAF cpumR3CpuIdGetLeaf(PCPUMCPUIDLEAF paLeaves, uint32_t cLeaves, uint32_t uLeaf, uint32_t uSubLeaf);
608	bool cpumR3CpuIdGetLeafLegacy(PCPUMCPUIDLEAF paLeaves, uint32_t cLeaves, uint32_t uLeaf, uint32_t uSubLeaf,
609	PCPUMCPUID pLeagcy);
610	int cpumR3CpuIdInsert(PVM pVM, PCPUMCPUIDLEAF ppaLeaves, uint32_t pcLeaves, PCPUMCPUIDLEAF pNewLeaf);
611	void cpumR3CpuIdRemoveRange(PCPUMCPUIDLEAF paLeaves, uint32_t *pcLeaves, uint32_t uFirst, uint32_t uLast);
612	int cpumR3CpuIdExplodeFeatures(PCCPUMCPUIDLEAF paLeaves, uint32_t cLeaves, PCPUMFEATURES pFeatures);
613	int cpumR3CpuIdInit(PVM pVM);
614	void cpumR3SaveCpuId(PVM pVM, PSSMHANDLE pSSM);
615	int cpumR3LoadCpuId(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion);
616
617	int cpumR3DbGetCpuInfo(const char *pszName, PCPUMINFO pInfo);
618	int cpumR3MsrRangesInsert(PVM pVM, PCPUMMSRRANGE ppaMsrRanges, uint32_t pcMsrRanges, PCCPUMMSRRANGE pNewRange);
619	int cpumR3MsrApplyFudge(PVM pVM);
620	int cpumR3MsrRegStats(PVM pVM);
621	int cpumR3MsrStrictInitChecks(void);
622	PCPUMMSRRANGE cpumLookupMsrRange(PVM pVM, uint32_t idMsr);
623	#endif
624
625	#ifdef IN_RC
626	DECLASM(int) cpumHandleLazyFPUAsm(PCPUMCPU pCPUM);
627	#endif
628
629	#ifdef IN_RING0
630	DECLASM(int) cpumR0SaveHostRestoreGuestFPUState(PCPUMCPU pCPUM);
631	DECLASM(int) cpumR0SaveGuestRestoreHostFPUState(PCPUMCPU pCPUM);
632	DECLASM(int) cpumR0SaveHostFPUState(PCPUMCPU pCPUM);
633	DECLASM(int) cpumR0RestoreHostFPUState(PCPUMCPU pCPUM);
634	DECLASM(void) cpumR0LoadFPU(PCPUMCTX pCtx);
635	DECLASM(void) cpumR0SaveFPU(PCPUMCTX pCtx);
636	DECLASM(void) cpumR0LoadXMM(PCPUMCTX pCtx);
637	DECLASM(void) cpumR0SaveXMM(PCPUMCTX pCtx);
638	DECLASM(void) cpumR0SetFCW(uint16_t u16FCW);
639	DECLASM(uint16_t) cpumR0GetFCW(void);
640	DECLASM(void) cpumR0SetMXCSR(uint32_t u32MXCSR);
641	DECLASM(uint32_t) cpumR0GetMXCSR(void);
642	DECLASM(void) cpumR0LoadDRx(uint64_t const *pa4Regs);
643	DECLASM(void) cpumR0SaveDRx(uint64_t *pa4Regs);
644	#endif
645
646	RT_C_DECLS_END
647	#endif /* !VBOX_FOR_DTRACE_LIB */
648
649	/** @} */
650
651	#endif
652

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source: vbox/trunk/src/VBox/VMM/include/CPUMInternal.h@ 54733

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