CPUMInternal.h@ 55049

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1	/* $Id: CPUMInternal.h 55049 2015-03-31 19:01:36Z vboxsync $ */
2	/** @file
3	* CPUM - Internal header file.
4	*/
5
6	/*
7	* Copyright (C) 2006-2015 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*/
17
18	#ifndef ___CPUMInternal_h
19	#define ___CPUMInternal_h
20
21	#ifndef VBOX_FOR_DTRACE_LIB
22	# include <VBox/cdefs.h>
23	# include <VBox/types.h>
24	# include <VBox/vmm/stam.h>
25	# include <iprt/x86.h>
26	#else
27	# pragma D depends_on library x86.d
28	# pragma D depends_on library cpumctx.d
29
30	/* Some fudging. */
31	typedef uint32_t CPUMMICROARCH;
32	typedef uint32_t CPUMUNKNOWNCPUID;
33	typedef struct CPUMCPUIDLEAF *PCPUMCPUIDLEAF;
34	typedef struct CPUMMSRRANGE *PCPUMMSRRANGE;
35	typedef uint64_t STAMCOUNTER;
36	#endif
37
38
39
40
41	/** @defgroup grp_cpum_int Internals
42	* @ingroup grp_cpum
43	* @internal
44	* @{
45	*/
46
47	/** Flags and types for CPUM fault handlers
48	* @{ */
49	/** Type: Load DS */
50	#define CPUM_HANDLER_DS 1
51	/** Type: Load ES */
52	#define CPUM_HANDLER_ES 2
53	/** Type: Load FS */
54	#define CPUM_HANDLER_FS 3
55	/** Type: Load GS */
56	#define CPUM_HANDLER_GS 4
57	/** Type: IRET */
58	#define CPUM_HANDLER_IRET 5
59	/** Type mask. */
60	#define CPUM_HANDLER_TYPEMASK 0xff
61	/** If set EBP points to the CPUMCTXCORE that's being used. */
62	#define CPUM_HANDLER_CTXCORE_IN_EBP RT_BIT(31)
63	/** @} */
64
65
66	/** Use flags (CPUM::fUseFlags).
67	* (Don't forget to sync this with CPUMInternal.mac !)
68	* @{ */
69	/** Used the FPU, SSE or such stuff. */
70	#define CPUM_USED_FPU RT_BIT(0)
71	/** Used the FPU, SSE or such stuff since last we were in REM.
72	* REM syncing is clearing this, lazy FPU is setting it. */
73	#define CPUM_USED_FPU_SINCE_REM RT_BIT(1)
74	/** The XMM state was manually restored. (AMD only) */
75	#define CPUM_USED_MANUAL_XMM_RESTORE RT_BIT(2)
76
77	/** Host OS is using SYSENTER and we must NULL the CS. */
78	#define CPUM_USE_SYSENTER RT_BIT(3)
79	/** Host OS is using SYSENTER and we must NULL the CS. */
80	#define CPUM_USE_SYSCALL RT_BIT(4)
81
82	/** Debug registers are used by host and that DR7 and DR6 must be saved and
83	* disabled when switching to raw-mode. */
84	#define CPUM_USE_DEBUG_REGS_HOST RT_BIT(5)
85	/** Records that we've saved the host DRx registers.
86	* In ring-0 this means all (DR0-7), while in raw-mode context this means DR0-3
87	* since DR6 and DR7 are covered by CPUM_USE_DEBUG_REGS_HOST. */
88	#define CPUM_USED_DEBUG_REGS_HOST RT_BIT(6)
89	/** Set to indicate that we should save host DR0-7 and load the hypervisor debug
90	* registers in the raw-mode world switchers. (See CPUMRecalcHyperDRx.) */
91	#define CPUM_USE_DEBUG_REGS_HYPER RT_BIT(7)
92	/** Used in ring-0 to indicate that we have loaded the hypervisor debug
93	* registers. */
94	#define CPUM_USED_DEBUG_REGS_HYPER RT_BIT(8)
95	/** Used in ring-0 to indicate that we have loaded the guest debug
96	* registers (DR0-3 and maybe DR6) for direct use by the guest.
97	* DR7 (and AMD-V DR6) are handled via the VMCB. */
98	#define CPUM_USED_DEBUG_REGS_GUEST RT_BIT(9)
99
100
101	/** Sync the FPU state on next entry (32->64 switcher only). */
102	#define CPUM_SYNC_FPU_STATE RT_BIT(16)
103	/** Sync the debug state on next entry (32->64 switcher only). */
104	#define CPUM_SYNC_DEBUG_REGS_GUEST RT_BIT(17)
105	/** Sync the debug state on next entry (32->64 switcher only).
106	* Almost the same as CPUM_USE_DEBUG_REGS_HYPER in the raw-mode switchers. */
107	#define CPUM_SYNC_DEBUG_REGS_HYPER RT_BIT(18)
108	/** Host CPU requires fxsave/fxrstor leaky bit handling. */
109	#define CPUM_USE_FFXSR_LEAKY RT_BIT(19)
110	/** Set if the VM supports long-mode. */
111	#define CPUM_USE_SUPPORTS_LONGMODE RT_BIT(20)
112	/** @} */
113
114	/* Sanity check. */
115	#ifndef VBOX_FOR_DTRACE_LIB
116	#if defined(VBOX_WITH_HYBRID_32BIT_KERNEL) && (HC_ARCH_BITS != 32 \|\| R0_ARCH_BITS != 32)
117	# error "VBOX_WITH_HYBRID_32BIT_KERNEL is only for 32 bit builds."
118	#endif
119	#endif
120
121
122	/** @name CPUM Saved State Version.
123	* @{ */
124	/** The current saved state version. */
125	#define CPUM_SAVED_STATE_VERSION 16
126	/** CPUID changes with explode forgetting to update the leaf count on
127	* restore, resulting in garbage being saved restoring+saving old states). */
128	#define CPUM_SAVED_STATE_VERSION_BAD_CPUID_COUNT 15
129	/** The saved state version before the CPUIDs changes. */
130	#define CPUM_SAVED_STATE_VERSION_PUT_STRUCT 14
131	/** The saved state version before using SSMR3PutStruct. */
132	#define CPUM_SAVED_STATE_VERSION_MEM 13
133	/** The saved state version before introducing the MSR size field. */
134	#define CPUM_SAVED_STATE_VERSION_NO_MSR_SIZE 12
135	/** The saved state version of 3.2, 3.1 and 3.3 trunk before the hidden
136	* selector register change (CPUM_CHANGED_HIDDEN_SEL_REGS_INVALID). */
137	#define CPUM_SAVED_STATE_VERSION_VER3_2 11
138	/** The saved state version of 3.0 and 3.1 trunk before the teleportation
139	* changes. */
140	#define CPUM_SAVED_STATE_VERSION_VER3_0 10
141	/** The saved state version for the 2.1 trunk before the MSR changes. */
142	#define CPUM_SAVED_STATE_VERSION_VER2_1_NOMSR 9
143	/** The saved state version of 2.0, used for backwards compatibility. */
144	#define CPUM_SAVED_STATE_VERSION_VER2_0 8
145	/** The saved state version of 1.6, used for backwards compatibility. */
146	#define CPUM_SAVED_STATE_VERSION_VER1_6 6
147	/** @} */
148
149
150
151	/**
152	* CPU features and quirks.
153	* This is mostly exploded CPUID info.
154	*/
155	typedef struct CPUMFEATURES
156	{
157	/** The CPU vendor (CPUMCPUVENDOR). */
158	uint8_t enmCpuVendor;
159	/** The CPU family. */
160	uint8_t uFamily;
161	/** The CPU model. */
162	uint8_t uModel;
163	/** The CPU stepping. */
164	uint8_t uStepping;
165	/** The microarchitecture. */
166	#ifndef VBOX_FOR_DTRACE_LIB
167	CPUMMICROARCH enmMicroarch;
168	#else
169	uint32_t enmMicroarch;
170	#endif
171	/** The maximum physical address with of the CPU. */
172	uint8_t cMaxPhysAddrWidth;
173	/** Alignment padding. */
174	uint8_t abPadding[3];
175
176	/** Supports MSRs. */
177	uint32_t fMsr : 1;
178	/** Supports the page size extension (4/2 MB pages). */
179	uint32_t fPse : 1;
180	/** Supports 36-bit page size extension (4 MB pages can map memory above
181	* 4GB). */
182	uint32_t fPse36 : 1;
183	/** Supports physical address extension (PAE). */
184	uint32_t fPae : 1;
185	/** Page attribute table (PAT) support (page level cache control). */
186	uint32_t fPat : 1;
187	/** Supports the FXSAVE and FXRSTOR instructions. */
188	uint32_t fFxSaveRstor : 1;
189	/** Intel SYSENTER/SYSEXIT support */
190	uint32_t fSysEnter : 1;
191	/** First generation APIC. */
192	uint32_t fApic : 1;
193	/** Second generation APIC. */
194	uint32_t fX2Apic : 1;
195	/** Hypervisor present. */
196	uint32_t fHypervisorPresent : 1;
197	/** MWAIT & MONITOR instructions supported. */
198	uint32_t fMonitorMWait : 1;
199	/** MWAIT Extensions present. */
200	uint32_t fMWaitExtensions : 1;
201
202	/** AMD64: Supports long mode. */
203	uint32_t fLongMode : 1;
204	/** AMD64: SYSCALL/SYSRET support. */
205	uint32_t fSysCall : 1;
206	/** AMD64: No-execute page table bit. */
207	uint32_t fNoExecute : 1;
208	/** AMD64: Supports LAHF & SAHF instructions in 64-bit mode. */
209	uint32_t fLahfSahf : 1;
210	/** AMD64: Supports RDTSCP. */
211	uint32_t fRdTscP : 1;
212
213	/** Indicates that FPU instruction and data pointers may leak.
214	* This generally applies to recent AMD CPUs, where the FPU IP and DP pointer
215	* is only saved and restored if an exception is pending. */
216	uint32_t fLeakyFxSR : 1;
217
218	/** Alignment padding. */
219	uint32_t fPadding : 8;
220
221	uint64_t auPadding[2];
222	} CPUMFEATURES;
223	#ifndef VBOX_FOR_DTRACE_LIB
224	AssertCompileSize(CPUMFEATURES, 32);
225	#endif
226	/** Pointer to a CPU feature structure. */
227	typedef CPUMFEATURES *PCPUMFEATURES;
228	/** Pointer to a const CPU feature structure. */
229	typedef CPUMFEATURES const *PCCPUMFEATURES;
230
231
232	/**
233	* CPU info
234	*/
235	typedef struct CPUMINFO
236	{
237	/** The number of MSR ranges (CPUMMSRRANGE) in the array pointed to below. */
238	uint32_t cMsrRanges;
239	/** Mask applied to ECX before looking up the MSR for a RDMSR/WRMSR
240	* instruction. Older hardware has been observed to ignore higher bits. */
241	uint32_t fMsrMask;
242
243	/** The number of CPUID leaves (CPUMCPUIDLEAF) in the array pointed to below. */
244	uint32_t cCpuIdLeaves;
245	/** The index of the first extended CPUID leaf in the array.
246	* Set to cCpuIdLeaves if none present. */
247	uint32_t iFirstExtCpuIdLeaf;
248	/** Alignment padding. */
249	uint32_t uPadding;
250	/** How to handle unknown CPUID leaves. */
251	CPUMUNKNOWNCPUID enmUnknownCpuIdMethod;
252	/** For use with CPUMUNKNOWNCPUID_DEFAULTS (DB & VM),
253	* CPUMUNKNOWNCPUID_LAST_STD_LEAF (VM) and CPUMUNKNOWNCPUID_LAST_STD_LEAF_WITH_ECX (VM). */
254	CPUMCPUID DefCpuId;
255
256	/** Scalable bus frequency used for reporting other frequencies. */
257	uint64_t uScalableBusFreq;
258
259	/** Pointer to the MSR ranges (ring-0 pointer). */
260	R0PTRTYPE(PCPUMMSRRANGE) paMsrRangesR0;
261	/** Pointer to the CPUID leaves (ring-0 pointer). */
262	R0PTRTYPE(PCPUMCPUIDLEAF) paCpuIdLeavesR0;
263
264	/** Pointer to the MSR ranges (ring-3 pointer). */
265	R3PTRTYPE(PCPUMMSRRANGE) paMsrRangesR3;
266	/** Pointer to the CPUID leaves (ring-3 pointer). */
267	R3PTRTYPE(PCPUMCPUIDLEAF) paCpuIdLeavesR3;
268
269	/** Pointer to the MSR ranges (raw-mode context pointer). */
270	RCPTRTYPE(PCPUMMSRRANGE) paMsrRangesRC;
271	/** Pointer to the CPUID leaves (raw-mode context pointer). */
272	RCPTRTYPE(PCPUMCPUIDLEAF) paCpuIdLeavesRC;
273	} CPUMINFO;
274	/** Pointer to a CPU info structure. */
275	typedef CPUMINFO *PCPUMINFO;
276	/** Pointer to a const CPU info structure. */
277	typedef CPUMINFO const *CPCPUMINFO;
278
279
280	/**
281	* The saved host CPU state.
282	*
283	* @remark The special VBOX_WITH_HYBRID_32BIT_KERNEL checks here are for the 10.4.x series
284	* of Mac OS X where the OS is essentially 32-bit but the cpu mode can be 64-bit.
285	*/
286	typedef struct CPUMHOSTCTX
287	{
288	/** General purpose register, selectors, flags and more
289	* @{ */
290	#if HC_ARCH_BITS == 64 \|\| defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
291	/** General purpose register ++
292	* { */
293	/uint64_t rax; - scratch/
294	uint64_t rbx;
295	/uint64_t rcx; - scratch/
296	/uint64_t rdx; - scratch/
297	uint64_t rdi;
298	uint64_t rsi;
299	uint64_t rbp;
300	uint64_t rsp;
301	/uint64_t r8; - scratch/
302	/uint64_t r9; - scratch/
303	uint64_t r10;
304	uint64_t r11;
305	uint64_t r12;
306	uint64_t r13;
307	uint64_t r14;
308	uint64_t r15;
309	/uint64_t rip; - scratch/
310	uint64_t rflags;
311	#endif
312
313	#if HC_ARCH_BITS == 32
314	/uint32_t eax; - scratch/
315	uint32_t ebx;
316	/uint32_t ecx; - scratch/
317	/uint32_t edx; - scratch/
318	uint32_t edi;
319	uint32_t esi;
320	uint32_t ebp;
321	X86EFLAGS eflags;
322	/uint32_t eip; - scratch/
323	/* lss pair! */
324	uint32_t esp;
325	#endif
326	/** @} */
327
328	/** Selector registers
329	* @{ */
330	RTSEL ss;
331	RTSEL ssPadding;
332	RTSEL gs;
333	RTSEL gsPadding;
334	RTSEL fs;
335	RTSEL fsPadding;
336	RTSEL es;
337	RTSEL esPadding;
338	RTSEL ds;
339	RTSEL dsPadding;
340	RTSEL cs;
341	RTSEL csPadding;
342	/** @} */
343
344	#if HC_ARCH_BITS == 32 && !defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
345	/** Control registers.
346	* @{ */
347	uint32_t cr0;
348	/uint32_t cr2; - scratch/
349	uint32_t cr3;
350	uint32_t cr4;
351	/** @} */
352
353	/** Debug registers.
354	* @{ */
355	uint32_t dr0;
356	uint32_t dr1;
357	uint32_t dr2;
358	uint32_t dr3;
359	uint32_t dr6;
360	uint32_t dr7;
361	/** @} */
362
363	/** Global Descriptor Table register. */
364	X86XDTR32 gdtr;
365	uint16_t gdtrPadding;
366	/** Interrupt Descriptor Table register. */
367	X86XDTR32 idtr;
368	uint16_t idtrPadding;
369	/** The task register. */
370	RTSEL ldtr;
371	RTSEL ldtrPadding;
372	/** The task register. */
373	RTSEL tr;
374	RTSEL trPadding;
375	uint32_t SysEnterPadding;
376
377	/** The sysenter msr registers.
378	* This member is not used by the hypervisor context. */
379	CPUMSYSENTER SysEnter;
380
381	/** MSRs
382	* @{ */
383	uint64_t efer;
384	/** @} */
385
386	/* padding to get 64byte aligned size */
387	uint8_t auPadding[16+20];
388
389	#elif HC_ARCH_BITS == 64 \|\| defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
390
391	/** Control registers.
392	* @{ */
393	uint64_t cr0;
394	/uint64_t cr2; - scratch/
395	uint64_t cr3;
396	uint64_t cr4;
397	uint64_t cr8;
398	/** @} */
399
400	/** Debug registers.
401	* @{ */
402	uint64_t dr0;
403	uint64_t dr1;
404	uint64_t dr2;
405	uint64_t dr3;
406	uint64_t dr6;
407	uint64_t dr7;
408	/** @} */
409
410	/** Global Descriptor Table register. */
411	X86XDTR64 gdtr;
412	uint16_t gdtrPadding;
413	/** Interrupt Descriptor Table register. */
414	X86XDTR64 idtr;
415	uint16_t idtrPadding;
416	/** The task register. */
417	RTSEL ldtr;
418	RTSEL ldtrPadding;
419	/** The task register. */
420	RTSEL tr;
421	RTSEL trPadding;
422
423	/** MSRs
424	* @{ */
425	CPUMSYSENTER SysEnter;
426	uint64_t FSbase;
427	uint64_t GSbase;
428	uint64_t efer;
429	/** @} */
430
431	/* padding to get 32byte aligned size */
432	# ifdef VBOX_WITH_HYBRID_32BIT_KERNEL
433	uint8_t auPadding[4];
434	# else
435	uint8_t auPadding[8+12];
436	# endif
437
438	#else
439	# error HC_ARCH_BITS not defined
440	#endif
441
442	/** Pointer to the FPU/SSE/AVX/XXXX state raw-mode mapping. */
443	RCPTRTYPE(PX86XSAVEAREA) pXStateRC;
444	/** Pointer to the FPU/SSE/AVX/XXXX state ring-0 mapping. */
445	R0PTRTYPE(PX86XSAVEAREA) pXStateR0;
446	/** Pointer to the FPU/SSE/AVX/XXXX state ring-3 mapping. */
447	R3PTRTYPE(PX86XSAVEAREA) pXStateR3;
448	} CPUMHOSTCTX;
449	AssertCompileSizeAlignment(CPUMHOSTCTX, 64);
450	/** Pointer to the saved host CPU state. */
451	typedef CPUMHOSTCTX *PCPUMHOSTCTX;
452
453
454	/**
455	* CPUM Data (part of VM)
456	*/
457	typedef struct CPUM
458	{
459	/** Offset from CPUM to CPUMCPU for the first CPU. */
460	uint32_t offCPUMCPU0;
461
462	/** Use flags.
463	* These flags indicates which CPU features the host uses.
464	*/
465	uint32_t fHostUseFlags;
466
467	/** Host CPU Features - ECX */
468	struct
469	{
470	/** edx part */
471	X86CPUIDFEATEDX edx;
472	/** ecx part */
473	X86CPUIDFEATECX ecx;
474	} CPUFeatures;
475	/** Host extended CPU features. */
476	struct
477	{
478	/** edx part */
479	uint32_t edx;
480	/** ecx part */
481	uint32_t ecx;
482	} CPUFeaturesExt;
483
484	/** CR4 mask */
485	struct
486	{
487	uint32_t AndMask; /*< @todo Move these to the per-CPU structure and fix the switchers. Saves a register! /
488	uint32_t OrMask;
489	} CR4;
490
491	/** The (more) portable CPUID level. */
492	uint8_t u8PortableCpuIdLevel;
493	/** Indicates that a state restore is pending.
494	* This is used to verify load order dependencies (PGM). */
495	bool fPendingRestore;
496	uint8_t abPadding[HC_ARCH_BITS == 64 ? 6 : 2];
497
498	/** The standard set of CpuId leaves. */
499	CPUMCPUID aGuestCpuIdPatmStd[6];
500	/** The extended set of CpuId leaves. */
501	CPUMCPUID aGuestCpuIdPatmExt[10];
502	/** The centaur set of CpuId leaves. */
503	CPUMCPUID aGuestCpuIdPatmCentaur[4];
504
505	#if HC_ARCH_BITS == 32
506	uint8_t abPadding2[4];
507	#endif
508
509	/** Guest CPU info. */
510	CPUMINFO GuestInfo;
511	/** Guest CPU feature information. */
512	CPUMFEATURES GuestFeatures;
513	/** Host CPU feature information. */
514	CPUMFEATURES HostFeatures;
515
516	/** @name MSR statistics.
517	* @{ */
518	STAMCOUNTER cMsrWrites;
519	STAMCOUNTER cMsrWritesToIgnoredBits;
520	STAMCOUNTER cMsrWritesRaiseGp;
521	STAMCOUNTER cMsrWritesUnknown;
522	STAMCOUNTER cMsrReads;
523	STAMCOUNTER cMsrReadsRaiseGp;
524	STAMCOUNTER cMsrReadsUnknown;
525	/** @} */
526	} CPUM;
527	/** Pointer to the CPUM instance data residing in the shared VM structure. */
528	typedef CPUM *PCPUM;
529
530	/**
531	* CPUM Data (part of VMCPU)
532	*/
533	typedef struct CPUMCPU
534	{
535	/**
536	* Guest context.
537	* Aligned on a 64-byte boundary.
538	*/
539	CPUMCTX Guest;
540
541	/**
542	* Guest context - misc MSRs
543	* Aligned on a 64-byte boundary.
544	*/
545	CPUMCTXMSRS GuestMsrs;
546
547	/** Use flags.
548	* These flags indicates both what is to be used and what has been used.
549	*/
550	uint32_t fUseFlags;
551
552	/** Changed flags.
553	* These flags indicates to REM (and others) which important guest
554	* registers which has been changed since last time the flags were cleared.
555	* See the CPUM_CHANGED_* defines for what we keep track of.
556	*/
557	uint32_t fChanged;
558
559	/** Offset from CPUM to CPUMCPU. */
560	uint32_t offCPUM;
561
562	/** Temporary storage for the return code of the function called in the
563	* 32-64 switcher. */
564	uint32_t u32RetCode;
565
566	#ifdef VBOX_WITH_VMMR0_DISABLE_LAPIC_NMI
567	/** The address of the APIC mapping, NULL if no APIC.
568	* Call CPUMR0SetLApic to update this before doing a world switch. */
569	RTHCPTR pvApicBase;
570	/** Used by the world switcher code to store which vectors needs restoring on
571	* the way back. */
572	uint32_t fApicDisVectors;
573	/** Set if the CPU has the X2APIC mode enabled.
574	* Call CPUMR0SetLApic to update this before doing a world switch. */
575	bool fX2Apic;
576	#else
577	uint8_t abPadding3[(HC_ARCH_BITS == 64 ? 8 : 4) + 4 + 1];
578	#endif
579
580	/** Have we entered raw-mode? */
581	bool fRawEntered;
582	/** Have we entered the recompiler? */
583	bool fRemEntered;
584
585	/** Align the next member on a 64-bit boundrary. */
586	uint8_t abPadding2[64 - 16 - (HC_ARCH_BITS == 64 ? 8 : 4) - 4 - 1 - 2];
587
588	/** Saved host context. Only valid while inside RC or HM contexts.
589	* Must be aligned on a 64-byte boundary. */
590	CPUMHOSTCTX Host;
591	/** Hypervisor context. Must be aligned on a 64-byte boundary. */
592	CPUMCTX Hyper;
593
594	#ifdef VBOX_WITH_CRASHDUMP_MAGIC
595	uint8_t aMagic[56];
596	uint64_t uMagic;
597	#endif
598	} CPUMCPU;
599	/** Pointer to the CPUMCPU instance data residing in the shared VMCPU structure. */
600	typedef CPUMCPU *PCPUMCPU;
601
602	#ifndef VBOX_FOR_DTRACE_LIB
603	RT_C_DECLS_BEGIN
604
605	PCPUMCPUIDLEAF cpumCpuIdGetLeaf(PVM pVM, uint32_t uLeaf);
606	PCPUMCPUIDLEAF cpumCpuIdGetLeafEx(PVM pVM, uint32_t uLeaf, uint32_t uSubLeaf, bool *pfExactSubLeafHit);
607
608	#ifdef IN_RING3
609	int cpumR3DbgInit(PVM pVM);
610	int cpumR3CpuIdExplodeFeatures(PCCPUMCPUIDLEAF paLeaves, uint32_t cLeaves, PCPUMFEATURES pFeatures);
611	int cpumR3InitCpuIdAndMsrs(PVM pVM);
612	void cpumR3SaveCpuId(PVM pVM, PSSMHANDLE pSSM);
613	int cpumR3LoadCpuId(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion);
614	DECLCALLBACK(void) cpumR3CpuIdInfo(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
615
616	int cpumR3DbGetCpuInfo(const char *pszName, PCPUMINFO pInfo);
617	int cpumR3MsrRangesInsert(PVM pVM, PCPUMMSRRANGE ppaMsrRanges, uint32_t pcMsrRanges, PCCPUMMSRRANGE pNewRange);
618	int cpumR3MsrApplyFudge(PVM pVM);
619	int cpumR3MsrRegStats(PVM pVM);
620	int cpumR3MsrStrictInitChecks(void);
621	PCPUMMSRRANGE cpumLookupMsrRange(PVM pVM, uint32_t idMsr);
622	#endif
623
624	#ifdef IN_RC
625	DECLASM(int) cpumHandleLazyFPUAsm(PCPUMCPU pCPUM);
626	#endif
627
628	#ifdef IN_RING0
629	DECLASM(int) cpumR0SaveHostRestoreGuestFPUState(PCPUMCPU pCPUM);
630	DECLASM(int) cpumR0SaveGuestRestoreHostFPUState(PCPUMCPU pCPUM);
631	DECLASM(int) cpumR0SaveHostFPUState(PCPUMCPU pCPUM);
632	DECLASM(int) cpumR0RestoreHostFPUState(PCPUMCPU pCPUM);
633	DECLASM(void) cpumR0LoadFPU(PCPUMCTX pCtx);
634	DECLASM(void) cpumR0SaveFPU(PCPUMCTX pCtx);
635	DECLASM(void) cpumR0LoadXMM(PCPUMCTX pCtx);
636	DECLASM(void) cpumR0SaveXMM(PCPUMCTX pCtx);
637	DECLASM(void) cpumR0SetFCW(uint16_t u16FCW);
638	DECLASM(uint16_t) cpumR0GetFCW(void);
639	DECLASM(void) cpumR0SetMXCSR(uint32_t u32MXCSR);
640	DECLASM(uint32_t) cpumR0GetMXCSR(void);
641	DECLASM(void) cpumR0LoadDRx(uint64_t const *pa4Regs);
642	DECLASM(void) cpumR0SaveDRx(uint64_t *pa4Regs);
643	#endif
644
645	RT_C_DECLS_END
646	#endif /* !VBOX_FOR_DTRACE_LIB */
647
648	/** @} */
649
650	#endif
651

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source: vbox/trunk/src/VBox/VMM/include/CPUMInternal.h@ 55049

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