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source: vbox/trunk/src/VBox/VMM/include/CPUMInternal.h@ 55106

Last change on this file since 55106 was 55106, checked in by vboxsync, 10 years ago

VMM: host+guest xsave/xrstor state handling - not enabled.
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1/* $Id: CPUMInternal.h 55106 2015-04-06 19:58:37Z vboxsync $ */
2/** @file
3 * CPUM - Internal header file.
4 */
5
6/*
7 * Copyright (C) 2006-2015 Oracle Corporation
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 */
17
18#ifndef ___CPUMInternal_h
19#define ___CPUMInternal_h
20
21#ifndef VBOX_FOR_DTRACE_LIB
22# include <VBox/cdefs.h>
23# include <VBox/types.h>
24# include <VBox/vmm/stam.h>
25# include <iprt/x86.h>
26#else
27# pragma D depends_on library x86.d
28# pragma D depends_on library cpumctx.d
29
30/* Some fudging. */
31typedef uint32_t CPUMMICROARCH;
32typedef uint32_t CPUMUNKNOWNCPUID;
33typedef struct CPUMCPUIDLEAF *PCPUMCPUIDLEAF;
34typedef struct CPUMMSRRANGE *PCPUMMSRRANGE;
35typedef uint64_t STAMCOUNTER;
36#endif
37
38
39
40
41/** @defgroup grp_cpum_int Internals
42 * @ingroup grp_cpum
43 * @internal
44 * @{
45 */
46
47/** Flags and types for CPUM fault handlers
48 * @{ */
49/** Type: Load DS */
50#define CPUM_HANDLER_DS 1
51/** Type: Load ES */
52#define CPUM_HANDLER_ES 2
53/** Type: Load FS */
54#define CPUM_HANDLER_FS 3
55/** Type: Load GS */
56#define CPUM_HANDLER_GS 4
57/** Type: IRET */
58#define CPUM_HANDLER_IRET 5
59/** Type mask. */
60#define CPUM_HANDLER_TYPEMASK 0xff
61/** If set EBP points to the CPUMCTXCORE that's being used. */
62#define CPUM_HANDLER_CTXCORE_IN_EBP RT_BIT(31)
63/** @} */
64
65
66/** Use flags (CPUM::fUseFlags).
67 * (Don't forget to sync this with CPUMInternal.mac !)
68 * @{ */
69/** Used the FPU, SSE or such stuff. */
70#define CPUM_USED_FPU RT_BIT(0)
71/** Used the FPU, SSE or such stuff since last we were in REM.
72 * REM syncing is clearing this, lazy FPU is setting it. */
73#define CPUM_USED_FPU_SINCE_REM RT_BIT(1)
74/** The XMM state was manually restored. (AMD only) */
75#define CPUM_USED_MANUAL_XMM_RESTORE RT_BIT(2)
76
77/** Host OS is using SYSENTER and we must NULL the CS. */
78#define CPUM_USE_SYSENTER RT_BIT(3)
79/** Host OS is using SYSENTER and we must NULL the CS. */
80#define CPUM_USE_SYSCALL RT_BIT(4)
81
82/** Debug registers are used by host and that DR7 and DR6 must be saved and
83 * disabled when switching to raw-mode. */
84#define CPUM_USE_DEBUG_REGS_HOST RT_BIT(5)
85/** Records that we've saved the host DRx registers.
86 * In ring-0 this means all (DR0-7), while in raw-mode context this means DR0-3
87 * since DR6 and DR7 are covered by CPUM_USE_DEBUG_REGS_HOST. */
88#define CPUM_USED_DEBUG_REGS_HOST RT_BIT(6)
89/** Set to indicate that we should save host DR0-7 and load the hypervisor debug
90 * registers in the raw-mode world switchers. (See CPUMRecalcHyperDRx.) */
91#define CPUM_USE_DEBUG_REGS_HYPER RT_BIT(7)
92/** Used in ring-0 to indicate that we have loaded the hypervisor debug
93 * registers. */
94#define CPUM_USED_DEBUG_REGS_HYPER RT_BIT(8)
95/** Used in ring-0 to indicate that we have loaded the guest debug
96 * registers (DR0-3 and maybe DR6) for direct use by the guest.
97 * DR7 (and AMD-V DR6) are handled via the VMCB. */
98#define CPUM_USED_DEBUG_REGS_GUEST RT_BIT(9)
99
100
101/** Sync the FPU state on next entry (32->64 switcher only). */
102#define CPUM_SYNC_FPU_STATE RT_BIT(16)
103/** Sync the debug state on next entry (32->64 switcher only). */
104#define CPUM_SYNC_DEBUG_REGS_GUEST RT_BIT(17)
105/** Sync the debug state on next entry (32->64 switcher only).
106 * Almost the same as CPUM_USE_DEBUG_REGS_HYPER in the raw-mode switchers. */
107#define CPUM_SYNC_DEBUG_REGS_HYPER RT_BIT(18)
108/** Host CPU requires fxsave/fxrstor leaky bit handling. */
109#define CPUM_USE_FFXSR_LEAKY RT_BIT(19)
110/** Set if the VM supports long-mode. */
111#define CPUM_USE_SUPPORTS_LONGMODE RT_BIT(20)
112/** @} */
113
114/* Sanity check. */
115#ifndef VBOX_FOR_DTRACE_LIB
116#if defined(VBOX_WITH_HYBRID_32BIT_KERNEL) && (HC_ARCH_BITS != 32 || R0_ARCH_BITS != 32)
117# error "VBOX_WITH_HYBRID_32BIT_KERNEL is only for 32 bit builds."
118#endif
119#endif
120
121
122/** @name CPUM Saved State Version.
123 * @{ */
124/** The current saved state version. */
125#define CPUM_SAVED_STATE_VERSION 16
126/** CPUID changes with explode forgetting to update the leaf count on
127 * restore, resulting in garbage being saved restoring+saving old states). */
128#define CPUM_SAVED_STATE_VERSION_BAD_CPUID_COUNT 15
129/** The saved state version before the CPUIDs changes. */
130#define CPUM_SAVED_STATE_VERSION_PUT_STRUCT 14
131/** The saved state version before using SSMR3PutStruct. */
132#define CPUM_SAVED_STATE_VERSION_MEM 13
133/** The saved state version before introducing the MSR size field. */
134#define CPUM_SAVED_STATE_VERSION_NO_MSR_SIZE 12
135/** The saved state version of 3.2, 3.1 and 3.3 trunk before the hidden
136 * selector register change (CPUM_CHANGED_HIDDEN_SEL_REGS_INVALID). */
137#define CPUM_SAVED_STATE_VERSION_VER3_2 11
138/** The saved state version of 3.0 and 3.1 trunk before the teleportation
139 * changes. */
140#define CPUM_SAVED_STATE_VERSION_VER3_0 10
141/** The saved state version for the 2.1 trunk before the MSR changes. */
142#define CPUM_SAVED_STATE_VERSION_VER2_1_NOMSR 9
143/** The saved state version of 2.0, used for backwards compatibility. */
144#define CPUM_SAVED_STATE_VERSION_VER2_0 8
145/** The saved state version of 1.6, used for backwards compatibility. */
146#define CPUM_SAVED_STATE_VERSION_VER1_6 6
147/** @} */
148
149
150
151/**
152 * CPU features and quirks.
153 * This is mostly exploded CPUID info.
154 */
155typedef struct CPUMFEATURES
156{
157 /** The CPU vendor (CPUMCPUVENDOR). */
158 uint8_t enmCpuVendor;
159 /** The CPU family. */
160 uint8_t uFamily;
161 /** The CPU model. */
162 uint8_t uModel;
163 /** The CPU stepping. */
164 uint8_t uStepping;
165 /** The microarchitecture. */
166#ifndef VBOX_FOR_DTRACE_LIB
167 CPUMMICROARCH enmMicroarch;
168#else
169 uint32_t enmMicroarch;
170#endif
171 /** The maximum physical address with of the CPU. */
172 uint8_t cMaxPhysAddrWidth;
173 /** Alignment padding. */
174 uint8_t abPadding[1];
175 /** Max size of the extended state (or FPU state if no XSAVE). */
176 uint16_t cbMaxExtendedState;
177
178 /** Supports MSRs. */
179 uint32_t fMsr : 1;
180 /** Supports the page size extension (4/2 MB pages). */
181 uint32_t fPse : 1;
182 /** Supports 36-bit page size extension (4 MB pages can map memory above
183 * 4GB). */
184 uint32_t fPse36 : 1;
185 /** Supports physical address extension (PAE). */
186 uint32_t fPae : 1;
187 /** Page attribute table (PAT) support (page level cache control). */
188 uint32_t fPat : 1;
189 /** Supports the FXSAVE and FXRSTOR instructions. */
190 uint32_t fFxSaveRstor : 1;
191 /** Supports the XSAVE and XRSTOR instructions. */
192 uint32_t fXSaveRstor : 1;
193 /** Supports MMX. */
194 uint32_t fMmx : 1;
195 /** Supports SSE. */
196 uint32_t fSse : 1;
197 /** Supports SSE2. */
198 uint32_t fSse2 : 1;
199 /** Supports SSE3. */
200 uint32_t fSse3 : 1;
201 /** Supports SSSE3. */
202 uint32_t fSsse3 : 1;
203 /** Supports SSE4.1. */
204 uint32_t fSse41 : 1;
205 /** Supports SSE4.2. */
206 uint32_t fSse42 : 1;
207 /** Supports AVX. */
208 uint32_t fAvx : 1;
209 /** Supports AVX2. */
210 uint32_t fAvx2 : 1;
211 /** Supports AVX512 foundation. */
212 uint32_t fAvx512Foundation : 1;
213 /** Supports RDTSC. */
214 uint32_t fTsc : 1;
215 /** Intel SYSENTER/SYSEXIT support */
216 uint32_t fSysEnter : 1;
217 /** First generation APIC. */
218 uint32_t fApic : 1;
219 /** Second generation APIC. */
220 uint32_t fX2Apic : 1;
221 /** Hypervisor present. */
222 uint32_t fHypervisorPresent : 1;
223 /** MWAIT & MONITOR instructions supported. */
224 uint32_t fMonitorMWait : 1;
225 /** MWAIT Extensions present. */
226 uint32_t fMWaitExtensions : 1;
227
228 /** AMD64: Supports long mode. */
229 uint32_t fLongMode : 1;
230 /** AMD64: SYSCALL/SYSRET support. */
231 uint32_t fSysCall : 1;
232 /** AMD64: No-execute page table bit. */
233 uint32_t fNoExecute : 1;
234 /** AMD64: Supports LAHF & SAHF instructions in 64-bit mode. */
235 uint32_t fLahfSahf : 1;
236 /** AMD64: Supports RDTSCP. */
237 uint32_t fRdTscP : 1;
238
239 /** Indicates that FPU instruction and data pointers may leak.
240 * This generally applies to recent AMD CPUs, where the FPU IP and DP pointer
241 * is only saved and restored if an exception is pending. */
242 uint32_t fLeakyFxSR : 1;
243
244 /** Alignment padding / reserved for future use. */
245 uint32_t fPadding : 2;
246 uint64_t auPadding[2];
247} CPUMFEATURES;
248#ifndef VBOX_FOR_DTRACE_LIB
249AssertCompileSize(CPUMFEATURES, 32);
250#endif
251/** Pointer to a CPU feature structure. */
252typedef CPUMFEATURES *PCPUMFEATURES;
253/** Pointer to a const CPU feature structure. */
254typedef CPUMFEATURES const *PCCPUMFEATURES;
255
256
257/**
258 * CPU info
259 */
260typedef struct CPUMINFO
261{
262 /** The number of MSR ranges (CPUMMSRRANGE) in the array pointed to below. */
263 uint32_t cMsrRanges;
264 /** Mask applied to ECX before looking up the MSR for a RDMSR/WRMSR
265 * instruction. Older hardware has been observed to ignore higher bits. */
266 uint32_t fMsrMask;
267
268 /** The number of CPUID leaves (CPUMCPUIDLEAF) in the array pointed to below. */
269 uint32_t cCpuIdLeaves;
270 /** The index of the first extended CPUID leaf in the array.
271 * Set to cCpuIdLeaves if none present. */
272 uint32_t iFirstExtCpuIdLeaf;
273 /** Alignment padding. */
274 uint32_t uPadding;
275 /** How to handle unknown CPUID leaves. */
276 CPUMUNKNOWNCPUID enmUnknownCpuIdMethod;
277 /** For use with CPUMUNKNOWNCPUID_DEFAULTS (DB & VM),
278 * CPUMUNKNOWNCPUID_LAST_STD_LEAF (VM) and CPUMUNKNOWNCPUID_LAST_STD_LEAF_WITH_ECX (VM). */
279 CPUMCPUID DefCpuId;
280
281 /** Scalable bus frequency used for reporting other frequencies. */
282 uint64_t uScalableBusFreq;
283
284 /** Pointer to the MSR ranges (ring-0 pointer). */
285 R0PTRTYPE(PCPUMMSRRANGE) paMsrRangesR0;
286 /** Pointer to the CPUID leaves (ring-0 pointer). */
287 R0PTRTYPE(PCPUMCPUIDLEAF) paCpuIdLeavesR0;
288
289 /** Pointer to the MSR ranges (ring-3 pointer). */
290 R3PTRTYPE(PCPUMMSRRANGE) paMsrRangesR3;
291 /** Pointer to the CPUID leaves (ring-3 pointer). */
292 R3PTRTYPE(PCPUMCPUIDLEAF) paCpuIdLeavesR3;
293
294 /** Pointer to the MSR ranges (raw-mode context pointer). */
295 RCPTRTYPE(PCPUMMSRRANGE) paMsrRangesRC;
296 /** Pointer to the CPUID leaves (raw-mode context pointer). */
297 RCPTRTYPE(PCPUMCPUIDLEAF) paCpuIdLeavesRC;
298} CPUMINFO;
299/** Pointer to a CPU info structure. */
300typedef CPUMINFO *PCPUMINFO;
301/** Pointer to a const CPU info structure. */
302typedef CPUMINFO const *CPCPUMINFO;
303
304
305/**
306 * The saved host CPU state.
307 *
308 * @remark The special VBOX_WITH_HYBRID_32BIT_KERNEL checks here are for the 10.4.x series
309 * of Mac OS X where the OS is essentially 32-bit but the cpu mode can be 64-bit.
310 */
311typedef struct CPUMHOSTCTX
312{
313 /** General purpose register, selectors, flags and more
314 * @{ */
315#if HC_ARCH_BITS == 64 || defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
316 /** General purpose register ++
317 * { */
318 /*uint64_t rax; - scratch*/
319 uint64_t rbx;
320 /*uint64_t rcx; - scratch*/
321 /*uint64_t rdx; - scratch*/
322 uint64_t rdi;
323 uint64_t rsi;
324 uint64_t rbp;
325 uint64_t rsp;
326 /*uint64_t r8; - scratch*/
327 /*uint64_t r9; - scratch*/
328 uint64_t r10;
329 uint64_t r11;
330 uint64_t r12;
331 uint64_t r13;
332 uint64_t r14;
333 uint64_t r15;
334 /*uint64_t rip; - scratch*/
335 uint64_t rflags;
336#endif
337
338#if HC_ARCH_BITS == 32
339 /*uint32_t eax; - scratch*/
340 uint32_t ebx;
341 /*uint32_t ecx; - scratch*/
342 /*uint32_t edx; - scratch*/
343 uint32_t edi;
344 uint32_t esi;
345 uint32_t ebp;
346 X86EFLAGS eflags;
347 /*uint32_t eip; - scratch*/
348 /* lss pair! */
349 uint32_t esp;
350#endif
351 /** @} */
352
353 /** Selector registers
354 * @{ */
355 RTSEL ss;
356 RTSEL ssPadding;
357 RTSEL gs;
358 RTSEL gsPadding;
359 RTSEL fs;
360 RTSEL fsPadding;
361 RTSEL es;
362 RTSEL esPadding;
363 RTSEL ds;
364 RTSEL dsPadding;
365 RTSEL cs;
366 RTSEL csPadding;
367 /** @} */
368
369#if HC_ARCH_BITS == 32 && !defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
370 /** Control registers.
371 * @{ */
372 uint32_t cr0;
373 /*uint32_t cr2; - scratch*/
374 uint32_t cr3;
375 uint32_t cr4;
376 /** @} */
377
378 /** Debug registers.
379 * @{ */
380 uint32_t dr0;
381 uint32_t dr1;
382 uint32_t dr2;
383 uint32_t dr3;
384 uint32_t dr6;
385 uint32_t dr7;
386 /** @} */
387
388 /** Global Descriptor Table register. */
389 X86XDTR32 gdtr;
390 uint16_t gdtrPadding;
391 /** Interrupt Descriptor Table register. */
392 X86XDTR32 idtr;
393 uint16_t idtrPadding;
394 /** The task register. */
395 RTSEL ldtr;
396 RTSEL ldtrPadding;
397 /** The task register. */
398 RTSEL tr;
399 RTSEL trPadding;
400 uint32_t SysEnterPadding;
401
402 /** The sysenter msr registers.
403 * This member is not used by the hypervisor context. */
404 CPUMSYSENTER SysEnter;
405
406 /** MSRs
407 * @{ */
408 uint64_t efer;
409 /** @} */
410
411 /* padding to get 64byte aligned size */
412 uint8_t auPadding[20];
413
414#elif HC_ARCH_BITS == 64 || defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
415
416 /** Control registers.
417 * @{ */
418 uint64_t cr0;
419 /*uint64_t cr2; - scratch*/
420 uint64_t cr3;
421 uint64_t cr4;
422 uint64_t cr8;
423 /** @} */
424
425 /** Debug registers.
426 * @{ */
427 uint64_t dr0;
428 uint64_t dr1;
429 uint64_t dr2;
430 uint64_t dr3;
431 uint64_t dr6;
432 uint64_t dr7;
433 /** @} */
434
435 /** Global Descriptor Table register. */
436 X86XDTR64 gdtr;
437 uint16_t gdtrPadding;
438 /** Interrupt Descriptor Table register. */
439 X86XDTR64 idtr;
440 uint16_t idtrPadding;
441 /** The task register. */
442 RTSEL ldtr;
443 RTSEL ldtrPadding;
444 /** The task register. */
445 RTSEL tr;
446 RTSEL trPadding;
447
448 /** MSRs
449 * @{ */
450 CPUMSYSENTER SysEnter;
451 uint64_t FSbase;
452 uint64_t GSbase;
453 uint64_t efer;
454 /** @} */
455
456 /* padding to get 32byte aligned size */
457# ifdef VBOX_WITH_HYBRID_32BIT_KERNEL
458 uint8_t auPadding[52];
459# else
460 uint8_t auPadding[4];
461# endif
462
463#else
464# error HC_ARCH_BITS not defined
465#endif
466
467 /** Pointer to the FPU/SSE/AVX/XXXX state raw-mode mapping. */
468 RCPTRTYPE(PX86XSAVEAREA) pXStateRC;
469 /** Pointer to the FPU/SSE/AVX/XXXX state ring-0 mapping. */
470 R0PTRTYPE(PX86XSAVEAREA) pXStateR0;
471 /** Pointer to the FPU/SSE/AVX/XXXX state ring-3 mapping. */
472 R3PTRTYPE(PX86XSAVEAREA) pXStateR3;
473 /** The XCR0 register. */
474 uint64_t xcr0;
475 /** The mask to pass to XSAVE/XRSTOR in EDX:EAX. If zero we use
476 * FXSAVE/FXRSTOR (since bit 0 will always be set, we only need to test it). */
477 uint64_t fXStateMask;
478} CPUMHOSTCTX;
479AssertCompileSizeAlignment(CPUMHOSTCTX, 64);
480/** Pointer to the saved host CPU state. */
481typedef CPUMHOSTCTX *PCPUMHOSTCTX;
482
483
484/**
485 * CPUM Data (part of VM)
486 */
487typedef struct CPUM
488{
489 /** Offset from CPUM to CPUMCPU for the first CPU. */
490 uint32_t offCPUMCPU0;
491
492 /** Use flags.
493 * These flags indicates which CPU features the host uses.
494 */
495 uint32_t fHostUseFlags;
496
497 /** CR4 mask */
498 struct
499 {
500 uint32_t AndMask; /**< @todo Move these to the per-CPU structure and fix the switchers. Saves a register! */
501 uint32_t OrMask;
502 } CR4;
503
504 /** The (more) portable CPUID level. */
505 uint8_t u8PortableCpuIdLevel;
506 /** Indicates that a state restore is pending.
507 * This is used to verify load order dependencies (PGM). */
508 bool fPendingRestore;
509 uint8_t abPadding[HC_ARCH_BITS == 64 ? 6 : 2];
510
511 /** The standard set of CpuId leaves. */
512 CPUMCPUID aGuestCpuIdPatmStd[6];
513 /** The extended set of CpuId leaves. */
514 CPUMCPUID aGuestCpuIdPatmExt[10];
515 /** The centaur set of CpuId leaves. */
516 CPUMCPUID aGuestCpuIdPatmCentaur[4];
517
518#if HC_ARCH_BITS == 32
519 uint8_t abPadding2[4];
520#endif
521
522 /** Guest CPU info. */
523 CPUMINFO GuestInfo;
524 /** Guest CPU feature information. */
525 CPUMFEATURES GuestFeatures;
526 /** Host CPU feature information. */
527 CPUMFEATURES HostFeatures;
528
529 /** @name MSR statistics.
530 * @{ */
531 STAMCOUNTER cMsrWrites;
532 STAMCOUNTER cMsrWritesToIgnoredBits;
533 STAMCOUNTER cMsrWritesRaiseGp;
534 STAMCOUNTER cMsrWritesUnknown;
535 STAMCOUNTER cMsrReads;
536 STAMCOUNTER cMsrReadsRaiseGp;
537 STAMCOUNTER cMsrReadsUnknown;
538 /** @} */
539} CPUM;
540/** Pointer to the CPUM instance data residing in the shared VM structure. */
541typedef CPUM *PCPUM;
542
543/**
544 * CPUM Data (part of VMCPU)
545 */
546typedef struct CPUMCPU
547{
548 /**
549 * Guest context.
550 * Aligned on a 64-byte boundary.
551 */
552 CPUMCTX Guest;
553
554 /**
555 * Guest context - misc MSRs
556 * Aligned on a 64-byte boundary.
557 */
558 CPUMCTXMSRS GuestMsrs;
559
560 /** Use flags.
561 * These flags indicates both what is to be used and what has been used.
562 */
563 uint32_t fUseFlags;
564
565 /** Changed flags.
566 * These flags indicates to REM (and others) which important guest
567 * registers which has been changed since last time the flags were cleared.
568 * See the CPUM_CHANGED_* defines for what we keep track of.
569 */
570 uint32_t fChanged;
571
572 /** Offset from CPUM to CPUMCPU. */
573 uint32_t offCPUM;
574
575 /** Temporary storage for the return code of the function called in the
576 * 32-64 switcher. */
577 uint32_t u32RetCode;
578
579#ifdef VBOX_WITH_VMMR0_DISABLE_LAPIC_NMI
580 /** The address of the APIC mapping, NULL if no APIC.
581 * Call CPUMR0SetLApic to update this before doing a world switch. */
582 RTHCPTR pvApicBase;
583 /** Used by the world switcher code to store which vectors needs restoring on
584 * the way back. */
585 uint32_t fApicDisVectors;
586 /** Set if the CPU has the X2APIC mode enabled.
587 * Call CPUMR0SetLApic to update this before doing a world switch. */
588 bool fX2Apic;
589#else
590 uint8_t abPadding3[(HC_ARCH_BITS == 64 ? 8 : 4) + 4 + 1];
591#endif
592
593 /** Have we entered raw-mode? */
594 bool fRawEntered;
595 /** Have we entered the recompiler? */
596 bool fRemEntered;
597
598 /** Align the next member on a 64-bit boundrary. */
599 uint8_t abPadding2[64 - 16 - (HC_ARCH_BITS == 64 ? 8 : 4) - 4 - 1 - 2];
600
601 /** Saved host context. Only valid while inside RC or HM contexts.
602 * Must be aligned on a 64-byte boundary. */
603 CPUMHOSTCTX Host;
604 /** Hypervisor context. Must be aligned on a 64-byte boundary. */
605 CPUMCTX Hyper;
606
607#ifdef VBOX_WITH_CRASHDUMP_MAGIC
608 uint8_t aMagic[56];
609 uint64_t uMagic;
610#endif
611} CPUMCPU;
612/** Pointer to the CPUMCPU instance data residing in the shared VMCPU structure. */
613typedef CPUMCPU *PCPUMCPU;
614
615#ifndef VBOX_FOR_DTRACE_LIB
616RT_C_DECLS_BEGIN
617
618PCPUMCPUIDLEAF cpumCpuIdGetLeaf(PVM pVM, uint32_t uLeaf);
619PCPUMCPUIDLEAF cpumCpuIdGetLeafEx(PVM pVM, uint32_t uLeaf, uint32_t uSubLeaf, bool *pfExactSubLeafHit);
620
621#ifdef IN_RING3
622int cpumR3DbgInit(PVM pVM);
623int cpumR3CpuIdExplodeFeatures(PCCPUMCPUIDLEAF paLeaves, uint32_t cLeaves, PCPUMFEATURES pFeatures);
624int cpumR3InitCpuIdAndMsrs(PVM pVM);
625void cpumR3SaveCpuId(PVM pVM, PSSMHANDLE pSSM);
626int cpumR3LoadCpuId(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion);
627DECLCALLBACK(void) cpumR3CpuIdInfo(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
628
629int cpumR3DbGetCpuInfo(const char *pszName, PCPUMINFO pInfo);
630int cpumR3MsrRangesInsert(PVM pVM, PCPUMMSRRANGE *ppaMsrRanges, uint32_t *pcMsrRanges, PCCPUMMSRRANGE pNewRange);
631int cpumR3MsrApplyFudge(PVM pVM);
632int cpumR3MsrRegStats(PVM pVM);
633int cpumR3MsrStrictInitChecks(void);
634PCPUMMSRRANGE cpumLookupMsrRange(PVM pVM, uint32_t idMsr);
635#endif
636
637#ifdef IN_RC
638DECLASM(int) cpumHandleLazyFPUAsm(PCPUMCPU pCPUM);
639#endif
640
641#ifdef IN_RING0
642DECLASM(int) cpumR0SaveHostRestoreGuestFPUState(PCPUMCPU pCPUM);
643DECLASM(int) cpumR0SaveGuestRestoreHostFPUState(PCPUMCPU pCPUM);
644DECLASM(int) cpumR0SaveHostFPUState(PCPUMCPU pCPUM);
645DECLASM(int) cpumR0RestoreHostFPUState(PCPUMCPU pCPUM);
646DECLASM(void) cpumR0LoadFPU(PCPUMCTX pCtx);
647DECLASM(void) cpumR0SaveFPU(PCPUMCTX pCtx);
648DECLASM(void) cpumR0LoadXMM(PCPUMCTX pCtx);
649DECLASM(void) cpumR0SaveXMM(PCPUMCTX pCtx);
650DECLASM(void) cpumR0SetFCW(uint16_t u16FCW);
651DECLASM(uint16_t) cpumR0GetFCW(void);
652DECLASM(void) cpumR0SetMXCSR(uint32_t u32MXCSR);
653DECLASM(uint32_t) cpumR0GetMXCSR(void);
654DECLASM(void) cpumR0LoadDRx(uint64_t const *pa4Regs);
655DECLASM(void) cpumR0SaveDRx(uint64_t *pa4Regs);
656#endif
657
658RT_C_DECLS_END
659#endif /* !VBOX_FOR_DTRACE_LIB */
660
661/** @} */
662
663#endif
664
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