VirtualBox

source: vbox/trunk/src/VBox/VMM/include/CPUMInternal.h@ 73389

Last change on this file since 73389 was 73389, checked in by vboxsync, 6 years ago

VMM, SUPDrv: Nested VMX: bugref:9180 Implement some of the VMX MSRs.
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1/* $Id: CPUMInternal.h 73389 2018-07-28 07:03:03Z vboxsync $ */
2/** @file
3 * CPUM - Internal header file.
4 */
5
6/*
7 * Copyright (C) 2006-2017 Oracle Corporation
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 */
17
18#ifndef ___CPUMInternal_h
19#define ___CPUMInternal_h
20
21#ifndef VBOX_FOR_DTRACE_LIB
22# include <VBox/cdefs.h>
23# include <VBox/types.h>
24# include <VBox/vmm/stam.h>
25# include <iprt/x86.h>
26#else
27# pragma D depends_on library x86.d
28# pragma D depends_on library cpumctx.d
29# pragma D depends_on library cpum.d
30
31/* Some fudging. */
32typedef uint64_t STAMCOUNTER;
33#endif
34
35
36
37
38/** @defgroup grp_cpum_int Internals
39 * @ingroup grp_cpum
40 * @internal
41 * @{
42 */
43
44/** Flags and types for CPUM fault handlers
45 * @{ */
46/** Type: Load DS */
47#define CPUM_HANDLER_DS 1
48/** Type: Load ES */
49#define CPUM_HANDLER_ES 2
50/** Type: Load FS */
51#define CPUM_HANDLER_FS 3
52/** Type: Load GS */
53#define CPUM_HANDLER_GS 4
54/** Type: IRET */
55#define CPUM_HANDLER_IRET 5
56/** Type mask. */
57#define CPUM_HANDLER_TYPEMASK 0xff
58/** If set EBP points to the CPUMCTXCORE that's being used. */
59#define CPUM_HANDLER_CTXCORE_IN_EBP RT_BIT(31)
60/** @} */
61
62
63/** Use flags (CPUM::fUseFlags).
64 * (Don't forget to sync this with CPUMInternal.mac !)
65 * @note Part of saved state.
66 * @{ */
67/** Indicates that we've saved the host FPU, SSE, whatever state and that it
68 * needs to be restored. */
69#define CPUM_USED_FPU_HOST RT_BIT(0)
70/** Indicates that we've loaded the guest FPU, SSE, whatever state and that it
71 * needs to be saved. */
72#define CPUM_USED_FPU_GUEST RT_BIT(10)
73/** Used the guest FPU, SSE or such stuff since last we were in REM.
74 * REM syncing is clearing this, lazy FPU is setting it. */
75#define CPUM_USED_FPU_SINCE_REM RT_BIT(1)
76/** The XMM state was manually restored. (AMD only) */
77#define CPUM_USED_MANUAL_XMM_RESTORE RT_BIT(2)
78
79/** Host OS is using SYSENTER and we must NULL the CS. */
80#define CPUM_USE_SYSENTER RT_BIT(3)
81/** Host OS is using SYSENTER and we must NULL the CS. */
82#define CPUM_USE_SYSCALL RT_BIT(4)
83
84/** Debug registers are used by host and that DR7 and DR6 must be saved and
85 * disabled when switching to raw-mode. */
86#define CPUM_USE_DEBUG_REGS_HOST RT_BIT(5)
87/** Records that we've saved the host DRx registers.
88 * In ring-0 this means all (DR0-7), while in raw-mode context this means DR0-3
89 * since DR6 and DR7 are covered by CPUM_USE_DEBUG_REGS_HOST. */
90#define CPUM_USED_DEBUG_REGS_HOST RT_BIT(6)
91/** Set to indicate that we should save host DR0-7 and load the hypervisor debug
92 * registers in the raw-mode world switchers. (See CPUMRecalcHyperDRx.) */
93#define CPUM_USE_DEBUG_REGS_HYPER RT_BIT(7)
94/** Used in ring-0 to indicate that we have loaded the hypervisor debug
95 * registers. */
96#define CPUM_USED_DEBUG_REGS_HYPER RT_BIT(8)
97/** Used in ring-0 to indicate that we have loaded the guest debug
98 * registers (DR0-3 and maybe DR6) for direct use by the guest.
99 * DR7 (and AMD-V DR6) are handled via the VMCB. */
100#define CPUM_USED_DEBUG_REGS_GUEST RT_BIT(9)
101
102/** Sync the FPU state on next entry (32->64 switcher only). */
103#define CPUM_SYNC_FPU_STATE RT_BIT(16)
104/** Sync the debug state on next entry (32->64 switcher only). */
105#define CPUM_SYNC_DEBUG_REGS_GUEST RT_BIT(17)
106/** Sync the debug state on next entry (32->64 switcher only).
107 * Almost the same as CPUM_USE_DEBUG_REGS_HYPER in the raw-mode switchers. */
108#define CPUM_SYNC_DEBUG_REGS_HYPER RT_BIT(18)
109/** Host CPU requires fxsave/fxrstor leaky bit handling. */
110#define CPUM_USE_FFXSR_LEAKY RT_BIT(19)
111/** Set if the VM supports long-mode. */
112#define CPUM_USE_SUPPORTS_LONGMODE RT_BIT(20)
113/** @} */
114
115
116/** @name CPUM Saved State Version.
117 * @{ */
118/** The current saved state version. */
119#define CPUM_SAVED_STATE_VERSION CPUM_SAVED_STATE_VERSION_HWVIRT_SVM
120/** The saved state version including SVM hardware virtualization state. */
121#define CPUM_SAVED_STATE_VERSION_HWVIRT_SVM 18
122/** The saved state version including XSAVE state. */
123#define CPUM_SAVED_STATE_VERSION_XSAVE 17
124/** The saved state version with good CPUID leaf count. */
125#define CPUM_SAVED_STATE_VERSION_GOOD_CPUID_COUNT 16
126/** CPUID changes with explode forgetting to update the leaf count on
127 * restore, resulting in garbage being saved restoring+saving old states). */
128#define CPUM_SAVED_STATE_VERSION_BAD_CPUID_COUNT 15
129/** The saved state version before the CPUIDs changes. */
130#define CPUM_SAVED_STATE_VERSION_PUT_STRUCT 14
131/** The saved state version before using SSMR3PutStruct. */
132#define CPUM_SAVED_STATE_VERSION_MEM 13
133/** The saved state version before introducing the MSR size field. */
134#define CPUM_SAVED_STATE_VERSION_NO_MSR_SIZE 12
135/** The saved state version of 3.2, 3.1 and 3.3 trunk before the hidden
136 * selector register change (CPUM_CHANGED_HIDDEN_SEL_REGS_INVALID). */
137#define CPUM_SAVED_STATE_VERSION_VER3_2 11
138/** The saved state version of 3.0 and 3.1 trunk before the teleportation
139 * changes. */
140#define CPUM_SAVED_STATE_VERSION_VER3_0 10
141/** The saved state version for the 2.1 trunk before the MSR changes. */
142#define CPUM_SAVED_STATE_VERSION_VER2_1_NOMSR 9
143/** The saved state version of 2.0, used for backwards compatibility. */
144#define CPUM_SAVED_STATE_VERSION_VER2_0 8
145/** The saved state version of 1.6, used for backwards compatibility. */
146#define CPUM_SAVED_STATE_VERSION_VER1_6 6
147/** @} */
148
149
150/**
151 * CPU info
152 */
153typedef struct CPUMINFO
154{
155 /** The number of MSR ranges (CPUMMSRRANGE) in the array pointed to below. */
156 uint32_t cMsrRanges;
157 /** Mask applied to ECX before looking up the MSR for a RDMSR/WRMSR
158 * instruction. Older hardware has been observed to ignore higher bits. */
159 uint32_t fMsrMask;
160
161 /** MXCSR mask. */
162 uint32_t fMxCsrMask;
163
164 /** The number of CPUID leaves (CPUMCPUIDLEAF) in the array pointed to below. */
165 uint32_t cCpuIdLeaves;
166 /** The index of the first extended CPUID leaf in the array.
167 * Set to cCpuIdLeaves if none present. */
168 uint32_t iFirstExtCpuIdLeaf;
169 /** How to handle unknown CPUID leaves. */
170 CPUMUNKNOWNCPUID enmUnknownCpuIdMethod;
171 /** For use with CPUMUNKNOWNCPUID_DEFAULTS (DB & VM),
172 * CPUMUNKNOWNCPUID_LAST_STD_LEAF (VM) and CPUMUNKNOWNCPUID_LAST_STD_LEAF_WITH_ECX (VM). */
173 CPUMCPUID DefCpuId;
174
175 /** Scalable bus frequency used for reporting other frequencies. */
176 uint64_t uScalableBusFreq;
177
178 /** Pointer to the MSR ranges (ring-0 pointer). */
179 R0PTRTYPE(PCPUMMSRRANGE) paMsrRangesR0;
180 /** Pointer to the CPUID leaves (ring-0 pointer). */
181 R0PTRTYPE(PCPUMCPUIDLEAF) paCpuIdLeavesR0;
182
183 /** Pointer to the MSR ranges (ring-3 pointer). */
184 R3PTRTYPE(PCPUMMSRRANGE) paMsrRangesR3;
185 /** Pointer to the CPUID leaves (ring-3 pointer). */
186 R3PTRTYPE(PCPUMCPUIDLEAF) paCpuIdLeavesR3;
187
188 /** Pointer to the MSR ranges (raw-mode context pointer). */
189 RCPTRTYPE(PCPUMMSRRANGE) paMsrRangesRC;
190 /** Pointer to the CPUID leaves (raw-mode context pointer). */
191 RCPTRTYPE(PCPUMCPUIDLEAF) paCpuIdLeavesRC;
192} CPUMINFO;
193/** Pointer to a CPU info structure. */
194typedef CPUMINFO *PCPUMINFO;
195/** Pointer to a const CPU info structure. */
196typedef CPUMINFO const *CPCPUMINFO;
197
198
199/**
200 * The saved host CPU state.
201 */
202typedef struct CPUMHOSTCTX
203{
204 /** General purpose register, selectors, flags and more
205 * @{ */
206#if HC_ARCH_BITS == 64
207 /** General purpose register ++
208 * { */
209 /*uint64_t rax; - scratch*/
210 uint64_t rbx;
211 /*uint64_t rcx; - scratch*/
212 /*uint64_t rdx; - scratch*/
213 uint64_t rdi;
214 uint64_t rsi;
215 uint64_t rbp;
216 uint64_t rsp;
217 /*uint64_t r8; - scratch*/
218 /*uint64_t r9; - scratch*/
219 uint64_t r10;
220 uint64_t r11;
221 uint64_t r12;
222 uint64_t r13;
223 uint64_t r14;
224 uint64_t r15;
225 /*uint64_t rip; - scratch*/
226 uint64_t rflags;
227#endif
228
229#if HC_ARCH_BITS == 32
230 /*uint32_t eax; - scratch*/
231 uint32_t ebx;
232 /*uint32_t ecx; - scratch*/
233 /*uint32_t edx; - scratch*/
234 uint32_t edi;
235 uint32_t esi;
236 uint32_t ebp;
237 X86EFLAGS eflags;
238 /*uint32_t eip; - scratch*/
239 /* lss pair! */
240 uint32_t esp;
241#endif
242 /** @} */
243
244 /** Selector registers
245 * @{ */
246 RTSEL ss;
247 RTSEL ssPadding;
248 RTSEL gs;
249 RTSEL gsPadding;
250 RTSEL fs;
251 RTSEL fsPadding;
252 RTSEL es;
253 RTSEL esPadding;
254 RTSEL ds;
255 RTSEL dsPadding;
256 RTSEL cs;
257 RTSEL csPadding;
258 /** @} */
259
260#if HC_ARCH_BITS == 32
261 /** Control registers.
262 * @{ */
263 uint32_t cr0;
264 /*uint32_t cr2; - scratch*/
265 uint32_t cr3;
266 uint32_t cr4;
267 /** The CR0 FPU state in HM mode. Can't use cr0 here because the
268 * 64-bit-on-32-bit-host world switches is using it. */
269 uint32_t cr0Fpu;
270 /** @} */
271
272 /** Debug registers.
273 * @{ */
274 uint32_t dr0;
275 uint32_t dr1;
276 uint32_t dr2;
277 uint32_t dr3;
278 uint32_t dr6;
279 uint32_t dr7;
280 /** @} */
281
282 /** Global Descriptor Table register. */
283 X86XDTR32 gdtr;
284 uint16_t gdtrPadding;
285 /** Interrupt Descriptor Table register. */
286 X86XDTR32 idtr;
287 uint16_t idtrPadding;
288 /** The task register. */
289 RTSEL ldtr;
290 RTSEL ldtrPadding;
291 /** The task register. */
292 RTSEL tr;
293 RTSEL trPadding;
294
295 /** The sysenter msr registers.
296 * This member is not used by the hypervisor context. */
297 CPUMSYSENTER SysEnter;
298
299 /** MSRs
300 * @{ */
301 uint64_t efer;
302 /** @} */
303
304 /* padding to get 64byte aligned size */
305 uint8_t auPadding[20];
306
307#elif HC_ARCH_BITS == 64
308
309 /** Control registers.
310 * @{ */
311 /** The CR0 FPU state in HM mode. */
312 uint64_t cr0;
313 /*uint64_t cr2; - scratch*/
314 uint64_t cr3;
315 uint64_t cr4;
316 uint64_t cr8;
317 /** @} */
318
319 /** Debug registers.
320 * @{ */
321 uint64_t dr0;
322 uint64_t dr1;
323 uint64_t dr2;
324 uint64_t dr3;
325 uint64_t dr6;
326 uint64_t dr7;
327 /** @} */
328
329 /** Global Descriptor Table register. */
330 X86XDTR64 gdtr;
331 uint16_t gdtrPadding;
332 /** Interrupt Descriptor Table register. */
333 X86XDTR64 idtr;
334 uint16_t idtrPadding;
335 /** The task register. */
336 RTSEL ldtr;
337 RTSEL ldtrPadding;
338 /** The task register. */
339 RTSEL tr;
340 RTSEL trPadding;
341
342 /** MSRs
343 * @{ */
344 CPUMSYSENTER SysEnter;
345 uint64_t FSbase;
346 uint64_t GSbase;
347 uint64_t efer;
348 /** @} */
349
350 /* padding to get 64byte aligned size */
351 uint8_t auPadding[4];
352
353#else
354# error HC_ARCH_BITS not defined or unsupported
355#endif
356
357 /** Pointer to the FPU/SSE/AVX/XXXX state raw-mode mapping. */
358 RCPTRTYPE(PX86XSAVEAREA) pXStateRC;
359 /** Pointer to the FPU/SSE/AVX/XXXX state ring-0 mapping. */
360 R0PTRTYPE(PX86XSAVEAREA) pXStateR0;
361 /** Pointer to the FPU/SSE/AVX/XXXX state ring-3 mapping. */
362 R3PTRTYPE(PX86XSAVEAREA) pXStateR3;
363 /** The XCR0 register. */
364 uint64_t xcr0;
365 /** The mask to pass to XSAVE/XRSTOR in EDX:EAX. If zero we use
366 * FXSAVE/FXRSTOR (since bit 0 will always be set, we only need to test it). */
367 uint64_t fXStateMask;
368} CPUMHOSTCTX;
369#ifndef VBOX_FOR_DTRACE_LIB
370AssertCompileSizeAlignment(CPUMHOSTCTX, 64);
371#endif
372/** Pointer to the saved host CPU state. */
373typedef CPUMHOSTCTX *PCPUMHOSTCTX;
374
375
376/**
377 * CPUM Data (part of VM)
378 */
379typedef struct CPUM
380{
381 /** Offset from CPUM to CPUMCPU for the first CPU. */
382 uint32_t offCPUMCPU0;
383
384 /** Use flags.
385 * These flags indicates which CPU features the host uses.
386 */
387 uint32_t fHostUseFlags;
388
389 /** CR4 mask */
390 struct
391 {
392 uint32_t AndMask; /**< @todo Move these to the per-CPU structure and fix the switchers. Saves a register! */
393 uint32_t OrMask;
394 } CR4;
395
396 /** The (more) portable CPUID level. */
397 uint8_t u8PortableCpuIdLevel;
398 /** Indicates that a state restore is pending.
399 * This is used to verify load order dependencies (PGM). */
400 bool fPendingRestore;
401 uint8_t abPadding0[6];
402
403 /** XSAVE/XRTOR components we can expose to the guest mask. */
404 uint64_t fXStateGuestMask;
405 /** XSAVE/XRSTOR host mask. Only state components in this mask can be exposed
406 * to the guest. This is 0 if no XSAVE/XRSTOR bits can be exposed. */
407 uint64_t fXStateHostMask;
408
409 /** The host MXCSR mask (determined at init). */
410 uint32_t fHostMxCsrMask;
411 uint8_t abPadding1[20];
412
413 /** Host CPU feature information.
414 * Externaly visible via the VM structure, aligned on 64-byte boundrary. */
415 CPUMFEATURES HostFeatures;
416 /** Guest CPU feature information.
417 * Externaly visible via that VM structure, aligned with HostFeatures. */
418 CPUMFEATURES GuestFeatures;
419 /** Guest CPU info. */
420 CPUMINFO GuestInfo;
421
422
423 /** The standard set of CpuId leaves. */
424 CPUMCPUID aGuestCpuIdPatmStd[6];
425 /** The extended set of CpuId leaves. */
426 CPUMCPUID aGuestCpuIdPatmExt[10];
427 /** The centaur set of CpuId leaves. */
428 CPUMCPUID aGuestCpuIdPatmCentaur[4];
429
430 /** @name MSR statistics.
431 * @{ */
432 STAMCOUNTER cMsrWrites;
433 STAMCOUNTER cMsrWritesToIgnoredBits;
434 STAMCOUNTER cMsrWritesRaiseGp;
435 STAMCOUNTER cMsrWritesUnknown;
436 STAMCOUNTER cMsrReads;
437 STAMCOUNTER cMsrReadsRaiseGp;
438 STAMCOUNTER cMsrReadsUnknown;
439 /** @} */
440} CPUM;
441#ifndef VBOX_FOR_DTRACE_LIB
442AssertCompileMemberOffset(CPUM, HostFeatures, 64);
443AssertCompileMemberOffset(CPUM, GuestFeatures, 104);
444#endif
445/** Pointer to the CPUM instance data residing in the shared VM structure. */
446typedef CPUM *PCPUM;
447
448/**
449 * CPUM Data (part of VMCPU)
450 */
451typedef struct CPUMCPU
452{
453 /**
454 * Guest context.
455 * Aligned on a 64-byte boundary.
456 */
457 CPUMCTX Guest;
458
459 /**
460 * Guest context - misc MSRs
461 * Aligned on a 64-byte boundary.
462 */
463 CPUMCTXMSRS GuestMsrs;
464
465 /** Use flags.
466 * These flags indicates both what is to be used and what has been used.
467 */
468 uint32_t fUseFlags;
469
470 /** Changed flags.
471 * These flags indicates to REM (and others) which important guest
472 * registers which has been changed since last time the flags were cleared.
473 * See the CPUM_CHANGED_* defines for what we keep track of.
474 */
475 uint32_t fChanged;
476
477 /** Offset from CPUM to CPUMCPU. */
478 uint32_t offCPUM;
479
480 /** Temporary storage for the return code of the function called in the
481 * 32-64 switcher. */
482 uint32_t u32RetCode;
483
484#ifdef VBOX_WITH_VMMR0_DISABLE_LAPIC_NMI
485 /** The address of the APIC mapping, NULL if no APIC.
486 * Call CPUMR0SetLApic to update this before doing a world switch. */
487 RTHCPTR pvApicBase;
488 /** Used by the world switcher code to store which vectors needs restoring on
489 * the way back. */
490 uint32_t fApicDisVectors;
491 /** Set if the CPU has the X2APIC mode enabled.
492 * Call CPUMR0SetLApic to update this before doing a world switch. */
493 bool fX2Apic;
494#else
495 uint8_t abPadding3[(HC_ARCH_BITS == 64 ? 8 : 4) + 4 + 1];
496#endif
497
498 /** Have we entered raw-mode? */
499 bool fRawEntered;
500 /** Have we entered the recompiler? */
501 bool fRemEntered;
502 /** Whether the X86_CPUID_FEATURE_EDX_APIC and X86_CPUID_AMD_FEATURE_EDX_APIC
503 * (?) bits are visible or not. (The APIC is responsible for setting this
504 * when loading state, so we won't save it.) */
505 bool fCpuIdApicFeatureVisible;
506
507 /** Align the next member on a 64-byte boundrary. */
508 uint8_t abPadding2[64 - 16 - (HC_ARCH_BITS == 64 ? 8 : 4) - 4 - 1 - 3];
509
510 /** Saved host context. Only valid while inside RC or HM contexts.
511 * Must be aligned on a 64-byte boundary. */
512 CPUMHOSTCTX Host;
513 /** Hypervisor context. Must be aligned on a 64-byte boundary. */
514 CPUMCTX Hyper;
515
516#ifdef VBOX_WITH_CRASHDUMP_MAGIC
517 uint8_t aMagic[56];
518 uint64_t uMagic;
519#endif
520} CPUMCPU;
521/** Pointer to the CPUMCPU instance data residing in the shared VMCPU structure. */
522typedef CPUMCPU *PCPUMCPU;
523
524#ifndef VBOX_FOR_DTRACE_LIB
525RT_C_DECLS_BEGIN
526
527PCPUMCPUIDLEAF cpumCpuIdGetLeaf(PVM pVM, uint32_t uLeaf);
528PCPUMCPUIDLEAF cpumCpuIdGetLeafEx(PVM pVM, uint32_t uLeaf, uint32_t uSubLeaf, bool *pfExactSubLeafHit);
529
530# ifdef IN_RING3
531int cpumR3DbgInit(PVM pVM);
532int cpumR3CpuIdExplodeFeatures(PCCPUMCPUIDLEAF paLeaves, uint32_t cLeaves, PCPUMFEATURES pFeatures);
533int cpumR3InitCpuIdAndMsrs(PVM pVM);
534void cpumR3SaveCpuId(PVM pVM, PSSMHANDLE pSSM);
535int cpumR3LoadCpuId(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion);
536int cpumR3LoadCpuIdPre32(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion);
537DECLCALLBACK(void) cpumR3CpuIdInfo(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
538
539int cpumR3DbGetCpuInfo(const char *pszName, PCPUMINFO pInfo);
540int cpumR3MsrRangesInsert(PVM pVM, PCPUMMSRRANGE *ppaMsrRanges, uint32_t *pcMsrRanges, PCCPUMMSRRANGE pNewRange);
541int cpumR3MsrApplyFudge(PVM pVM);
542int cpumR3MsrRegStats(PVM pVM);
543int cpumR3MsrStrictInitChecks(void);
544PCPUMMSRRANGE cpumLookupMsrRange(PVM pVM, uint32_t idMsr);
545# endif
546
547# ifdef IN_RC
548DECLASM(int) cpumHandleLazyFPUAsm(PCPUMCPU pCPUM);
549# endif
550
551# ifdef IN_RING0
552DECLASM(int) cpumR0SaveHostRestoreGuestFPUState(PCPUMCPU pCPUM);
553DECLASM(void) cpumR0SaveGuestRestoreHostFPUState(PCPUMCPU pCPUM);
554# if ARCH_BITS == 32 && defined(VBOX_WITH_64_BITS_GUESTS)
555DECLASM(void) cpumR0RestoreHostFPUState(PCPUMCPU pCPUM);
556# endif
557# endif
558
559# if defined(IN_RC) || defined(IN_RING0)
560DECLASM(int) cpumRZSaveHostFPUState(PCPUMCPU pCPUM);
561DECLASM(void) cpumRZSaveGuestFpuState(PCPUMCPU pCPUM, bool fLeaveFpuAccessible);
562DECLASM(void) cpumRZSaveGuestSseRegisters(PCPUMCPU pCPUM);
563DECLASM(void) cpumRZSaveGuestAvxRegisters(PCPUMCPU pCPUM);
564# endif
565
566RT_C_DECLS_END
567#endif /* !VBOX_FOR_DTRACE_LIB */
568
569/** @} */
570
571#endif
572
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