VirtualBox

source: vbox/trunk/src/VBox/VMM/include/CPUMInternal.h@ 75611

Last change on this file since 75611 was 75611, checked in by vboxsync, 6 years ago

VMM: Nested VMX: bugref:9180 Move the VMX APIC-access guest-physical page registration into IEM and got rid of the CPUM all context code that does not quite fit because we still have to declare the prototypes in the HM headers anyway, so just keep it in HM all context code for now.
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File size: 19.3 KB
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1/* $Id: CPUMInternal.h 75611 2018-11-20 11:20:25Z vboxsync $ */
2/** @file
3 * CPUM - Internal header file.
4 */
5
6/*
7 * Copyright (C) 2006-2017 Oracle Corporation
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 */
17
18#ifndef ___CPUMInternal_h
19#define ___CPUMInternal_h
20
21#ifndef VBOX_FOR_DTRACE_LIB
22# include <VBox/cdefs.h>
23# include <VBox/types.h>
24# include <VBox/vmm/stam.h>
25# include <iprt/x86.h>
26# include <VBox/vmm/pgm.h>
27#else
28# pragma D depends_on library x86.d
29# pragma D depends_on library cpumctx.d
30# pragma D depends_on library cpum.d
31
32/* Some fudging. */
33typedef uint64_t STAMCOUNTER;
34#endif
35
36
37
38
39/** @defgroup grp_cpum_int Internals
40 * @ingroup grp_cpum
41 * @internal
42 * @{
43 */
44
45/** Flags and types for CPUM fault handlers
46 * @{ */
47/** Type: Load DS */
48#define CPUM_HANDLER_DS 1
49/** Type: Load ES */
50#define CPUM_HANDLER_ES 2
51/** Type: Load FS */
52#define CPUM_HANDLER_FS 3
53/** Type: Load GS */
54#define CPUM_HANDLER_GS 4
55/** Type: IRET */
56#define CPUM_HANDLER_IRET 5
57/** Type mask. */
58#define CPUM_HANDLER_TYPEMASK 0xff
59/** If set EBP points to the CPUMCTXCORE that's being used. */
60#define CPUM_HANDLER_CTXCORE_IN_EBP RT_BIT(31)
61/** @} */
62
63
64/** Use flags (CPUM::fUseFlags).
65 * (Don't forget to sync this with CPUMInternal.mac !)
66 * @note Part of saved state.
67 * @{ */
68/** Indicates that we've saved the host FPU, SSE, whatever state and that it
69 * needs to be restored. */
70#define CPUM_USED_FPU_HOST RT_BIT(0)
71/** Indicates that we've loaded the guest FPU, SSE, whatever state and that it
72 * needs to be saved. */
73#define CPUM_USED_FPU_GUEST RT_BIT(10)
74/** Used the guest FPU, SSE or such stuff since last we were in REM.
75 * REM syncing is clearing this, lazy FPU is setting it. */
76#define CPUM_USED_FPU_SINCE_REM RT_BIT(1)
77/** The XMM state was manually restored. (AMD only) */
78#define CPUM_USED_MANUAL_XMM_RESTORE RT_BIT(2)
79
80/** Host OS is using SYSENTER and we must NULL the CS. */
81#define CPUM_USE_SYSENTER RT_BIT(3)
82/** Host OS is using SYSENTER and we must NULL the CS. */
83#define CPUM_USE_SYSCALL RT_BIT(4)
84
85/** Debug registers are used by host and that DR7 and DR6 must be saved and
86 * disabled when switching to raw-mode. */
87#define CPUM_USE_DEBUG_REGS_HOST RT_BIT(5)
88/** Records that we've saved the host DRx registers.
89 * In ring-0 this means all (DR0-7), while in raw-mode context this means DR0-3
90 * since DR6 and DR7 are covered by CPUM_USE_DEBUG_REGS_HOST. */
91#define CPUM_USED_DEBUG_REGS_HOST RT_BIT(6)
92/** Set to indicate that we should save host DR0-7 and load the hypervisor debug
93 * registers in the raw-mode world switchers. (See CPUMRecalcHyperDRx.) */
94#define CPUM_USE_DEBUG_REGS_HYPER RT_BIT(7)
95/** Used in ring-0 to indicate that we have loaded the hypervisor debug
96 * registers. */
97#define CPUM_USED_DEBUG_REGS_HYPER RT_BIT(8)
98/** Used in ring-0 to indicate that we have loaded the guest debug
99 * registers (DR0-3 and maybe DR6) for direct use by the guest.
100 * DR7 (and AMD-V DR6) are handled via the VMCB. */
101#define CPUM_USED_DEBUG_REGS_GUEST RT_BIT(9)
102
103/** Sync the FPU state on next entry (32->64 switcher only). */
104#define CPUM_SYNC_FPU_STATE RT_BIT(16)
105/** Sync the debug state on next entry (32->64 switcher only). */
106#define CPUM_SYNC_DEBUG_REGS_GUEST RT_BIT(17)
107/** Sync the debug state on next entry (32->64 switcher only).
108 * Almost the same as CPUM_USE_DEBUG_REGS_HYPER in the raw-mode switchers. */
109#define CPUM_SYNC_DEBUG_REGS_HYPER RT_BIT(18)
110/** Host CPU requires fxsave/fxrstor leaky bit handling. */
111#define CPUM_USE_FFXSR_LEAKY RT_BIT(19)
112/** Set if the VM supports long-mode. */
113#define CPUM_USE_SUPPORTS_LONGMODE RT_BIT(20)
114/** @} */
115
116
117/** @name CPUM Saved State Version.
118 * @{ */
119/** The current saved state version. */
120#define CPUM_SAVED_STATE_VERSION CPUM_SAVED_STATE_VERSION_HWVIRT_SVM
121/** The saved state version including SVM hardware virtualization state. */
122#define CPUM_SAVED_STATE_VERSION_HWVIRT_SVM 18
123/** The saved state version including XSAVE state. */
124#define CPUM_SAVED_STATE_VERSION_XSAVE 17
125/** The saved state version with good CPUID leaf count. */
126#define CPUM_SAVED_STATE_VERSION_GOOD_CPUID_COUNT 16
127/** CPUID changes with explode forgetting to update the leaf count on
128 * restore, resulting in garbage being saved restoring+saving old states). */
129#define CPUM_SAVED_STATE_VERSION_BAD_CPUID_COUNT 15
130/** The saved state version before the CPUIDs changes. */
131#define CPUM_SAVED_STATE_VERSION_PUT_STRUCT 14
132/** The saved state version before using SSMR3PutStruct. */
133#define CPUM_SAVED_STATE_VERSION_MEM 13
134/** The saved state version before introducing the MSR size field. */
135#define CPUM_SAVED_STATE_VERSION_NO_MSR_SIZE 12
136/** The saved state version of 3.2, 3.1 and 3.3 trunk before the hidden
137 * selector register change (CPUM_CHANGED_HIDDEN_SEL_REGS_INVALID). */
138#define CPUM_SAVED_STATE_VERSION_VER3_2 11
139/** The saved state version of 3.0 and 3.1 trunk before the teleportation
140 * changes. */
141#define CPUM_SAVED_STATE_VERSION_VER3_0 10
142/** The saved state version for the 2.1 trunk before the MSR changes. */
143#define CPUM_SAVED_STATE_VERSION_VER2_1_NOMSR 9
144/** The saved state version of 2.0, used for backwards compatibility. */
145#define CPUM_SAVED_STATE_VERSION_VER2_0 8
146/** The saved state version of 1.6, used for backwards compatibility. */
147#define CPUM_SAVED_STATE_VERSION_VER1_6 6
148/** @} */
149
150
151/**
152 * CPU info
153 */
154typedef struct CPUMINFO
155{
156 /** The number of MSR ranges (CPUMMSRRANGE) in the array pointed to below. */
157 uint32_t cMsrRanges;
158 /** Mask applied to ECX before looking up the MSR for a RDMSR/WRMSR
159 * instruction. Older hardware has been observed to ignore higher bits. */
160 uint32_t fMsrMask;
161
162 /** MXCSR mask. */
163 uint32_t fMxCsrMask;
164
165 /** The number of CPUID leaves (CPUMCPUIDLEAF) in the array pointed to below. */
166 uint32_t cCpuIdLeaves;
167 /** The index of the first extended CPUID leaf in the array.
168 * Set to cCpuIdLeaves if none present. */
169 uint32_t iFirstExtCpuIdLeaf;
170 /** How to handle unknown CPUID leaves. */
171 CPUMUNKNOWNCPUID enmUnknownCpuIdMethod;
172 /** For use with CPUMUNKNOWNCPUID_DEFAULTS (DB & VM),
173 * CPUMUNKNOWNCPUID_LAST_STD_LEAF (VM) and CPUMUNKNOWNCPUID_LAST_STD_LEAF_WITH_ECX (VM). */
174 CPUMCPUID DefCpuId;
175
176 /** Scalable bus frequency used for reporting other frequencies. */
177 uint64_t uScalableBusFreq;
178
179 /** Pointer to the MSR ranges (ring-0 pointer). */
180 R0PTRTYPE(PCPUMMSRRANGE) paMsrRangesR0;
181 /** Pointer to the CPUID leaves (ring-0 pointer). */
182 R0PTRTYPE(PCPUMCPUIDLEAF) paCpuIdLeavesR0;
183
184 /** Pointer to the MSR ranges (ring-3 pointer). */
185 R3PTRTYPE(PCPUMMSRRANGE) paMsrRangesR3;
186 /** Pointer to the CPUID leaves (ring-3 pointer). */
187 R3PTRTYPE(PCPUMCPUIDLEAF) paCpuIdLeavesR3;
188
189 /** Pointer to the MSR ranges (raw-mode context pointer). */
190 RCPTRTYPE(PCPUMMSRRANGE) paMsrRangesRC;
191 /** Pointer to the CPUID leaves (raw-mode context pointer). */
192 RCPTRTYPE(PCPUMCPUIDLEAF) paCpuIdLeavesRC;
193} CPUMINFO;
194/** Pointer to a CPU info structure. */
195typedef CPUMINFO *PCPUMINFO;
196/** Pointer to a const CPU info structure. */
197typedef CPUMINFO const *CPCPUMINFO;
198
199
200/**
201 * The saved host CPU state.
202 */
203typedef struct CPUMHOSTCTX
204{
205 /** General purpose register, selectors, flags and more
206 * @{ */
207#if HC_ARCH_BITS == 64
208 /** General purpose register ++
209 * { */
210 /*uint64_t rax; - scratch*/
211 uint64_t rbx;
212 /*uint64_t rcx; - scratch*/
213 /*uint64_t rdx; - scratch*/
214 uint64_t rdi;
215 uint64_t rsi;
216 uint64_t rbp;
217 uint64_t rsp;
218 /*uint64_t r8; - scratch*/
219 /*uint64_t r9; - scratch*/
220 uint64_t r10;
221 uint64_t r11;
222 uint64_t r12;
223 uint64_t r13;
224 uint64_t r14;
225 uint64_t r15;
226 /*uint64_t rip; - scratch*/
227 uint64_t rflags;
228#endif
229
230#if HC_ARCH_BITS == 32
231 /*uint32_t eax; - scratch*/
232 uint32_t ebx;
233 /*uint32_t ecx; - scratch*/
234 /*uint32_t edx; - scratch*/
235 uint32_t edi;
236 uint32_t esi;
237 uint32_t ebp;
238 X86EFLAGS eflags;
239 /*uint32_t eip; - scratch*/
240 /* lss pair! */
241 uint32_t esp;
242#endif
243 /** @} */
244
245 /** Selector registers
246 * @{ */
247 RTSEL ss;
248 RTSEL ssPadding;
249 RTSEL gs;
250 RTSEL gsPadding;
251 RTSEL fs;
252 RTSEL fsPadding;
253 RTSEL es;
254 RTSEL esPadding;
255 RTSEL ds;
256 RTSEL dsPadding;
257 RTSEL cs;
258 RTSEL csPadding;
259 /** @} */
260
261#if HC_ARCH_BITS == 32
262 /** Control registers.
263 * @{ */
264 uint32_t cr0;
265 /*uint32_t cr2; - scratch*/
266 uint32_t cr3;
267 uint32_t cr4;
268 /** The CR0 FPU state in HM mode. Can't use cr0 here because the
269 * 64-bit-on-32-bit-host world switches is using it. */
270 uint32_t cr0Fpu;
271 /** @} */
272
273 /** Debug registers.
274 * @{ */
275 uint32_t dr0;
276 uint32_t dr1;
277 uint32_t dr2;
278 uint32_t dr3;
279 uint32_t dr6;
280 uint32_t dr7;
281 /** @} */
282
283 /** Global Descriptor Table register. */
284 X86XDTR32 gdtr;
285 uint16_t gdtrPadding;
286 /** Interrupt Descriptor Table register. */
287 X86XDTR32 idtr;
288 uint16_t idtrPadding;
289 /** The task register. */
290 RTSEL ldtr;
291 RTSEL ldtrPadding;
292 /** The task register. */
293 RTSEL tr;
294 RTSEL trPadding;
295
296 /** The sysenter msr registers.
297 * This member is not used by the hypervisor context. */
298 CPUMSYSENTER SysEnter;
299
300 /** MSRs
301 * @{ */
302 uint64_t efer;
303 /** @} */
304
305 /* padding to get 64byte aligned size */
306 uint8_t auPadding[20];
307
308#elif HC_ARCH_BITS == 64
309
310 /** Control registers.
311 * @{ */
312 /** The CR0 FPU state in HM mode. */
313 uint64_t cr0;
314 /*uint64_t cr2; - scratch*/
315 uint64_t cr3;
316 uint64_t cr4;
317 uint64_t cr8;
318 /** @} */
319
320 /** Debug registers.
321 * @{ */
322 uint64_t dr0;
323 uint64_t dr1;
324 uint64_t dr2;
325 uint64_t dr3;
326 uint64_t dr6;
327 uint64_t dr7;
328 /** @} */
329
330 /** Global Descriptor Table register. */
331 X86XDTR64 gdtr;
332 uint16_t gdtrPadding;
333 /** Interrupt Descriptor Table register. */
334 X86XDTR64 idtr;
335 uint16_t idtrPadding;
336 /** The task register. */
337 RTSEL ldtr;
338 RTSEL ldtrPadding;
339 /** The task register. */
340 RTSEL tr;
341 RTSEL trPadding;
342
343 /** MSRs
344 * @{ */
345 CPUMSYSENTER SysEnter;
346 uint64_t FSbase;
347 uint64_t GSbase;
348 uint64_t efer;
349 /** @} */
350
351 /* padding to get 64byte aligned size */
352 uint8_t auPadding[4];
353
354#else
355# error HC_ARCH_BITS not defined or unsupported
356#endif
357
358 /** Pointer to the FPU/SSE/AVX/XXXX state raw-mode mapping. */
359 RCPTRTYPE(PX86XSAVEAREA) pXStateRC;
360 /** Pointer to the FPU/SSE/AVX/XXXX state ring-0 mapping. */
361 R0PTRTYPE(PX86XSAVEAREA) pXStateR0;
362 /** Pointer to the FPU/SSE/AVX/XXXX state ring-3 mapping. */
363 R3PTRTYPE(PX86XSAVEAREA) pXStateR3;
364 /** The XCR0 register. */
365 uint64_t xcr0;
366 /** The mask to pass to XSAVE/XRSTOR in EDX:EAX. If zero we use
367 * FXSAVE/FXRSTOR (since bit 0 will always be set, we only need to test it). */
368 uint64_t fXStateMask;
369} CPUMHOSTCTX;
370#ifndef VBOX_FOR_DTRACE_LIB
371AssertCompileSizeAlignment(CPUMHOSTCTX, 64);
372#endif
373/** Pointer to the saved host CPU state. */
374typedef CPUMHOSTCTX *PCPUMHOSTCTX;
375
376
377/**
378 * CPUM Data (part of VM)
379 */
380typedef struct CPUM
381{
382 /** Offset from CPUM to CPUMCPU for the first CPU. */
383 uint32_t offCPUMCPU0;
384
385 /** Use flags.
386 * These flags indicates which CPU features the host uses.
387 */
388 uint32_t fHostUseFlags;
389
390 /** CR4 mask */
391 struct
392 {
393 uint32_t AndMask; /**< @todo Move these to the per-CPU structure and fix the switchers. Saves a register! */
394 uint32_t OrMask;
395 } CR4;
396
397 /** The (more) portable CPUID level. */
398 uint8_t u8PortableCpuIdLevel;
399 /** Indicates that a state restore is pending.
400 * This is used to verify load order dependencies (PGM). */
401 bool fPendingRestore;
402 uint8_t abPadding0[6];
403
404 /** XSAVE/XRTOR components we can expose to the guest mask. */
405 uint64_t fXStateGuestMask;
406 /** XSAVE/XRSTOR host mask. Only state components in this mask can be exposed
407 * to the guest. This is 0 if no XSAVE/XRSTOR bits can be exposed. */
408 uint64_t fXStateHostMask;
409
410 /** The host MXCSR mask (determined at init). */
411 uint32_t fHostMxCsrMask;
412 uint8_t abPadding1[20];
413
414 /** Host CPU feature information.
415 * Externaly visible via the VM structure, aligned on 64-byte boundrary. */
416 CPUMFEATURES HostFeatures;
417 /** Guest CPU feature information.
418 * Externaly visible via that VM structure, aligned with HostFeatures. */
419 CPUMFEATURES GuestFeatures;
420 /** Guest CPU info. */
421 CPUMINFO GuestInfo;
422
423 /** The standard set of CpuId leaves. */
424 CPUMCPUID aGuestCpuIdPatmStd[6];
425 /** The extended set of CpuId leaves. */
426 CPUMCPUID aGuestCpuIdPatmExt[10];
427 /** The centaur set of CpuId leaves. */
428 CPUMCPUID aGuestCpuIdPatmCentaur[4];
429
430 /** @name MSR statistics.
431 * @{ */
432 STAMCOUNTER cMsrWrites;
433 STAMCOUNTER cMsrWritesToIgnoredBits;
434 STAMCOUNTER cMsrWritesRaiseGp;
435 STAMCOUNTER cMsrWritesUnknown;
436 STAMCOUNTER cMsrReads;
437 STAMCOUNTER cMsrReadsRaiseGp;
438 STAMCOUNTER cMsrReadsUnknown;
439 /** @} */
440} CPUM;
441#ifndef VBOX_FOR_DTRACE_LIB
442AssertCompileMemberOffset(CPUM, HostFeatures, 64);
443AssertCompileMemberOffset(CPUM, GuestFeatures, 112);
444#endif
445/** Pointer to the CPUM instance data residing in the shared VM structure. */
446typedef CPUM *PCPUM;
447
448/**
449 * CPUM Data (part of VMCPU)
450 */
451typedef struct CPUMCPU
452{
453 /**
454 * Guest context.
455 * Aligned on a 64-byte boundary.
456 */
457 CPUMCTX Guest;
458
459 /**
460 * Guest context - misc MSRs
461 * Aligned on a 64-byte boundary.
462 */
463 CPUMCTXMSRS GuestMsrs;
464
465 /** Use flags.
466 * These flags indicates both what is to be used and what has been used.
467 */
468 uint32_t fUseFlags;
469
470 /** Changed flags.
471 * These flags indicates to REM (and others) which important guest
472 * registers which has been changed since last time the flags were cleared.
473 * See the CPUM_CHANGED_* defines for what we keep track of.
474 */
475 uint32_t fChanged;
476
477 /** Offset from CPUM to CPUMCPU. */
478 uint32_t offCPUM;
479
480 /** Temporary storage for the return code of the function called in the
481 * 32-64 switcher. */
482 uint32_t u32RetCode;
483
484#ifdef VBOX_WITH_VMMR0_DISABLE_LAPIC_NMI
485 /** The address of the APIC mapping, NULL if no APIC.
486 * Call CPUMR0SetLApic to update this before doing a world switch. */
487 RTHCPTR pvApicBase;
488 /** Used by the world switcher code to store which vectors needs restoring on
489 * the way back. */
490 uint32_t fApicDisVectors;
491 /** Set if the CPU has the X2APIC mode enabled.
492 * Call CPUMR0SetLApic to update this before doing a world switch. */
493 bool fX2Apic;
494#else
495 uint8_t abPadding3[(HC_ARCH_BITS == 64 ? 8 : 4) + 4 + 1];
496#endif
497
498 /** Have we entered raw-mode? */
499 bool fRawEntered;
500 /** Have we entered the recompiler? */
501 bool fRemEntered;
502 /** Whether the X86_CPUID_FEATURE_EDX_APIC and X86_CPUID_AMD_FEATURE_EDX_APIC
503 * (?) bits are visible or not. (The APIC is responsible for setting this
504 * when loading state, so we won't save it.) */
505 bool fCpuIdApicFeatureVisible;
506
507 /** Align the next member on a 64-byte boundrary. */
508 uint8_t abPadding2[64 - 16 - (HC_ARCH_BITS == 64 ? 8 : 4) - 4 - 1 - 3];
509
510 /** Saved host context. Only valid while inside RC or HM contexts.
511 * Must be aligned on a 64-byte boundary. */
512 CPUMHOSTCTX Host;
513 /** Hypervisor context. Must be aligned on a 64-byte boundary. */
514 CPUMCTX Hyper;
515
516#ifdef VBOX_WITH_CRASHDUMP_MAGIC
517 uint8_t aMagic[56];
518 uint64_t uMagic;
519#endif
520} CPUMCPU;
521/** Pointer to the CPUMCPU instance data residing in the shared VMCPU structure. */
522typedef CPUMCPU *PCPUMCPU;
523
524#ifndef VBOX_FOR_DTRACE_LIB
525RT_C_DECLS_BEGIN
526
527PCPUMCPUIDLEAF cpumCpuIdGetLeaf(PVM pVM, uint32_t uLeaf);
528PCPUMCPUIDLEAF cpumCpuIdGetLeafEx(PVM pVM, uint32_t uLeaf, uint32_t uSubLeaf, bool *pfExactSubLeafHit);
529
530# ifdef IN_RING3
531int cpumR3DbgInit(PVM pVM);
532int cpumR3CpuIdExplodeFeatures(PCCPUMCPUIDLEAF paLeaves, uint32_t cLeaves, PCPUMFEATURES pFeatures);
533int cpumR3InitCpuIdAndMsrs(PVM pVM);
534void cpumR3SaveCpuId(PVM pVM, PSSMHANDLE pSSM);
535int cpumR3LoadCpuId(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion);
536int cpumR3LoadCpuIdPre32(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion);
537DECLCALLBACK(void) cpumR3CpuIdInfo(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
538
539int cpumR3DbGetCpuInfo(const char *pszName, PCPUMINFO pInfo);
540int cpumR3MsrRangesInsert(PVM pVM, PCPUMMSRRANGE *ppaMsrRanges, uint32_t *pcMsrRanges, PCCPUMMSRRANGE pNewRange);
541int cpumR3MsrApplyFudge(PVM pVM);
542int cpumR3MsrRegStats(PVM pVM);
543int cpumR3MsrStrictInitChecks(void);
544PCPUMMSRRANGE cpumLookupMsrRange(PVM pVM, uint32_t idMsr);
545# endif
546
547# ifdef IN_RC
548DECLASM(int) cpumHandleLazyFPUAsm(PCPUMCPU pCPUM);
549# endif
550
551# ifdef IN_RING0
552DECLASM(int) cpumR0SaveHostRestoreGuestFPUState(PCPUMCPU pCPUM);
553DECLASM(void) cpumR0SaveGuestRestoreHostFPUState(PCPUMCPU pCPUM);
554# if ARCH_BITS == 32 && defined(VBOX_WITH_64_BITS_GUESTS)
555DECLASM(void) cpumR0RestoreHostFPUState(PCPUMCPU pCPUM);
556# endif
557# endif
558
559# if defined(IN_RC) || defined(IN_RING0)
560DECLASM(int) cpumRZSaveHostFPUState(PCPUMCPU pCPUM);
561DECLASM(void) cpumRZSaveGuestFpuState(PCPUMCPU pCPUM, bool fLeaveFpuAccessible);
562DECLASM(void) cpumRZSaveGuestSseRegisters(PCPUMCPU pCPUM);
563DECLASM(void) cpumRZSaveGuestAvxRegisters(PCPUMCPU pCPUM);
564# endif
565
566RT_C_DECLS_END
567#endif /* !VBOX_FOR_DTRACE_LIB */
568
569/** @} */
570
571#endif
572
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