VirtualBox

source: vbox/trunk/src/VBox/VMM/include/CPUMInternal.h@ 77922

Last change on this file since 77922 was 76678, checked in by vboxsync, 6 years ago

Port r124260, r124263, r124271, r124273, r124277, r124278, r124279, r124284, r124285, r124286, r124287, r124288, r124289 and r124290 (Ported fixes over from 5.2, see bugref:9179 for more information)
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1/* $Id: CPUMInternal.h 76678 2019-01-07 13:48:16Z vboxsync $ */
2/** @file
3 * CPUM - Internal header file.
4 */
5
6/*
7 * Copyright (C) 2006-2019 Oracle Corporation
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 */
17
18#ifndef VMM_INCLUDED_SRC_include_CPUMInternal_h
19#define VMM_INCLUDED_SRC_include_CPUMInternal_h
20#ifndef RT_WITHOUT_PRAGMA_ONCE
21# pragma once
22#endif
23
24#ifndef VBOX_FOR_DTRACE_LIB
25# include <VBox/cdefs.h>
26# include <VBox/types.h>
27# include <VBox/vmm/stam.h>
28# include <iprt/x86.h>
29# include <VBox/vmm/pgm.h>
30#else
31# pragma D depends_on library x86.d
32# pragma D depends_on library cpumctx.d
33# pragma D depends_on library cpum.d
34
35/* Some fudging. */
36typedef uint64_t STAMCOUNTER;
37#endif
38
39
40
41
42/** @defgroup grp_cpum_int Internals
43 * @ingroup grp_cpum
44 * @internal
45 * @{
46 */
47
48/** Flags and types for CPUM fault handlers
49 * @{ */
50/** Type: Load DS */
51#define CPUM_HANDLER_DS 1
52/** Type: Load ES */
53#define CPUM_HANDLER_ES 2
54/** Type: Load FS */
55#define CPUM_HANDLER_FS 3
56/** Type: Load GS */
57#define CPUM_HANDLER_GS 4
58/** Type: IRET */
59#define CPUM_HANDLER_IRET 5
60/** Type mask. */
61#define CPUM_HANDLER_TYPEMASK 0xff
62/** If set EBP points to the CPUMCTXCORE that's being used. */
63#define CPUM_HANDLER_CTXCORE_IN_EBP RT_BIT(31)
64/** @} */
65
66
67/** Use flags (CPUM::fUseFlags).
68 * (Don't forget to sync this with CPUMInternal.mac !)
69 * @note Part of saved state.
70 * @{ */
71/** Indicates that we've saved the host FPU, SSE, whatever state and that it
72 * needs to be restored. */
73#define CPUM_USED_FPU_HOST RT_BIT(0)
74/** Indicates that we've loaded the guest FPU, SSE, whatever state and that it
75 * needs to be saved. */
76#define CPUM_USED_FPU_GUEST RT_BIT(10)
77/** Used the guest FPU, SSE or such stuff since last we were in REM.
78 * REM syncing is clearing this, lazy FPU is setting it. */
79#define CPUM_USED_FPU_SINCE_REM RT_BIT(1)
80/** The XMM state was manually restored. (AMD only) */
81#define CPUM_USED_MANUAL_XMM_RESTORE RT_BIT(2)
82
83/** Host OS is using SYSENTER and we must NULL the CS. */
84#define CPUM_USE_SYSENTER RT_BIT(3)
85/** Host OS is using SYSENTER and we must NULL the CS. */
86#define CPUM_USE_SYSCALL RT_BIT(4)
87
88/** Debug registers are used by host and that DR7 and DR6 must be saved and
89 * disabled when switching to raw-mode. */
90#define CPUM_USE_DEBUG_REGS_HOST RT_BIT(5)
91/** Records that we've saved the host DRx registers.
92 * In ring-0 this means all (DR0-7), while in raw-mode context this means DR0-3
93 * since DR6 and DR7 are covered by CPUM_USE_DEBUG_REGS_HOST. */
94#define CPUM_USED_DEBUG_REGS_HOST RT_BIT(6)
95/** Set to indicate that we should save host DR0-7 and load the hypervisor debug
96 * registers in the raw-mode world switchers. (See CPUMRecalcHyperDRx.) */
97#define CPUM_USE_DEBUG_REGS_HYPER RT_BIT(7)
98/** Used in ring-0 to indicate that we have loaded the hypervisor debug
99 * registers. */
100#define CPUM_USED_DEBUG_REGS_HYPER RT_BIT(8)
101/** Used in ring-0 to indicate that we have loaded the guest debug
102 * registers (DR0-3 and maybe DR6) for direct use by the guest.
103 * DR7 (and AMD-V DR6) are handled via the VMCB. */
104#define CPUM_USED_DEBUG_REGS_GUEST RT_BIT(9)
105
106/** Sync the FPU state on next entry (32->64 switcher only). */
107#define CPUM_SYNC_FPU_STATE RT_BIT(16)
108/** Sync the debug state on next entry (32->64 switcher only). */
109#define CPUM_SYNC_DEBUG_REGS_GUEST RT_BIT(17)
110/** Sync the debug state on next entry (32->64 switcher only).
111 * Almost the same as CPUM_USE_DEBUG_REGS_HYPER in the raw-mode switchers. */
112#define CPUM_SYNC_DEBUG_REGS_HYPER RT_BIT(18)
113/** Host CPU requires fxsave/fxrstor leaky bit handling. */
114#define CPUM_USE_FFXSR_LEAKY RT_BIT(19)
115/** Set if the VM supports long-mode. */
116#define CPUM_USE_SUPPORTS_LONGMODE RT_BIT(20)
117/** @} */
118
119
120/** @name CPUM Saved State Version.
121 * @{ */
122/** The current saved state version. */
123#define CPUM_SAVED_STATE_VERSION CPUM_SAVED_STATE_VERSION_HWVIRT_SVM
124/** The saved state version including SVM hardware virtualization state. */
125#define CPUM_SAVED_STATE_VERSION_HWVIRT_SVM 18
126/** The saved state version including XSAVE state. */
127#define CPUM_SAVED_STATE_VERSION_XSAVE 17
128/** The saved state version with good CPUID leaf count. */
129#define CPUM_SAVED_STATE_VERSION_GOOD_CPUID_COUNT 16
130/** CPUID changes with explode forgetting to update the leaf count on
131 * restore, resulting in garbage being saved restoring+saving old states). */
132#define CPUM_SAVED_STATE_VERSION_BAD_CPUID_COUNT 15
133/** The saved state version before the CPUIDs changes. */
134#define CPUM_SAVED_STATE_VERSION_PUT_STRUCT 14
135/** The saved state version before using SSMR3PutStruct. */
136#define CPUM_SAVED_STATE_VERSION_MEM 13
137/** The saved state version before introducing the MSR size field. */
138#define CPUM_SAVED_STATE_VERSION_NO_MSR_SIZE 12
139/** The saved state version of 3.2, 3.1 and 3.3 trunk before the hidden
140 * selector register change (CPUM_CHANGED_HIDDEN_SEL_REGS_INVALID). */
141#define CPUM_SAVED_STATE_VERSION_VER3_2 11
142/** The saved state version of 3.0 and 3.1 trunk before the teleportation
143 * changes. */
144#define CPUM_SAVED_STATE_VERSION_VER3_0 10
145/** The saved state version for the 2.1 trunk before the MSR changes. */
146#define CPUM_SAVED_STATE_VERSION_VER2_1_NOMSR 9
147/** The saved state version of 2.0, used for backwards compatibility. */
148#define CPUM_SAVED_STATE_VERSION_VER2_0 8
149/** The saved state version of 1.6, used for backwards compatibility. */
150#define CPUM_SAVED_STATE_VERSION_VER1_6 6
151/** @} */
152
153
154/**
155 * CPU info
156 */
157typedef struct CPUMINFO
158{
159 /** The number of MSR ranges (CPUMMSRRANGE) in the array pointed to below. */
160 uint32_t cMsrRanges;
161 /** Mask applied to ECX before looking up the MSR for a RDMSR/WRMSR
162 * instruction. Older hardware has been observed to ignore higher bits. */
163 uint32_t fMsrMask;
164
165 /** MXCSR mask. */
166 uint32_t fMxCsrMask;
167
168 /** The number of CPUID leaves (CPUMCPUIDLEAF) in the array pointed to below. */
169 uint32_t cCpuIdLeaves;
170 /** The index of the first extended CPUID leaf in the array.
171 * Set to cCpuIdLeaves if none present. */
172 uint32_t iFirstExtCpuIdLeaf;
173 /** How to handle unknown CPUID leaves. */
174 CPUMUNKNOWNCPUID enmUnknownCpuIdMethod;
175 /** For use with CPUMUNKNOWNCPUID_DEFAULTS (DB & VM),
176 * CPUMUNKNOWNCPUID_LAST_STD_LEAF (VM) and CPUMUNKNOWNCPUID_LAST_STD_LEAF_WITH_ECX (VM). */
177 CPUMCPUID DefCpuId;
178
179 /** Scalable bus frequency used for reporting other frequencies. */
180 uint64_t uScalableBusFreq;
181
182 /** Pointer to the MSR ranges (ring-0 pointer). */
183 R0PTRTYPE(PCPUMMSRRANGE) paMsrRangesR0;
184 /** Pointer to the CPUID leaves (ring-0 pointer). */
185 R0PTRTYPE(PCPUMCPUIDLEAF) paCpuIdLeavesR0;
186
187 /** Pointer to the MSR ranges (ring-3 pointer). */
188 R3PTRTYPE(PCPUMMSRRANGE) paMsrRangesR3;
189 /** Pointer to the CPUID leaves (ring-3 pointer). */
190 R3PTRTYPE(PCPUMCPUIDLEAF) paCpuIdLeavesR3;
191
192 /** Pointer to the MSR ranges (raw-mode context pointer). */
193 RCPTRTYPE(PCPUMMSRRANGE) paMsrRangesRC;
194 /** Pointer to the CPUID leaves (raw-mode context pointer). */
195 RCPTRTYPE(PCPUMCPUIDLEAF) paCpuIdLeavesRC;
196} CPUMINFO;
197/** Pointer to a CPU info structure. */
198typedef CPUMINFO *PCPUMINFO;
199/** Pointer to a const CPU info structure. */
200typedef CPUMINFO const *CPCPUMINFO;
201
202
203/**
204 * The saved host CPU state.
205 */
206typedef struct CPUMHOSTCTX
207{
208 /** General purpose register, selectors, flags and more
209 * @{ */
210#if HC_ARCH_BITS == 64
211 /** General purpose register ++
212 * { */
213 /*uint64_t rax; - scratch*/
214 uint64_t rbx;
215 /*uint64_t rcx; - scratch*/
216 /*uint64_t rdx; - scratch*/
217 uint64_t rdi;
218 uint64_t rsi;
219 uint64_t rbp;
220 uint64_t rsp;
221 /*uint64_t r8; - scratch*/
222 /*uint64_t r9; - scratch*/
223 uint64_t r10;
224 uint64_t r11;
225 uint64_t r12;
226 uint64_t r13;
227 uint64_t r14;
228 uint64_t r15;
229 /*uint64_t rip; - scratch*/
230 uint64_t rflags;
231#endif
232
233#if HC_ARCH_BITS == 32
234 /*uint32_t eax; - scratch*/
235 uint32_t ebx;
236 /*uint32_t ecx; - scratch*/
237 /*uint32_t edx; - scratch*/
238 uint32_t edi;
239 uint32_t esi;
240 uint32_t ebp;
241 X86EFLAGS eflags;
242 /*uint32_t eip; - scratch*/
243 /* lss pair! */
244 uint32_t esp;
245#endif
246 /** @} */
247
248 /** Selector registers
249 * @{ */
250 RTSEL ss;
251 RTSEL ssPadding;
252 RTSEL gs;
253 RTSEL gsPadding;
254 RTSEL fs;
255 RTSEL fsPadding;
256 RTSEL es;
257 RTSEL esPadding;
258 RTSEL ds;
259 RTSEL dsPadding;
260 RTSEL cs;
261 RTSEL csPadding;
262 /** @} */
263
264#if HC_ARCH_BITS == 32
265 /** Control registers.
266 * @{ */
267 uint32_t cr0;
268 /*uint32_t cr2; - scratch*/
269 uint32_t cr3;
270 uint32_t cr4;
271 /** The CR0 FPU state in HM mode. Can't use cr0 here because the
272 * 64-bit-on-32-bit-host world switches is using it. */
273 uint32_t cr0Fpu;
274 /** @} */
275
276 /** Debug registers.
277 * @{ */
278 uint32_t dr0;
279 uint32_t dr1;
280 uint32_t dr2;
281 uint32_t dr3;
282 uint32_t dr6;
283 uint32_t dr7;
284 /** @} */
285
286 /** Global Descriptor Table register. */
287 X86XDTR32 gdtr;
288 uint16_t gdtrPadding;
289 /** Interrupt Descriptor Table register. */
290 X86XDTR32 idtr;
291 uint16_t idtrPadding;
292 /** The task register. */
293 RTSEL ldtr;
294 RTSEL ldtrPadding;
295 /** The task register. */
296 RTSEL tr;
297 RTSEL trPadding;
298
299 /** The sysenter msr registers.
300 * This member is not used by the hypervisor context. */
301 CPUMSYSENTER SysEnter;
302
303 /** MSRs
304 * @{ */
305 uint64_t efer;
306 /** @} */
307
308 /* padding to get 64byte aligned size */
309 uint8_t auPadding[20];
310
311#elif HC_ARCH_BITS == 64
312
313 /** Control registers.
314 * @{ */
315 /** The CR0 FPU state in HM mode. */
316 uint64_t cr0;
317 /*uint64_t cr2; - scratch*/
318 uint64_t cr3;
319 uint64_t cr4;
320 uint64_t cr8;
321 /** @} */
322
323 /** Debug registers.
324 * @{ */
325 uint64_t dr0;
326 uint64_t dr1;
327 uint64_t dr2;
328 uint64_t dr3;
329 uint64_t dr6;
330 uint64_t dr7;
331 /** @} */
332
333 /** Global Descriptor Table register. */
334 X86XDTR64 gdtr;
335 uint16_t gdtrPadding;
336 /** Interrupt Descriptor Table register. */
337 X86XDTR64 idtr;
338 uint16_t idtrPadding;
339 /** The task register. */
340 RTSEL ldtr;
341 RTSEL ldtrPadding;
342 /** The task register. */
343 RTSEL tr;
344 RTSEL trPadding;
345
346 /** MSRs
347 * @{ */
348 CPUMSYSENTER SysEnter;
349 uint64_t FSbase;
350 uint64_t GSbase;
351 uint64_t efer;
352 /** @} */
353
354 /* padding to get 64byte aligned size */
355 uint8_t auPadding[4];
356
357#else
358# error HC_ARCH_BITS not defined or unsupported
359#endif
360
361 /** Pointer to the FPU/SSE/AVX/XXXX state raw-mode mapping. */
362 RCPTRTYPE(PX86XSAVEAREA) pXStateRC;
363 /** Pointer to the FPU/SSE/AVX/XXXX state ring-0 mapping. */
364 R0PTRTYPE(PX86XSAVEAREA) pXStateR0;
365 /** Pointer to the FPU/SSE/AVX/XXXX state ring-3 mapping. */
366 R3PTRTYPE(PX86XSAVEAREA) pXStateR3;
367 /** The XCR0 register. */
368 uint64_t xcr0;
369 /** The mask to pass to XSAVE/XRSTOR in EDX:EAX. If zero we use
370 * FXSAVE/FXRSTOR (since bit 0 will always be set, we only need to test it). */
371 uint64_t fXStateMask;
372} CPUMHOSTCTX;
373#ifndef VBOX_FOR_DTRACE_LIB
374AssertCompileSizeAlignment(CPUMHOSTCTX, 64);
375#endif
376/** Pointer to the saved host CPU state. */
377typedef CPUMHOSTCTX *PCPUMHOSTCTX;
378
379
380/**
381 * CPUM Data (part of VM)
382 */
383typedef struct CPUM
384{
385 /** Offset from CPUM to CPUMCPU for the first CPU. */
386 uint32_t offCPUMCPU0;
387
388 /** Use flags.
389 * These flags indicates which CPU features the host uses.
390 */
391 uint32_t fHostUseFlags;
392
393 /** CR4 mask */
394 struct
395 {
396 uint32_t AndMask; /**< @todo Move these to the per-CPU structure and fix the switchers. Saves a register! */
397 uint32_t OrMask;
398 } CR4;
399
400 /** The (more) portable CPUID level. */
401 uint8_t u8PortableCpuIdLevel;
402 /** Indicates that a state restore is pending.
403 * This is used to verify load order dependencies (PGM). */
404 bool fPendingRestore;
405 uint8_t abPadding0[6];
406
407 /** XSAVE/XRTOR components we can expose to the guest mask. */
408 uint64_t fXStateGuestMask;
409 /** XSAVE/XRSTOR host mask. Only state components in this mask can be exposed
410 * to the guest. This is 0 if no XSAVE/XRSTOR bits can be exposed. */
411 uint64_t fXStateHostMask;
412
413 /** The host MXCSR mask (determined at init). */
414 uint32_t fHostMxCsrMask;
415 uint8_t abPadding1[20];
416
417 /** Host CPU feature information.
418 * Externaly visible via the VM structure, aligned on 64-byte boundrary. */
419 CPUMFEATURES HostFeatures;
420 /** Guest CPU feature information.
421 * Externaly visible via that VM structure, aligned with HostFeatures. */
422 CPUMFEATURES GuestFeatures;
423 /** Guest CPU info. */
424 CPUMINFO GuestInfo;
425
426 /** The standard set of CpuId leaves. */
427 CPUMCPUID aGuestCpuIdPatmStd[6];
428 /** The extended set of CpuId leaves. */
429 CPUMCPUID aGuestCpuIdPatmExt[10];
430 /** The centaur set of CpuId leaves. */
431 CPUMCPUID aGuestCpuIdPatmCentaur[4];
432
433 /** @name MSR statistics.
434 * @{ */
435 STAMCOUNTER cMsrWrites;
436 STAMCOUNTER cMsrWritesToIgnoredBits;
437 STAMCOUNTER cMsrWritesRaiseGp;
438 STAMCOUNTER cMsrWritesUnknown;
439 STAMCOUNTER cMsrReads;
440 STAMCOUNTER cMsrReadsRaiseGp;
441 STAMCOUNTER cMsrReadsUnknown;
442 /** @} */
443} CPUM;
444#ifndef VBOX_FOR_DTRACE_LIB
445AssertCompileMemberOffset(CPUM, HostFeatures, 64);
446AssertCompileMemberOffset(CPUM, GuestFeatures, 112);
447#endif
448/** Pointer to the CPUM instance data residing in the shared VM structure. */
449typedef CPUM *PCPUM;
450
451/**
452 * CPUM Data (part of VMCPU)
453 */
454typedef struct CPUMCPU
455{
456 /**
457 * Guest context.
458 * Aligned on a 64-byte boundary.
459 */
460 CPUMCTX Guest;
461
462 /**
463 * Guest context - misc MSRs
464 * Aligned on a 64-byte boundary.
465 */
466 CPUMCTXMSRS GuestMsrs;
467
468 /** Use flags.
469 * These flags indicates both what is to be used and what has been used.
470 */
471 uint32_t fUseFlags;
472
473 /** Changed flags.
474 * These flags indicates to REM (and others) which important guest
475 * registers which has been changed since last time the flags were cleared.
476 * See the CPUM_CHANGED_* defines for what we keep track of.
477 */
478 uint32_t fChanged;
479
480 /** Offset from CPUM to CPUMCPU. */
481 uint32_t offCPUM;
482
483 /** Temporary storage for the return code of the function called in the
484 * 32-64 switcher. */
485 uint32_t u32RetCode;
486
487#ifdef VBOX_WITH_VMMR0_DISABLE_LAPIC_NMI
488 /** The address of the APIC mapping, NULL if no APIC.
489 * Call CPUMR0SetLApic to update this before doing a world switch. */
490 RTHCPTR pvApicBase;
491 /** Used by the world switcher code to store which vectors needs restoring on
492 * the way back. */
493 uint32_t fApicDisVectors;
494 /** Set if the CPU has the X2APIC mode enabled.
495 * Call CPUMR0SetLApic to update this before doing a world switch. */
496 bool fX2Apic;
497#else
498 uint8_t abPadding3[(HC_ARCH_BITS == 64 ? 8 : 4) + 4 + 1];
499#endif
500
501 /** Have we entered raw-mode? */
502 bool fRawEntered;
503 /** Have we entered the recompiler? */
504 bool fRemEntered;
505 /** Whether the X86_CPUID_FEATURE_EDX_APIC and X86_CPUID_AMD_FEATURE_EDX_APIC
506 * (?) bits are visible or not. (The APIC is responsible for setting this
507 * when loading state, so we won't save it.) */
508 bool fCpuIdApicFeatureVisible;
509
510 /** Align the next member on a 64-byte boundrary. */
511 uint8_t abPadding2[64 - 16 - (HC_ARCH_BITS == 64 ? 8 : 4) - 4 - 1 - 3];
512
513 /** Saved host context. Only valid while inside RC or HM contexts.
514 * Must be aligned on a 64-byte boundary. */
515 CPUMHOSTCTX Host;
516 /** Hypervisor context. Must be aligned on a 64-byte boundary. */
517 CPUMCTX Hyper;
518
519#ifdef VBOX_WITH_CRASHDUMP_MAGIC
520 uint8_t aMagic[56];
521 uint64_t uMagic;
522#endif
523} CPUMCPU;
524/** Pointer to the CPUMCPU instance data residing in the shared VMCPU structure. */
525typedef CPUMCPU *PCPUMCPU;
526
527#ifndef VBOX_FOR_DTRACE_LIB
528RT_C_DECLS_BEGIN
529
530PCPUMCPUIDLEAF cpumCpuIdGetLeaf(PVM pVM, uint32_t uLeaf);
531PCPUMCPUIDLEAF cpumCpuIdGetLeafEx(PVM pVM, uint32_t uLeaf, uint32_t uSubLeaf, bool *pfExactSubLeafHit);
532
533# ifdef IN_RING3
534int cpumR3DbgInit(PVM pVM);
535int cpumR3CpuIdExplodeFeatures(PCCPUMCPUIDLEAF paLeaves, uint32_t cLeaves, PCCPUMMSRS pMsrs, PCPUMFEATURES pFeatures);
536int cpumR3InitCpuIdAndMsrs(PVM pVM, PCCPUMMSRS pHostMsrs);
537void cpumR3InitVmxGuestFeaturesAndMsrs(PVM pVM, PCVMXMSRS pHostVmxMsrs, PVMXMSRS pGuestVmxMsrs);
538void cpumR3SaveCpuId(PVM pVM, PSSMHANDLE pSSM);
539int cpumR3LoadCpuId(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion, PCCPUMMSRS pGuestMsrs);
540int cpumR3LoadCpuIdPre32(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion);
541DECLCALLBACK(void) cpumR3CpuIdInfo(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
542
543int cpumR3DbGetCpuInfo(const char *pszName, PCPUMINFO pInfo);
544int cpumR3MsrRangesInsert(PVM pVM, PCPUMMSRRANGE *ppaMsrRanges, uint32_t *pcMsrRanges, PCCPUMMSRRANGE pNewRange);
545int cpumR3MsrReconcileWithCpuId(PVM pVM);
546int cpumR3MsrApplyFudge(PVM pVM);
547int cpumR3MsrRegStats(PVM pVM);
548int cpumR3MsrStrictInitChecks(void);
549PCPUMMSRRANGE cpumLookupMsrRange(PVM pVM, uint32_t idMsr);
550# endif
551
552# ifdef IN_RC
553DECLASM(int) cpumHandleLazyFPUAsm(PCPUMCPU pCPUM);
554# endif
555
556# ifdef IN_RING0
557DECLASM(int) cpumR0SaveHostRestoreGuestFPUState(PCPUMCPU pCPUM);
558DECLASM(void) cpumR0SaveGuestRestoreHostFPUState(PCPUMCPU pCPUM);
559# if ARCH_BITS == 32 && defined(VBOX_WITH_64_BITS_GUESTS)
560DECLASM(void) cpumR0RestoreHostFPUState(PCPUMCPU pCPUM);
561# endif
562# endif
563
564# if defined(IN_RC) || defined(IN_RING0)
565DECLASM(int) cpumRZSaveHostFPUState(PCPUMCPU pCPUM);
566DECLASM(void) cpumRZSaveGuestFpuState(PCPUMCPU pCPUM, bool fLeaveFpuAccessible);
567DECLASM(void) cpumRZSaveGuestSseRegisters(PCPUMCPU pCPUM);
568DECLASM(void) cpumRZSaveGuestAvxRegisters(PCPUMCPU pCPUM);
569# endif
570
571RT_C_DECLS_END
572#endif /* !VBOX_FOR_DTRACE_LIB */
573
574/** @} */
575
576#endif /* !VMM_INCLUDED_SRC_include_CPUMInternal_h */
577
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