VirtualBox

source: vbox/trunk/src/VBox/VMM/include/CPUMInternal.h@ 78402

Last change on this file since 78402 was 78220, checked in by vboxsync, 6 years ago

VMM: Nested VMX: bugref:9180 Hardware-assisted nested VT-x infrastructure changes and VM-entry implementation.
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1/* $Id: CPUMInternal.h 78220 2019-04-20 04:08:44Z vboxsync $ */
2/** @file
3 * CPUM - Internal header file.
4 */
5
6/*
7 * Copyright (C) 2006-2019 Oracle Corporation
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 */
17
18#ifndef VMM_INCLUDED_SRC_include_CPUMInternal_h
19#define VMM_INCLUDED_SRC_include_CPUMInternal_h
20#ifndef RT_WITHOUT_PRAGMA_ONCE
21# pragma once
22#endif
23
24#ifndef VBOX_FOR_DTRACE_LIB
25# include <VBox/cdefs.h>
26# include <VBox/types.h>
27# include <VBox/vmm/stam.h>
28# include <iprt/x86.h>
29# include <VBox/vmm/pgm.h>
30#else
31# pragma D depends_on library x86.d
32# pragma D depends_on library cpumctx.d
33# pragma D depends_on library cpum.d
34
35/* Some fudging. */
36typedef uint64_t STAMCOUNTER;
37#endif
38
39
40
41
42/** @defgroup grp_cpum_int Internals
43 * @ingroup grp_cpum
44 * @internal
45 * @{
46 */
47
48/** Flags and types for CPUM fault handlers
49 * @{ */
50/** Type: Load DS */
51#define CPUM_HANDLER_DS 1
52/** Type: Load ES */
53#define CPUM_HANDLER_ES 2
54/** Type: Load FS */
55#define CPUM_HANDLER_FS 3
56/** Type: Load GS */
57#define CPUM_HANDLER_GS 4
58/** Type: IRET */
59#define CPUM_HANDLER_IRET 5
60/** Type mask. */
61#define CPUM_HANDLER_TYPEMASK 0xff
62/** If set EBP points to the CPUMCTXCORE that's being used. */
63#define CPUM_HANDLER_CTXCORE_IN_EBP RT_BIT(31)
64/** @} */
65
66
67/** Use flags (CPUM::fUseFlags).
68 * (Don't forget to sync this with CPUMInternal.mac !)
69 * @note Part of saved state.
70 * @{ */
71/** Indicates that we've saved the host FPU, SSE, whatever state and that it
72 * needs to be restored. */
73#define CPUM_USED_FPU_HOST RT_BIT(0)
74/** Indicates that we've loaded the guest FPU, SSE, whatever state and that it
75 * needs to be saved. */
76#define CPUM_USED_FPU_GUEST RT_BIT(10)
77/** Used the guest FPU, SSE or such stuff since last we were in REM.
78 * REM syncing is clearing this, lazy FPU is setting it. */
79#define CPUM_USED_FPU_SINCE_REM RT_BIT(1)
80/** The XMM state was manually restored. (AMD only) */
81#define CPUM_USED_MANUAL_XMM_RESTORE RT_BIT(2)
82
83/** Host OS is using SYSENTER and we must NULL the CS. */
84#define CPUM_USE_SYSENTER RT_BIT(3)
85/** Host OS is using SYSENTER and we must NULL the CS. */
86#define CPUM_USE_SYSCALL RT_BIT(4)
87
88/** Debug registers are used by host and that DR7 and DR6 must be saved and
89 * disabled when switching to raw-mode. */
90#define CPUM_USE_DEBUG_REGS_HOST RT_BIT(5)
91/** Records that we've saved the host DRx registers.
92 * In ring-0 this means all (DR0-7), while in raw-mode context this means DR0-3
93 * since DR6 and DR7 are covered by CPUM_USE_DEBUG_REGS_HOST. */
94#define CPUM_USED_DEBUG_REGS_HOST RT_BIT(6)
95/** Set to indicate that we should save host DR0-7 and load the hypervisor debug
96 * registers in the raw-mode world switchers. (See CPUMRecalcHyperDRx.) */
97#define CPUM_USE_DEBUG_REGS_HYPER RT_BIT(7)
98/** Used in ring-0 to indicate that we have loaded the hypervisor debug
99 * registers. */
100#define CPUM_USED_DEBUG_REGS_HYPER RT_BIT(8)
101/** Used in ring-0 to indicate that we have loaded the guest debug
102 * registers (DR0-3 and maybe DR6) for direct use by the guest.
103 * DR7 (and AMD-V DR6) are handled via the VMCB. */
104#define CPUM_USED_DEBUG_REGS_GUEST RT_BIT(9)
105
106/** Sync the FPU state on next entry (32->64 switcher only). */
107#define CPUM_SYNC_FPU_STATE RT_BIT(16)
108/** Sync the debug state on next entry (32->64 switcher only). */
109#define CPUM_SYNC_DEBUG_REGS_GUEST RT_BIT(17)
110/** Sync the debug state on next entry (32->64 switcher only).
111 * Almost the same as CPUM_USE_DEBUG_REGS_HYPER in the raw-mode switchers. */
112#define CPUM_SYNC_DEBUG_REGS_HYPER RT_BIT(18)
113/** Host CPU requires fxsave/fxrstor leaky bit handling. */
114#define CPUM_USE_FFXSR_LEAKY RT_BIT(19)
115/** Set if the VM supports long-mode. */
116#define CPUM_USE_SUPPORTS_LONGMODE RT_BIT(20)
117/** @} */
118
119
120/** @name CPUM Saved State Version.
121 * @{ */
122/** The current saved state version. */
123#define CPUM_SAVED_STATE_VERSION CPUM_SAVED_STATE_VERSION_HWVIRT_VMX_IEM
124/** The saved state version including VMX hardware virtualization state (IEM only
125 * execution). */
126#define CPUM_SAVED_STATE_VERSION_HWVIRT_VMX_IEM 19
127/** The saved state version including SVM hardware virtualization state. */
128#define CPUM_SAVED_STATE_VERSION_HWVIRT_SVM 18
129/** The saved state version including XSAVE state. */
130#define CPUM_SAVED_STATE_VERSION_XSAVE 17
131/** The saved state version with good CPUID leaf count. */
132#define CPUM_SAVED_STATE_VERSION_GOOD_CPUID_COUNT 16
133/** CPUID changes with explode forgetting to update the leaf count on
134 * restore, resulting in garbage being saved restoring+saving old states). */
135#define CPUM_SAVED_STATE_VERSION_BAD_CPUID_COUNT 15
136/** The saved state version before the CPUIDs changes. */
137#define CPUM_SAVED_STATE_VERSION_PUT_STRUCT 14
138/** The saved state version before using SSMR3PutStruct. */
139#define CPUM_SAVED_STATE_VERSION_MEM 13
140/** The saved state version before introducing the MSR size field. */
141#define CPUM_SAVED_STATE_VERSION_NO_MSR_SIZE 12
142/** The saved state version of 3.2, 3.1 and 3.3 trunk before the hidden
143 * selector register change (CPUM_CHANGED_HIDDEN_SEL_REGS_INVALID). */
144#define CPUM_SAVED_STATE_VERSION_VER3_2 11
145/** The saved state version of 3.0 and 3.1 trunk before the teleportation
146 * changes. */
147#define CPUM_SAVED_STATE_VERSION_VER3_0 10
148/** The saved state version for the 2.1 trunk before the MSR changes. */
149#define CPUM_SAVED_STATE_VERSION_VER2_1_NOMSR 9
150/** The saved state version of 2.0, used for backwards compatibility. */
151#define CPUM_SAVED_STATE_VERSION_VER2_0 8
152/** The saved state version of 1.6, used for backwards compatibility. */
153#define CPUM_SAVED_STATE_VERSION_VER1_6 6
154/** @} */
155
156
157/**
158 * CPU info
159 */
160typedef struct CPUMINFO
161{
162 /** The number of MSR ranges (CPUMMSRRANGE) in the array pointed to below. */
163 uint32_t cMsrRanges;
164 /** Mask applied to ECX before looking up the MSR for a RDMSR/WRMSR
165 * instruction. Older hardware has been observed to ignore higher bits. */
166 uint32_t fMsrMask;
167
168 /** MXCSR mask. */
169 uint32_t fMxCsrMask;
170
171 /** The number of CPUID leaves (CPUMCPUIDLEAF) in the array pointed to below. */
172 uint32_t cCpuIdLeaves;
173 /** The index of the first extended CPUID leaf in the array.
174 * Set to cCpuIdLeaves if none present. */
175 uint32_t iFirstExtCpuIdLeaf;
176 /** How to handle unknown CPUID leaves. */
177 CPUMUNKNOWNCPUID enmUnknownCpuIdMethod;
178 /** For use with CPUMUNKNOWNCPUID_DEFAULTS (DB & VM),
179 * CPUMUNKNOWNCPUID_LAST_STD_LEAF (VM) and CPUMUNKNOWNCPUID_LAST_STD_LEAF_WITH_ECX (VM). */
180 CPUMCPUID DefCpuId;
181
182 /** Scalable bus frequency used for reporting other frequencies. */
183 uint64_t uScalableBusFreq;
184
185 /** Pointer to the MSR ranges (ring-0 pointer). */
186 R0PTRTYPE(PCPUMMSRRANGE) paMsrRangesR0;
187 /** Pointer to the CPUID leaves (ring-0 pointer). */
188 R0PTRTYPE(PCPUMCPUIDLEAF) paCpuIdLeavesR0;
189
190 /** Pointer to the MSR ranges (ring-3 pointer). */
191 R3PTRTYPE(PCPUMMSRRANGE) paMsrRangesR3;
192 /** Pointer to the CPUID leaves (ring-3 pointer). */
193 R3PTRTYPE(PCPUMCPUIDLEAF) paCpuIdLeavesR3;
194
195 /** Pointer to the MSR ranges (raw-mode context pointer). */
196 RCPTRTYPE(PCPUMMSRRANGE) paMsrRangesRC;
197 /** Pointer to the CPUID leaves (raw-mode context pointer). */
198 RCPTRTYPE(PCPUMCPUIDLEAF) paCpuIdLeavesRC;
199} CPUMINFO;
200/** Pointer to a CPU info structure. */
201typedef CPUMINFO *PCPUMINFO;
202/** Pointer to a const CPU info structure. */
203typedef CPUMINFO const *CPCPUMINFO;
204
205
206/**
207 * The saved host CPU state.
208 */
209typedef struct CPUMHOSTCTX
210{
211 /** General purpose register, selectors, flags and more
212 * @{ */
213#if HC_ARCH_BITS == 64
214 /** General purpose register ++
215 * { */
216 /*uint64_t rax; - scratch*/
217 uint64_t rbx;
218 /*uint64_t rcx; - scratch*/
219 /*uint64_t rdx; - scratch*/
220 uint64_t rdi;
221 uint64_t rsi;
222 uint64_t rbp;
223 uint64_t rsp;
224 /*uint64_t r8; - scratch*/
225 /*uint64_t r9; - scratch*/
226 uint64_t r10;
227 uint64_t r11;
228 uint64_t r12;
229 uint64_t r13;
230 uint64_t r14;
231 uint64_t r15;
232 /*uint64_t rip; - scratch*/
233 uint64_t rflags;
234#endif
235
236#if HC_ARCH_BITS == 32
237 /*uint32_t eax; - scratch*/
238 uint32_t ebx;
239 /*uint32_t ecx; - scratch*/
240 /*uint32_t edx; - scratch*/
241 uint32_t edi;
242 uint32_t esi;
243 uint32_t ebp;
244 X86EFLAGS eflags;
245 /*uint32_t eip; - scratch*/
246 /* lss pair! */
247 uint32_t esp;
248#endif
249 /** @} */
250
251 /** Selector registers
252 * @{ */
253 RTSEL ss;
254 RTSEL ssPadding;
255 RTSEL gs;
256 RTSEL gsPadding;
257 RTSEL fs;
258 RTSEL fsPadding;
259 RTSEL es;
260 RTSEL esPadding;
261 RTSEL ds;
262 RTSEL dsPadding;
263 RTSEL cs;
264 RTSEL csPadding;
265 /** @} */
266
267#if HC_ARCH_BITS == 32
268 /** Control registers.
269 * @{ */
270 uint32_t cr0;
271 /*uint32_t cr2; - scratch*/
272 uint32_t cr3;
273 uint32_t cr4;
274 /** The CR0 FPU state in HM mode. Can't use cr0 here because the
275 * 64-bit-on-32-bit-host world switches is using it. */
276 uint32_t cr0Fpu;
277 /** @} */
278
279 /** Debug registers.
280 * @{ */
281 uint32_t dr0;
282 uint32_t dr1;
283 uint32_t dr2;
284 uint32_t dr3;
285 uint32_t dr6;
286 uint32_t dr7;
287 /** @} */
288
289 /** Global Descriptor Table register. */
290 X86XDTR32 gdtr;
291 uint16_t gdtrPadding;
292 /** Interrupt Descriptor Table register. */
293 X86XDTR32 idtr;
294 uint16_t idtrPadding;
295 /** The task register. */
296 RTSEL ldtr;
297 RTSEL ldtrPadding;
298 /** The task register. */
299 RTSEL tr;
300 RTSEL trPadding;
301
302 /** The sysenter msr registers.
303 * This member is not used by the hypervisor context. */
304 CPUMSYSENTER SysEnter;
305
306 /** MSRs
307 * @{ */
308 uint64_t efer;
309 /** @} */
310
311 /* padding to get 64byte aligned size */
312 uint8_t auPadding[20];
313
314#elif HC_ARCH_BITS == 64
315
316 /** Control registers.
317 * @{ */
318 /** The CR0 FPU state in HM mode. */
319 uint64_t cr0;
320 /*uint64_t cr2; - scratch*/
321 uint64_t cr3;
322 uint64_t cr4;
323 uint64_t cr8;
324 /** @} */
325
326 /** Debug registers.
327 * @{ */
328 uint64_t dr0;
329 uint64_t dr1;
330 uint64_t dr2;
331 uint64_t dr3;
332 uint64_t dr6;
333 uint64_t dr7;
334 /** @} */
335
336 /** Global Descriptor Table register. */
337 X86XDTR64 gdtr;
338 uint16_t gdtrPadding;
339 /** Interrupt Descriptor Table register. */
340 X86XDTR64 idtr;
341 uint16_t idtrPadding;
342 /** The task register. */
343 RTSEL ldtr;
344 RTSEL ldtrPadding;
345 /** The task register. */
346 RTSEL tr;
347 RTSEL trPadding;
348
349 /** MSRs
350 * @{ */
351 CPUMSYSENTER SysEnter;
352 uint64_t FSbase;
353 uint64_t GSbase;
354 uint64_t efer;
355 /** @} */
356
357 /* padding to get 64byte aligned size */
358 uint8_t auPadding[4];
359
360#else
361# error HC_ARCH_BITS not defined or unsupported
362#endif
363
364 /** Pointer to the FPU/SSE/AVX/XXXX state raw-mode mapping. */
365 RCPTRTYPE(PX86XSAVEAREA) pXStateRC;
366 /** Pointer to the FPU/SSE/AVX/XXXX state ring-0 mapping. */
367 R0PTRTYPE(PX86XSAVEAREA) pXStateR0;
368 /** Pointer to the FPU/SSE/AVX/XXXX state ring-3 mapping. */
369 R3PTRTYPE(PX86XSAVEAREA) pXStateR3;
370 /** The XCR0 register. */
371 uint64_t xcr0;
372 /** The mask to pass to XSAVE/XRSTOR in EDX:EAX. If zero we use
373 * FXSAVE/FXRSTOR (since bit 0 will always be set, we only need to test it). */
374 uint64_t fXStateMask;
375} CPUMHOSTCTX;
376#ifndef VBOX_FOR_DTRACE_LIB
377AssertCompileSizeAlignment(CPUMHOSTCTX, 64);
378#endif
379/** Pointer to the saved host CPU state. */
380typedef CPUMHOSTCTX *PCPUMHOSTCTX;
381
382
383/**
384 * CPUM Data (part of VM)
385 */
386typedef struct CPUM
387{
388 /** Offset from CPUM to CPUMCPU for the first CPU. */
389 uint32_t offCPUMCPU0;
390
391 /** Use flags.
392 * These flags indicates which CPU features the host uses.
393 */
394 uint32_t fHostUseFlags;
395
396 /** CR4 mask */
397 struct
398 {
399 uint32_t AndMask; /**< @todo Move these to the per-CPU structure and fix the switchers. Saves a register! */
400 uint32_t OrMask;
401 } CR4;
402
403 /** The (more) portable CPUID level. */
404 uint8_t u8PortableCpuIdLevel;
405 /** Indicates that a state restore is pending.
406 * This is used to verify load order dependencies (PGM). */
407 bool fPendingRestore;
408 uint8_t abPadding0[6];
409
410 /** XSAVE/XRTOR components we can expose to the guest mask. */
411 uint64_t fXStateGuestMask;
412 /** XSAVE/XRSTOR host mask. Only state components in this mask can be exposed
413 * to the guest. This is 0 if no XSAVE/XRSTOR bits can be exposed. */
414 uint64_t fXStateHostMask;
415
416 /** The host MXCSR mask (determined at init). */
417 uint32_t fHostMxCsrMask;
418 uint8_t abPadding1[20];
419
420 /** Host CPU feature information.
421 * Externaly visible via the VM structure, aligned on 64-byte boundrary. */
422 CPUMFEATURES HostFeatures;
423 /** Guest CPU feature information.
424 * Externaly visible via that VM structure, aligned with HostFeatures. */
425 CPUMFEATURES GuestFeatures;
426 /** Guest CPU info. */
427 CPUMINFO GuestInfo;
428
429 /** The standard set of CpuId leaves. */
430 CPUMCPUID aGuestCpuIdPatmStd[6];
431 /** The extended set of CpuId leaves. */
432 CPUMCPUID aGuestCpuIdPatmExt[10];
433 /** The centaur set of CpuId leaves. */
434 CPUMCPUID aGuestCpuIdPatmCentaur[4];
435
436 /** @name MSR statistics.
437 * @{ */
438 STAMCOUNTER cMsrWrites;
439 STAMCOUNTER cMsrWritesToIgnoredBits;
440 STAMCOUNTER cMsrWritesRaiseGp;
441 STAMCOUNTER cMsrWritesUnknown;
442 STAMCOUNTER cMsrReads;
443 STAMCOUNTER cMsrReadsRaiseGp;
444 STAMCOUNTER cMsrReadsUnknown;
445 /** @} */
446} CPUM;
447#ifndef VBOX_FOR_DTRACE_LIB
448AssertCompileMemberOffset(CPUM, HostFeatures, 64);
449AssertCompileMemberOffset(CPUM, GuestFeatures, 112);
450#endif
451/** Pointer to the CPUM instance data residing in the shared VM structure. */
452typedef CPUM *PCPUM;
453
454/**
455 * CPUM Data (part of VMCPU)
456 */
457typedef struct CPUMCPU
458{
459 /**
460 * Guest context.
461 * Aligned on a 64-byte boundary.
462 */
463 CPUMCTX Guest;
464
465 /**
466 * Guest context - misc MSRs
467 * Aligned on a 64-byte boundary.
468 */
469 CPUMCTXMSRS GuestMsrs;
470
471 /** Use flags.
472 * These flags indicates both what is to be used and what has been used.
473 */
474 uint32_t fUseFlags;
475
476 /** Changed flags.
477 * These flags indicates to REM (and others) which important guest
478 * registers which has been changed since last time the flags were cleared.
479 * See the CPUM_CHANGED_* defines for what we keep track of.
480 */
481 uint32_t fChanged;
482
483 /** Offset from CPUM to CPUMCPU. */
484 uint32_t offCPUM;
485
486 /** Temporary storage for the return code of the function called in the
487 * 32-64 switcher. */
488 uint32_t u32RetCode;
489
490#ifdef VBOX_WITH_VMMR0_DISABLE_LAPIC_NMI
491 /** The address of the APIC mapping, NULL if no APIC.
492 * Call CPUMR0SetLApic to update this before doing a world switch. */
493 RTHCPTR pvApicBase;
494 /** Used by the world switcher code to store which vectors needs restoring on
495 * the way back. */
496 uint32_t fApicDisVectors;
497 /** Set if the CPU has the X2APIC mode enabled.
498 * Call CPUMR0SetLApic to update this before doing a world switch. */
499 bool fX2Apic;
500#else
501 uint8_t abPadding3[(HC_ARCH_BITS == 64 ? 8 : 4) + 4 + 1];
502#endif
503
504 /** Have we entered raw-mode? */
505 bool fRawEntered;
506 /** Have we entered the recompiler? */
507 bool fRemEntered;
508 /** Whether the X86_CPUID_FEATURE_EDX_APIC and X86_CPUID_AMD_FEATURE_EDX_APIC
509 * (?) bits are visible or not. (The APIC is responsible for setting this
510 * when loading state, so we won't save it.) */
511 bool fCpuIdApicFeatureVisible;
512
513 /** Align the next member on a 64-byte boundrary. */
514 uint8_t abPadding2[64 - 16 - (HC_ARCH_BITS == 64 ? 8 : 4) - 4 - 1 - 3];
515
516 /** Saved host context. Only valid while inside RC or HM contexts.
517 * Must be aligned on a 64-byte boundary. */
518 CPUMHOSTCTX Host;
519 /** Hypervisor context. Must be aligned on a 64-byte boundary. */
520 CPUMCTX Hyper;
521
522#ifdef VBOX_WITH_CRASHDUMP_MAGIC
523 uint8_t aMagic[56];
524 uint64_t uMagic;
525#endif
526} CPUMCPU;
527/** Pointer to the CPUMCPU instance data residing in the shared VMCPU structure. */
528typedef CPUMCPU *PCPUMCPU;
529
530#ifndef VBOX_FOR_DTRACE_LIB
531RT_C_DECLS_BEGIN
532
533PCPUMCPUIDLEAF cpumCpuIdGetLeaf(PVM pVM, uint32_t uLeaf);
534PCPUMCPUIDLEAF cpumCpuIdGetLeafEx(PVM pVM, uint32_t uLeaf, uint32_t uSubLeaf, bool *pfExactSubLeafHit);
535
536# ifdef IN_RING3
537int cpumR3DbgInit(PVM pVM);
538int cpumR3CpuIdExplodeFeatures(PCCPUMCPUIDLEAF paLeaves, uint32_t cLeaves, PCCPUMMSRS pMsrs, PCPUMFEATURES pFeatures);
539int cpumR3InitCpuIdAndMsrs(PVM pVM, PCCPUMMSRS pHostMsrs);
540void cpumR3InitVmxGuestFeaturesAndMsrs(PVM pVM, PCVMXMSRS pHostVmxMsrs, PVMXMSRS pGuestVmxMsrs);
541void cpumR3SaveCpuId(PVM pVM, PSSMHANDLE pSSM);
542int cpumR3LoadCpuId(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion, PCCPUMMSRS pGuestMsrs);
543int cpumR3LoadCpuIdPre32(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion);
544DECLCALLBACK(void) cpumR3CpuIdInfo(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
545
546int cpumR3DbGetCpuInfo(const char *pszName, PCPUMINFO pInfo);
547int cpumR3MsrRangesInsert(PVM pVM, PCPUMMSRRANGE *ppaMsrRanges, uint32_t *pcMsrRanges, PCCPUMMSRRANGE pNewRange);
548int cpumR3MsrReconcileWithCpuId(PVM pVM);
549int cpumR3MsrApplyFudge(PVM pVM);
550int cpumR3MsrRegStats(PVM pVM);
551int cpumR3MsrStrictInitChecks(void);
552PCPUMMSRRANGE cpumLookupMsrRange(PVM pVM, uint32_t idMsr);
553# endif
554
555# ifdef IN_RC
556DECLASM(int) cpumHandleLazyFPUAsm(PCPUMCPU pCPUM);
557# endif
558
559# ifdef IN_RING0
560DECLASM(int) cpumR0SaveHostRestoreGuestFPUState(PCPUMCPU pCPUM);
561DECLASM(void) cpumR0SaveGuestRestoreHostFPUState(PCPUMCPU pCPUM);
562# if ARCH_BITS == 32 && defined(VBOX_WITH_64_BITS_GUESTS)
563DECLASM(void) cpumR0RestoreHostFPUState(PCPUMCPU pCPUM);
564# endif
565# endif
566
567# if defined(IN_RC) || defined(IN_RING0)
568DECLASM(int) cpumRZSaveHostFPUState(PCPUMCPU pCPUM);
569DECLASM(void) cpumRZSaveGuestFpuState(PCPUMCPU pCPUM, bool fLeaveFpuAccessible);
570DECLASM(void) cpumRZSaveGuestSseRegisters(PCPUMCPU pCPUM);
571DECLASM(void) cpumRZSaveGuestAvxRegisters(PCPUMCPU pCPUM);
572# endif
573
574RT_C_DECLS_END
575#endif /* !VBOX_FOR_DTRACE_LIB */
576
577/** @} */
578
579#endif /* !VMM_INCLUDED_SRC_include_CPUMInternal_h */
580
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