VirtualBox

source: vbox/trunk/src/VBox/VMM/include/CPUMInternal.h@ 94901

Last change on this file since 94901 was 94901, checked in by vboxsync, 3 years ago

VMM/CPUM: On non-x86 hosts, just use the MXCSR MASK from the CPU DB as-is. bugref:9898
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1/* $Id: CPUMInternal.h 94901 2022-05-06 18:59:14Z vboxsync $ */
2/** @file
3 * CPUM - Internal header file.
4 */
5
6/*
7 * Copyright (C) 2006-2022 Oracle Corporation
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 */
17
18#ifndef VMM_INCLUDED_SRC_include_CPUMInternal_h
19#define VMM_INCLUDED_SRC_include_CPUMInternal_h
20#ifndef RT_WITHOUT_PRAGMA_ONCE
21# pragma once
22#endif
23
24#ifndef VBOX_FOR_DTRACE_LIB
25# include <VBox/cdefs.h>
26# include <VBox/types.h>
27# include <VBox/vmm/stam.h>
28# include <iprt/x86.h>
29# include <VBox/vmm/pgm.h>
30#else
31# pragma D depends_on library x86.d
32# pragma D depends_on library cpumctx.d
33# pragma D depends_on library cpum.d
34
35/* Some fudging. */
36typedef uint64_t STAMCOUNTER;
37#endif
38
39
40
41
42/** @defgroup grp_cpum_int Internals
43 * @ingroup grp_cpum
44 * @internal
45 * @{
46 */
47
48/** Flags and types for CPUM fault handlers
49 * @{ */
50/** Type: Load DS */
51#define CPUM_HANDLER_DS 1
52/** Type: Load ES */
53#define CPUM_HANDLER_ES 2
54/** Type: Load FS */
55#define CPUM_HANDLER_FS 3
56/** Type: Load GS */
57#define CPUM_HANDLER_GS 4
58/** Type: IRET */
59#define CPUM_HANDLER_IRET 5
60/** Type mask. */
61#define CPUM_HANDLER_TYPEMASK 0xff
62/** If set EBP points to the CPUMCTXCORE that's being used. */
63#define CPUM_HANDLER_CTXCORE_IN_EBP RT_BIT(31)
64/** @} */
65
66
67/** Use flags (CPUM::fUseFlags).
68 * (Don't forget to sync this with CPUMInternal.mac !)
69 * @note Was part of saved state (6.1 and earlier).
70 * @{ */
71/** Indicates that we've saved the host FPU, SSE, whatever state and that it
72 * needs to be restored. */
73#define CPUM_USED_FPU_HOST RT_BIT(0)
74/** Indicates that we've loaded the guest FPU, SSE, whatever state and that it
75 * needs to be saved.
76 * @note Mirrored in CPUMCTX::fUsedFpuGuest for the HM switcher code. */
77#define CPUM_USED_FPU_GUEST RT_BIT(10)
78/** Used the guest FPU, SSE or such stuff since last we were in REM.
79 * REM syncing is clearing this, lazy FPU is setting it. */
80#define CPUM_USED_FPU_SINCE_REM RT_BIT(1)
81/** The XMM state was manually restored. (AMD only) */
82#define CPUM_USED_MANUAL_XMM_RESTORE RT_BIT(2)
83
84/** Host OS is using SYSENTER and we must NULL the CS. */
85#define CPUM_USE_SYSENTER RT_BIT(3)
86/** Host OS is using SYSENTER and we must NULL the CS. */
87#define CPUM_USE_SYSCALL RT_BIT(4)
88
89/** Debug registers are used by host and that DR7 and DR6 must be saved and
90 * disabled when switching to raw-mode. */
91#define CPUM_USE_DEBUG_REGS_HOST RT_BIT(5)
92/** Records that we've saved the host DRx registers.
93 * In ring-0 this means all (DR0-7), while in raw-mode context this means DR0-3
94 * since DR6 and DR7 are covered by CPUM_USE_DEBUG_REGS_HOST. */
95#define CPUM_USED_DEBUG_REGS_HOST RT_BIT(6)
96/** Set to indicate that we should save host DR0-7 and load the hypervisor debug
97 * registers in the raw-mode world switchers. (See CPUMRecalcHyperDRx.) */
98#define CPUM_USE_DEBUG_REGS_HYPER RT_BIT(7)
99/** Used in ring-0 to indicate that we have loaded the hypervisor debug
100 * registers. */
101#define CPUM_USED_DEBUG_REGS_HYPER RT_BIT(8)
102/** Used in ring-0 to indicate that we have loaded the guest debug
103 * registers (DR0-3 and maybe DR6) for direct use by the guest.
104 * DR7 (and AMD-V DR6) are handled via the VMCB. */
105#define CPUM_USED_DEBUG_REGS_GUEST RT_BIT(9)
106
107/** Host CPU requires fxsave/fxrstor leaky bit handling. */
108#define CPUM_USE_FFXSR_LEAKY RT_BIT(19)
109/** Set if the VM supports long-mode. */
110#define CPUM_USE_SUPPORTS_LONGMODE RT_BIT(20)
111/** @} */
112
113
114/** @name CPUM Saved State Version.
115 * @{ */
116/** The current saved state version. */
117#define CPUM_SAVED_STATE_VERSION CPUM_SAVED_STATE_VERSION_PAE_PDPES
118/** The saved state version with PAE PDPEs added. */
119#define CPUM_SAVED_STATE_VERSION_PAE_PDPES 21
120/** The saved state version with more virtual VMCS fields and CPUMCTX VMX fields. */
121#define CPUM_SAVED_STATE_VERSION_HWVIRT_VMX_2 20
122/** The saved state version including VMX hardware virtualization state. */
123#define CPUM_SAVED_STATE_VERSION_HWVIRT_VMX 19
124/** The saved state version including SVM hardware virtualization state. */
125#define CPUM_SAVED_STATE_VERSION_HWVIRT_SVM 18
126/** The saved state version including XSAVE state. */
127#define CPUM_SAVED_STATE_VERSION_XSAVE 17
128/** The saved state version with good CPUID leaf count. */
129#define CPUM_SAVED_STATE_VERSION_GOOD_CPUID_COUNT 16
130/** CPUID changes with explode forgetting to update the leaf count on
131 * restore, resulting in garbage being saved restoring+saving old states). */
132#define CPUM_SAVED_STATE_VERSION_BAD_CPUID_COUNT 15
133/** The saved state version before the CPUIDs changes. */
134#define CPUM_SAVED_STATE_VERSION_PUT_STRUCT 14
135/** The saved state version before using SSMR3PutStruct. */
136#define CPUM_SAVED_STATE_VERSION_MEM 13
137/** The saved state version before introducing the MSR size field. */
138#define CPUM_SAVED_STATE_VERSION_NO_MSR_SIZE 12
139/** The saved state version of 3.2, 3.1 and 3.3 trunk before the hidden
140 * selector register change (CPUM_CHANGED_HIDDEN_SEL_REGS_INVALID). */
141#define CPUM_SAVED_STATE_VERSION_VER3_2 11
142/** The saved state version of 3.0 and 3.1 trunk before the teleportation
143 * changes. */
144#define CPUM_SAVED_STATE_VERSION_VER3_0 10
145/** The saved state version for the 2.1 trunk before the MSR changes. */
146#define CPUM_SAVED_STATE_VERSION_VER2_1_NOMSR 9
147/** The saved state version of 2.0, used for backwards compatibility. */
148#define CPUM_SAVED_STATE_VERSION_VER2_0 8
149/** The saved state version of 1.6, used for backwards compatibility. */
150#define CPUM_SAVED_STATE_VERSION_VER1_6 6
151/** @} */
152
153
154/**
155 * CPU info
156 */
157typedef struct CPUMINFO
158{
159 /** The number of MSR ranges (CPUMMSRRANGE) in the array pointed to below. */
160 uint32_t cMsrRanges;
161 /** Mask applied to ECX before looking up the MSR for a RDMSR/WRMSR
162 * instruction. Older hardware has been observed to ignore higher bits. */
163 uint32_t fMsrMask;
164
165 /** MXCSR mask. */
166 uint32_t fMxCsrMask;
167
168 /** The number of CPUID leaves (CPUMCPUIDLEAF) in the array pointed to below. */
169 uint32_t cCpuIdLeaves;
170 /** The index of the first extended CPUID leaf in the array.
171 * Set to cCpuIdLeaves if none present. */
172 uint32_t iFirstExtCpuIdLeaf;
173 /** How to handle unknown CPUID leaves. */
174 CPUMUNKNOWNCPUID enmUnknownCpuIdMethod;
175 /** For use with CPUMUNKNOWNCPUID_DEFAULTS (DB & VM),
176 * CPUMUNKNOWNCPUID_LAST_STD_LEAF (VM) and CPUMUNKNOWNCPUID_LAST_STD_LEAF_WITH_ECX (VM). */
177 CPUMCPUID DefCpuId;
178
179 /** Scalable bus frequency used for reporting other frequencies. */
180 uint64_t uScalableBusFreq;
181
182 /** Pointer to the MSR ranges (for compatibility with old hyper heap code). */
183 R3PTRTYPE(PCPUMMSRRANGE) paMsrRangesR3;
184 /** Pointer to the CPUID leaves (for compatibility with old hyper heap code). */
185 R3PTRTYPE(PCPUMCPUIDLEAF) paCpuIdLeavesR3;
186
187 /** CPUID leaves. */
188 CPUMCPUIDLEAF aCpuIdLeaves[256];
189 /** MSR ranges.
190 * @todo This is insane, so might want to move this into a separate
191 * allocation. The insanity is mainly for more recent AMD CPUs. */
192 CPUMMSRRANGE aMsrRanges[8192];
193} CPUMINFO;
194/** Pointer to a CPU info structure. */
195typedef CPUMINFO *PCPUMINFO;
196/** Pointer to a const CPU info structure. */
197typedef CPUMINFO const *CPCPUMINFO;
198
199
200/**
201 * The saved host CPU state.
202 */
203typedef struct CPUMHOSTCTX
204{
205 /** The extended state (FPU/SSE/AVX/AVX-2/XXXX). Must be aligned on 64 bytes. */
206 union /* no tag */
207 {
208 X86XSAVEAREA XState;
209 /** Byte view for simple indexing and space allocation.
210 * @note Must match or exceed the size of CPUMCTX::abXState. */
211 uint8_t abXState[0x4000 - 0x300];
212 } CPUM_UNION_NM(u);
213
214 /** General purpose register, selectors, flags and more
215 * @{ */
216 /** General purpose register ++
217 * { */
218 /*uint64_t rax; - scratch*/
219 uint64_t rbx;
220 /*uint64_t rcx; - scratch*/
221 /*uint64_t rdx; - scratch*/
222 uint64_t rdi;
223 uint64_t rsi;
224 uint64_t rbp;
225 uint64_t rsp;
226 /*uint64_t r8; - scratch*/
227 /*uint64_t r9; - scratch*/
228 uint64_t r10;
229 uint64_t r11;
230 uint64_t r12;
231 uint64_t r13;
232 uint64_t r14;
233 uint64_t r15;
234 /*uint64_t rip; - scratch*/
235 uint64_t rflags;
236 /** @} */
237
238 /** Selector registers
239 * @{ */
240 RTSEL ss;
241 RTSEL ssPadding;
242 RTSEL gs;
243 RTSEL gsPadding;
244 RTSEL fs;
245 RTSEL fsPadding;
246 RTSEL es;
247 RTSEL esPadding;
248 RTSEL ds;
249 RTSEL dsPadding;
250 RTSEL cs;
251 RTSEL csPadding;
252 /** @} */
253
254 /** Control registers.
255 * @{ */
256 /** The CR0 FPU state in HM mode. */
257 uint64_t cr0;
258 /*uint64_t cr2; - scratch*/
259 uint64_t cr3;
260 uint64_t cr4;
261 uint64_t cr8;
262 /** @} */
263
264 /** Debug registers.
265 * @{ */
266 uint64_t dr0;
267 uint64_t dr1;
268 uint64_t dr2;
269 uint64_t dr3;
270 uint64_t dr6;
271 uint64_t dr7;
272 /** @} */
273
274 /** Global Descriptor Table register. */
275 X86XDTR64 gdtr;
276 uint16_t gdtrPadding;
277 /** Interrupt Descriptor Table register. */
278 X86XDTR64 idtr;
279 uint16_t idtrPadding;
280 /** The task register. */
281 RTSEL ldtr;
282 RTSEL ldtrPadding;
283 /** The task register. */
284 RTSEL tr;
285 RTSEL trPadding;
286
287 /** MSRs
288 * @{ */
289 CPUMSYSENTER SysEnter;
290 uint64_t FSbase;
291 uint64_t GSbase;
292 uint64_t efer;
293 /** @} */
294
295 /** The XCR0 register. */
296 uint64_t xcr0;
297 /** The mask to pass to XSAVE/XRSTOR in EDX:EAX. If zero we use
298 * FXSAVE/FXRSTOR (since bit 0 will always be set, we only need to test it). */
299 uint64_t fXStateMask;
300
301 /* padding to get 64byte aligned size */
302 uint8_t auPadding[24];
303#if HC_ARCH_BITS != 64
304# error HC_ARCH_BITS not defined or unsupported
305#endif
306} CPUMHOSTCTX;
307#ifndef VBOX_FOR_DTRACE_LIB
308AssertCompileSizeAlignment(CPUMHOSTCTX, 64);
309#endif
310/** Pointer to the saved host CPU state. */
311typedef CPUMHOSTCTX *PCPUMHOSTCTX;
312
313
314/**
315 * The hypervisor context CPU state (just DRx left now).
316 */
317typedef struct CPUMHYPERCTX
318{
319 /** Debug registers.
320 * @remarks DR4 and DR5 should not be used since they are aliases for
321 * DR6 and DR7 respectively on both AMD and Intel CPUs.
322 * @remarks DR8-15 are currently not supported by AMD or Intel, so
323 * neither do we.
324 */
325 uint64_t dr[8];
326 /** @todo eliminiate the rest. */
327 uint64_t cr3;
328 uint64_t au64Padding[7];
329} CPUMHYPERCTX;
330#ifndef VBOX_FOR_DTRACE_LIB
331AssertCompileSizeAlignment(CPUMHYPERCTX, 64);
332#endif
333/** Pointer to the hypervisor context CPU state. */
334typedef CPUMHYPERCTX *PCPUMHYPERCTX;
335
336
337/**
338 * CPUM Data (part of VM)
339 */
340typedef struct CPUM
341{
342 /** Use flags.
343 * These flags indicates which CPU features the host uses.
344 */
345 uint32_t fHostUseFlags;
346
347 /** CR4 mask
348 * @todo obsolete? */
349 struct
350 {
351 uint32_t AndMask; /**< @todo Move these to the per-CPU structure and fix the switchers. Saves a register! */
352 uint32_t OrMask;
353 } CR4;
354
355 /** The (more) portable CPUID level. */
356 uint8_t u8PortableCpuIdLevel;
357 /** Indicates that a state restore is pending.
358 * This is used to verify load order dependencies (PGM). */
359 bool fPendingRestore;
360 uint8_t abPadding0[2];
361
362 /** XSAVE/XRTOR components we can expose to the guest mask. */
363 uint64_t fXStateGuestMask;
364 /** XSAVE/XRSTOR host mask. Only state components in this mask can be exposed
365 * to the guest. This is 0 if no XSAVE/XRSTOR bits can be exposed. */
366 uint64_t fXStateHostMask;
367
368#if defined(RT_ARCH_X86) || defined(RT_ARCH_AMD64)
369 /** The host MXCSR mask (determined at init). */
370 uint32_t fHostMxCsrMask;
371#else
372 uint32_t u32UnusedOnNonX86;
373#endif
374 /** Nested VMX: Whether to expose VMX-preemption timer to the guest. */
375 bool fNestedVmxPreemptTimer;
376 /** Nested VMX: Whether to expose EPT to the guest. If this is disabled make sure
377 * to also disable fNestedVmxUnrestrictedGuest. */
378 bool fNestedVmxEpt;
379 /** Nested VMX: Whether to expose "unrestricted guest" to the guest. */
380 bool fNestedVmxUnrestrictedGuest;
381 uint8_t abPadding1[1];
382
383 /** Align to 64-byte boundary. */
384 uint8_t abPadding2[20+4];
385
386 /** Host CPU feature information.
387 * Externaly visible via the VM structure, aligned on 64-byte boundrary. */
388 CPUMFEATURES HostFeatures;
389 /** Guest CPU feature information.
390 * Externaly visible via that VM structure, aligned with HostFeatures. */
391 CPUMFEATURES GuestFeatures;
392 /** Guest CPU info. */
393 CPUMINFO GuestInfo;
394
395 /** The standard set of CpuId leaves. */
396 CPUMCPUID aGuestCpuIdPatmStd[6];
397 /** The extended set of CpuId leaves. */
398 CPUMCPUID aGuestCpuIdPatmExt[10];
399 /** The centaur set of CpuId leaves. */
400 CPUMCPUID aGuestCpuIdPatmCentaur[4];
401
402 /** @name MSR statistics.
403 * @{ */
404 STAMCOUNTER cMsrWrites;
405 STAMCOUNTER cMsrWritesToIgnoredBits;
406 STAMCOUNTER cMsrWritesRaiseGp;
407 STAMCOUNTER cMsrWritesUnknown;
408 STAMCOUNTER cMsrReads;
409 STAMCOUNTER cMsrReadsRaiseGp;
410 STAMCOUNTER cMsrReadsUnknown;
411 /** @} */
412} CPUM;
413#ifndef VBOX_FOR_DTRACE_LIB
414AssertCompileMemberOffset(CPUM, HostFeatures, 64);
415AssertCompileMemberOffset(CPUM, GuestFeatures, 112);
416#endif
417/** Pointer to the CPUM instance data residing in the shared VM structure. */
418typedef CPUM *PCPUM;
419
420/**
421 * CPUM Data (part of VMCPU)
422 */
423typedef struct CPUMCPU
424{
425 /**
426 * Guest context.
427 * Aligned on a 64-byte boundary.
428 */
429 CPUMCTX Guest;
430
431 /**
432 * Guest context - misc MSRs
433 * Aligned on a 64-byte boundary.
434 */
435 CPUMCTXMSRS GuestMsrs;
436
437 /** Nested VMX: VMX-preemption timer. */
438 TMTIMERHANDLE hNestedVmxPreemptTimer;
439
440 /** Use flags.
441 * These flags indicates both what is to be used and what has been used.
442 */
443 uint32_t fUseFlags;
444
445 /** Changed flags.
446 * These flags indicates to REM (and others) which important guest
447 * registers which has been changed since last time the flags were cleared.
448 * See the CPUM_CHANGED_* defines for what we keep track of.
449 *
450 * @todo Obsolete, but will probably refactored so keep it for reference. */
451 uint32_t fChanged;
452
453 /** Temporary storage for the return code of the function called in the
454 * 32-64 switcher. */
455 uint32_t u32RetCode;
456
457#ifdef VBOX_WITH_VMMR0_DISABLE_LAPIC_NMI
458 /** Used by the world switcher code to store which vectors needs restoring on
459 * the way back. */
460 uint32_t fApicDisVectors;
461 /** The address of the APIC mapping, NULL if no APIC.
462 * Call CPUMR0SetLApic to update this before doing a world switch. */
463 RTHCPTR pvApicBase;
464 /** Set if the CPU has the X2APIC mode enabled.
465 * Call CPUMR0SetLApic to update this before doing a world switch. */
466 bool fX2Apic;
467#else
468 uint8_t abPadding3[4 + sizeof(RTHCPTR) + 1];
469#endif
470
471 /** Whether the X86_CPUID_FEATURE_EDX_APIC and X86_CPUID_AMD_FEATURE_EDX_APIC
472 * (?) bits are visible or not. (The APIC is responsible for setting this
473 * when loading state, so we won't save it.) */
474 bool fCpuIdApicFeatureVisible;
475
476 /** Align the next member on a 64-byte boundary. */
477 uint8_t abPadding2[64 - (8 + 12 + 4 + 8 + 1 + 1)];
478
479 /** Saved host context. Only valid while inside RC or HM contexts.
480 * Must be aligned on a 64-byte boundary. */
481 CPUMHOSTCTX Host;
482 /** Old hypervisor context, only used for combined DRx values now.
483 * Must be aligned on a 64-byte boundary. */
484 CPUMHYPERCTX Hyper;
485
486#ifdef VBOX_WITH_CRASHDUMP_MAGIC
487 uint8_t aMagic[56];
488 uint64_t uMagic;
489#endif
490} CPUMCPU;
491#ifndef VBOX_FOR_DTRACE_LIB
492AssertCompileMemberAlignment(CPUMCPU, Host, 64);
493#endif
494/** Pointer to the CPUMCPU instance data residing in the shared VMCPU structure. */
495typedef CPUMCPU *PCPUMCPU;
496
497#ifndef VBOX_FOR_DTRACE_LIB
498RT_C_DECLS_BEGIN
499
500PCPUMCPUIDLEAF cpumCpuIdGetLeaf(PVM pVM, uint32_t uLeaf);
501PCPUMCPUIDLEAF cpumCpuIdGetLeafEx(PVM pVM, uint32_t uLeaf, uint32_t uSubLeaf, bool *pfExactSubLeafHit);
502
503# ifdef IN_RING3
504int cpumR3DbgInit(PVM pVM);
505int cpumR3CpuIdExplodeFeatures(PCCPUMCPUIDLEAF paLeaves, uint32_t cLeaves, PCCPUMMSRS pMsrs, PCPUMFEATURES pFeatures);
506int cpumR3InitCpuIdAndMsrs(PVM pVM, PCCPUMMSRS pHostMsrs);
507void cpumR3InitVmxGuestFeaturesAndMsrs(PVM pVM, PCVMXMSRS pHostVmxMsrs, PVMXMSRS pGuestVmxMsrs);
508void cpumR3SaveCpuId(PVM pVM, PSSMHANDLE pSSM);
509int cpumR3LoadCpuId(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion, PCCPUMMSRS pGuestMsrs);
510int cpumR3LoadCpuIdPre32(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion);
511DECLCALLBACK(void) cpumR3CpuIdInfo(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
512
513int cpumR3DbGetCpuInfo(const char *pszName, PCPUMINFO pInfo);
514int cpumR3MsrRangesInsert(PVM pVM, PCPUMMSRRANGE *ppaMsrRanges, uint32_t *pcMsrRanges, PCCPUMMSRRANGE pNewRange);
515int cpumR3MsrReconcileWithCpuId(PVM pVM);
516int cpumR3MsrApplyFudge(PVM pVM);
517int cpumR3MsrRegStats(PVM pVM);
518int cpumR3MsrStrictInitChecks(void);
519PCPUMMSRRANGE cpumLookupMsrRange(PVM pVM, uint32_t idMsr);
520# endif
521
522# ifdef IN_RC
523DECLASM(int) cpumHandleLazyFPUAsm(PCPUMCPU pCPUM);
524# endif
525
526# ifdef IN_RING0
527DECLASM(int) cpumR0SaveHostRestoreGuestFPUState(PCPUMCPU pCPUM);
528DECLASM(void) cpumR0SaveGuestRestoreHostFPUState(PCPUMCPU pCPUM);
529# if ARCH_BITS == 32 && defined(VBOX_WITH_64_BITS_GUESTS)
530DECLASM(void) cpumR0RestoreHostFPUState(PCPUMCPU pCPUM);
531# endif
532# endif
533
534# if defined(IN_RC) || defined(IN_RING0)
535DECLASM(int) cpumRZSaveHostFPUState(PCPUMCPU pCPUM);
536DECLASM(void) cpumRZSaveGuestFpuState(PCPUMCPU pCPUM, bool fLeaveFpuAccessible);
537DECLASM(void) cpumRZSaveGuestSseRegisters(PCPUMCPU pCPUM);
538DECLASM(void) cpumRZSaveGuestAvxRegisters(PCPUMCPU pCPUM);
539# endif
540
541RT_C_DECLS_END
542#endif /* !VBOX_FOR_DTRACE_LIB */
543
544/** @} */
545
546#endif /* !VMM_INCLUDED_SRC_include_CPUMInternal_h */
547
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