| 1 | ; $Id: CPUMInternal.mac 51301 2014-05-20 04:47:59Z vboxsync $
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| 2 | ;; @file
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| 3 | ; CPUM - Internal header file (asm).
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| 4 | ;
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| 5 |
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| 6 | ;
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| 7 | ; Copyright (C) 2006-2012 Oracle Corporation
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| 8 | ;
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| 9 | ; This file is part of VirtualBox Open Source Edition (OSE), as
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| 10 | ; available from http://www.virtualbox.org. This file is free software;
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| 11 | ; you can redistribute it and/or modify it under the terms of the GNU
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| 12 | ; General Public License (GPL) as published by the Free Software
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| 13 | ; Foundation, in version 2 as it comes in the "COPYING" file of the
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| 14 | ; VirtualBox OSE distribution. VirtualBox OSE is distributed in the
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| 15 | ; hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
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| 16 | ;
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| 17 |
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| 18 | %include "VBox/asmdefs.mac"
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| 19 |
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| 20 |
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| 21 | %define CPUM_USED_FPU RT_BIT(0)
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| 22 | %define CPUM_USED_FPU_SINCE_REM RT_BIT(1)
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| 23 | %define CPUM_USED_MANUAL_XMM_RESTORE RT_BIT(2)
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| 24 | %define CPUM_USE_SYSENTER RT_BIT(3)
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| 25 | %define CPUM_USE_SYSCALL RT_BIT(4)
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| 26 | %define CPUM_USE_DEBUG_REGS_HOST RT_BIT(5)
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| 27 | %define CPUM_USED_DEBUG_REGS_HOST RT_BIT(6)
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| 28 | %define CPUM_USE_DEBUG_REGS_HYPER RT_BIT(7)
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| 29 | %define CPUM_USED_DEBUG_REGS_HYPER RT_BIT(8)
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| 30 | %define CPUM_USED_DEBUG_REGS_GUEST RT_BIT(9)
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| 31 | %define CPUM_SYNC_FPU_STATE RT_BIT(16)
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| 32 | %define CPUM_SYNC_DEBUG_REGS_GUEST RT_BIT(17)
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| 33 | %define CPUM_SYNC_DEBUG_REGS_HYPER RT_BIT(18)
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| 34 | %define CPUM_USE_FFXSR_LEAKY RT_BIT(19)
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| 35 |
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| 36 | %define CPUM_HANDLER_DS 1
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| 37 | %define CPUM_HANDLER_ES 2
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| 38 | %define CPUM_HANDLER_FS 3
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| 39 | %define CPUM_HANDLER_GS 4
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| 40 | %define CPUM_HANDLER_IRET 5
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| 41 | %define CPUM_HANDLER_TYPEMASK 0ffh
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| 42 | %define CPUM_HANDLER_CTXCORE_IN_EBP RT_BIT(31)
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| 43 |
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| 44 | %define VMMGCRET_USED_FPU 040000000h
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| 45 |
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| 46 | %define FPUSTATE_SIZE 512
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| 47 |
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| 48 | ;; if anyone figures how to do %if HC_ARCH_BITS == 64 || defined(VBOX_WITH_HYBRID_32BIT_KERNEL) in
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| 49 | ; nasm please tell / fix this hack.
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| 50 | %ifdef VBOX_WITH_HYBRID_32BIT_KERNEL
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| 51 | %define fVBOX_WITH_HYBRID_32BIT_KERNEL 1
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| 52 | %else
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| 53 | %define fVBOX_WITH_HYBRID_32BIT_KERNEL 0
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| 54 | %endif
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| 55 |
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| 56 | struc CPUM
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| 57 | ;...
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| 58 | .offCPUMCPU0 resd 1
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| 59 | .fHostUseFlags resd 1
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| 60 |
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| 61 | ; CPUID eax=1
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| 62 | .CPUFeatures.edx resd 1
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| 63 | .CPUFeatures.ecx resd 1
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| 64 |
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| 65 | ; CPUID eax=0x80000001
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| 66 | .CPUFeaturesExt.edx resd 1
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| 67 | .CPUFeaturesExt.ecx resd 1
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| 68 |
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| 69 | ; CR4 masks
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| 70 | .CR4.AndMask resd 1
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| 71 | .CR4.OrMask resd 1
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| 72 | ; entered rawmode?
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| 73 | .u8PortableCpuIdLevel resb 1
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| 74 | .fPendingRestore resb 1
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| 75 | %if RTHCPTR_CB == 8
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| 76 | .abPadding resb 6
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| 77 | %else
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| 78 | .abPadding resb 2
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| 79 | %endif
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| 80 |
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| 81 | ; CPUID leafs
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| 82 | .aGuestCpuIdStd resb 16*6
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| 83 | .aGuestCpuIdExt resb 16*10
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| 84 | .aGuestCpuIdCentaur resb 16*4
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| 85 | .GuestCpuIdDef resb 16
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| 86 |
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| 87 | %if HC_ARCH_BITS == 32
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| 88 | .abPadding2 resb 4
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| 89 | %endif
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| 90 |
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| 91 | .GuestInfo resb RTHCPTR_CB*4 + RTRCPTR_CB*2 + 4*12
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| 92 | .GuestFeatures resb 32
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| 93 | .HostFeatures resb 32
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| 94 |
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| 95 | .cMsrWrites resq 1
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| 96 | .cMsrWritesToIgnoredBits resq 1
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| 97 | .cMsrWritesRaiseGp resq 1
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| 98 | .cMsrWritesUnknown resq 1
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| 99 | .cMsrReads resq 1
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| 100 | .cMsrReadsRaiseGp resq 1
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| 101 | .cMsrReadsUnknown resq 1
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| 102 | endstruc
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| 103 |
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| 104 | struc CPUMCPU
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| 105 | ;
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| 106 | ; Hypervisor Context.
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| 107 | ;
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| 108 | .Hyper.fpu resb 512
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| 109 | .Hyper.eax resq 1
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| 110 | .Hyper.ecx resq 1
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| 111 | .Hyper.edx resq 1
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| 112 | .Hyper.ebx resq 1
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| 113 | .Hyper.esp resq 1
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| 114 | .Hyper.ebp resq 1
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| 115 | .Hyper.esi resq 1
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| 116 | .Hyper.edi resq 1
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| 117 | .Hyper.r8 resq 1
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| 118 | .Hyper.r9 resq 1
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| 119 | .Hyper.r10 resq 1
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| 120 | .Hyper.r11 resq 1
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| 121 | .Hyper.r12 resq 1
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| 122 | .Hyper.r13 resq 1
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| 123 | .Hyper.r14 resq 1
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| 124 | .Hyper.r15 resq 1
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| 125 | .Hyper.es.Sel resw 1
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| 126 | .Hyper.es.PaddingSel resw 1
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| 127 | .Hyper.es.ValidSel resw 1
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| 128 | .Hyper.es.fFlags resw 1
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| 129 | .Hyper.es.u64Base resq 1
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| 130 | .Hyper.es.u32Limit resd 1
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| 131 | .Hyper.es.Attr resd 1
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| 132 | .Hyper.cs.Sel resw 1
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| 133 | .Hyper.cs.PaddingSel resw 1
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| 134 | .Hyper.cs.ValidSel resw 1
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| 135 | .Hyper.cs.fFlags resw 1
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| 136 | .Hyper.cs.u64Base resq 1
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| 137 | .Hyper.cs.u32Limit resd 1
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| 138 | .Hyper.cs.Attr resd 1
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| 139 | .Hyper.ss.Sel resw 1
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| 140 | .Hyper.ss.PaddingSel resw 1
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| 141 | .Hyper.ss.ValidSel resw 1
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| 142 | .Hyper.ss.fFlags resw 1
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| 143 | .Hyper.ss.u64Base resq 1
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| 144 | .Hyper.ss.u32Limit resd 1
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| 145 | .Hyper.ss.Attr resd 1
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| 146 | .Hyper.ds.Sel resw 1
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| 147 | .Hyper.ds.PaddingSel resw 1
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| 148 | .Hyper.ds.ValidSel resw 1
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| 149 | .Hyper.ds.fFlags resw 1
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| 150 | .Hyper.ds.u64Base resq 1
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| 151 | .Hyper.ds.u32Limit resd 1
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| 152 | .Hyper.ds.Attr resd 1
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| 153 | .Hyper.fs.Sel resw 1
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| 154 | .Hyper.fs.PaddingSel resw 1
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| 155 | .Hyper.fs.ValidSel resw 1
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| 156 | .Hyper.fs.fFlags resw 1
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| 157 | .Hyper.fs.u64Base resq 1
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| 158 | .Hyper.fs.u32Limit resd 1
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| 159 | .Hyper.fs.Attr resd 1
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| 160 | .Hyper.gs.Sel resw 1
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| 161 | .Hyper.gs.PaddingSel resw 1
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| 162 | .Hyper.gs.ValidSel resw 1
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| 163 | .Hyper.gs.fFlags resw 1
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| 164 | .Hyper.gs.u64Base resq 1
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| 165 | .Hyper.gs.u32Limit resd 1
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| 166 | .Hyper.gs.Attr resd 1
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| 167 | .Hyper.eip resq 1
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| 168 | .Hyper.eflags resq 1
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| 169 | .Hyper.cr0 resq 1
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| 170 | .Hyper.cr2 resq 1
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| 171 | .Hyper.cr3 resq 1
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| 172 | .Hyper.cr4 resq 1
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| 173 | .Hyper.dr resq 8
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| 174 | .Hyper.gdtrPadding resw 3
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| 175 | .Hyper.gdtr resw 0
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| 176 | .Hyper.gdtr.cbGdt resw 1
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| 177 | .Hyper.gdtr.pGdt resq 1
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| 178 | .Hyper.idtrPadding resw 3
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| 179 | .Hyper.idtr resw 0
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| 180 | .Hyper.idtr.cbIdt resw 1
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| 181 | .Hyper.idtr.pIdt resq 1
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| 182 | .Hyper.ldtr.Sel resw 1
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| 183 | .Hyper.ldtr.PaddingSel resw 1
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| 184 | .Hyper.ldtr.ValidSel resw 1
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| 185 | .Hyper.ldtr.fFlags resw 1
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| 186 | .Hyper.ldtr.u64Base resq 1
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| 187 | .Hyper.ldtr.u32Limit resd 1
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| 188 | .Hyper.ldtr.Attr resd 1
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| 189 | .Hyper.tr.Sel resw 1
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| 190 | .Hyper.tr.PaddingSel resw 1
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| 191 | .Hyper.tr.ValidSel resw 1
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| 192 | .Hyper.tr.fFlags resw 1
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| 193 | .Hyper.tr.u64Base resq 1
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| 194 | .Hyper.tr.u32Limit resd 1
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| 195 | .Hyper.tr.Attr resd 1
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| 196 | .Hyper.SysEnter.cs resb 8
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| 197 | .Hyper.SysEnter.eip resb 8
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| 198 | .Hyper.SysEnter.esp resb 8
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| 199 | .Hyper.msrEFER resb 8
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| 200 | .Hyper.msrSTAR resb 8
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| 201 | .Hyper.msrPAT resb 8
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| 202 | .Hyper.msrLSTAR resb 8
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| 203 | .Hyper.msrCSTAR resb 8
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| 204 | .Hyper.msrSFMASK resb 8
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| 205 | .Hyper.msrKERNELGSBASE resb 8
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| 206 | .Hyper.msrApicBase resb 8
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| 207 |
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| 208 | ;
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| 209 | ; Host context state
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| 210 | ;
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| 211 | alignb 64
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| 212 | .Host.fpu resb FPUSTATE_SIZE
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| 213 |
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| 214 | %if HC_ARCH_BITS == 64 || fVBOX_WITH_HYBRID_32BIT_KERNEL
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| 215 | ;.Host.rax resq 1 - scratch
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| 216 | .Host.rbx resq 1
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| 217 | ;.Host.rcx resq 1 - scratch
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| 218 | ;.Host.rdx resq 1 - scratch
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| 219 | .Host.rdi resq 1
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| 220 | .Host.rsi resq 1
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| 221 | .Host.rbp resq 1
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| 222 | .Host.rsp resq 1
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| 223 | ;.Host.r8 resq 1 - scratch
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| 224 | ;.Host.r9 resq 1 - scratch
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| 225 | .Host.r10 resq 1
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| 226 | .Host.r11 resq 1
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| 227 | .Host.r12 resq 1
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| 228 | .Host.r13 resq 1
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| 229 | .Host.r14 resq 1
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| 230 | .Host.r15 resq 1
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| 231 | ;.Host.rip resd 1 - scratch
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| 232 | .Host.rflags resq 1
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| 233 | %endif
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| 234 | %if HC_ARCH_BITS == 32
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| 235 | ;.Host.eax resd 1 - scratch
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| 236 | .Host.ebx resd 1
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| 237 | ;.Host.edx resd 1 - scratch
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| 238 | ;.Host.ecx resd 1 - scratch
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| 239 | .Host.edi resd 1
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| 240 | .Host.esi resd 1
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| 241 | .Host.ebp resd 1
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| 242 | .Host.eflags resd 1
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| 243 | ;.Host.eip resd 1 - scratch
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| 244 | ; lss pair!
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| 245 | .Host.esp resd 1
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| 246 | %endif
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| 247 | .Host.ss resw 1
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| 248 | .Host.ssPadding resw 1
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| 249 | .Host.gs resw 1
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| 250 | .Host.gsPadding resw 1
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| 251 | .Host.fs resw 1
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| 252 | .Host.fsPadding resw 1
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| 253 | .Host.es resw 1
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| 254 | .Host.esPadding resw 1
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| 255 | .Host.ds resw 1
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| 256 | .Host.dsPadding resw 1
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| 257 | .Host.cs resw 1
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| 258 | .Host.csPadding resw 1
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| 259 |
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| 260 | %if HC_ARCH_BITS == 32 && fVBOX_WITH_HYBRID_32BIT_KERNEL == 0
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| 261 | .Host.cr0 resd 1
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| 262 | ;.Host.cr2 resd 1 - scratch
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| 263 | .Host.cr3 resd 1
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| 264 | .Host.cr4 resd 1
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| 265 |
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| 266 | .Host.dr0 resd 1
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| 267 | .Host.dr1 resd 1
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| 268 | .Host.dr2 resd 1
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| 269 | .Host.dr3 resd 1
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| 270 | .Host.dr6 resd 1
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| 271 | .Host.dr7 resd 1
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| 272 |
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| 273 | .Host.gdtr resb 6 ; GDT limit + linear address
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| 274 | .Host.gdtrPadding resw 1
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| 275 | .Host.idtr resb 6 ; IDT limit + linear address
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| 276 | .Host.idtrPadding resw 1
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| 277 | .Host.ldtr resw 1
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| 278 | .Host.ldtrPadding resw 1
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| 279 | .Host.tr resw 1
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| 280 | .Host.trPadding resw 1
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| 281 |
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| 282 | .Host.SysEnterPadding resd 1
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| 283 | .Host.SysEnter.cs resq 1
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| 284 | .Host.SysEnter.eip resq 1
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| 285 | .Host.SysEnter.esp resq 1
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| 286 | .Host.efer resq 1
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| 287 |
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| 288 | %else ; 64-bit
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| 289 |
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| 290 | .Host.cr0 resq 1
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| 291 | ;.Host.cr2 resq 1 - scratch
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| 292 | .Host.cr3 resq 1
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| 293 | .Host.cr4 resq 1
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| 294 | .Host.cr8 resq 1
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| 295 |
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| 296 | .Host.dr0 resq 1
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| 297 | .Host.dr1 resq 1
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| 298 | .Host.dr2 resq 1
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| 299 | .Host.dr3 resq 1
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| 300 | .Host.dr6 resq 1
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| 301 | .Host.dr7 resq 1
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| 302 |
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| 303 | .Host.gdtr resb 10 ; GDT limit + linear address
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| 304 | .Host.gdtrPadding resw 1
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| 305 | .Host.idtr resb 10 ; IDT limit + linear address
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| 306 | .Host.idtrPadding resw 1
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| 307 | .Host.ldtr resw 1
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| 308 | .Host.ldtrPadding resw 1
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| 309 | .Host.tr resw 1
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| 310 | .Host.trPadding resw 1
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| 311 |
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| 312 | .Host.SysEnter.cs resq 1
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| 313 | .Host.SysEnter.eip resq 1
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| 314 | .Host.SysEnter.esp resq 1
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| 315 | .Host.FSbase resq 1
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| 316 | .Host.GSbase resq 1
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| 317 | .Host.efer resq 1
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| 318 | %endif ; 64-bit
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| 319 |
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| 320 | %ifdef VBOX_WITH_CRASHDUMP_MAGIC
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| 321 | .aMagic resb 56
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| 322 | .uMagic resq 1
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| 323 | %endif
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| 324 | ;
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| 325 | ; Guest context state
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| 326 | ; (Identical to the .Hyper chunk above.)
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| 327 | ;
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| 328 | alignb 64
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| 329 | .Guest.fpu resb 512
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| 330 | .Guest.eax resq 1
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| 331 | .Guest.ecx resq 1
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| 332 | .Guest.edx resq 1
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| 333 | .Guest.ebx resq 1
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| 334 | .Guest.esp resq 1
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| 335 | .Guest.ebp resq 1
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| 336 | .Guest.esi resq 1
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| 337 | .Guest.edi resq 1
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| 338 | .Guest.r8 resq 1
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| 339 | .Guest.r9 resq 1
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| 340 | .Guest.r10 resq 1
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| 341 | .Guest.r11 resq 1
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| 342 | .Guest.r12 resq 1
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| 343 | .Guest.r13 resq 1
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| 344 | .Guest.r14 resq 1
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| 345 | .Guest.r15 resq 1
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| 346 | .Guest.es.Sel resw 1
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| 347 | .Guest.es.PaddingSel resw 1
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| 348 | .Guest.es.ValidSel resw 1
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| 349 | .Guest.es.fFlags resw 1
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| 350 | .Guest.es.u64Base resq 1
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| 351 | .Guest.es.u32Limit resd 1
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| 352 | .Guest.es.Attr resd 1
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| 353 | .Guest.cs.Sel resw 1
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| 354 | .Guest.cs.PaddingSel resw 1
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| 355 | .Guest.cs.ValidSel resw 1
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| 356 | .Guest.cs.fFlags resw 1
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| 357 | .Guest.cs.u64Base resq 1
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| 358 | .Guest.cs.u32Limit resd 1
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| 359 | .Guest.cs.Attr resd 1
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| 360 | .Guest.ss.Sel resw 1
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| 361 | .Guest.ss.PaddingSel resw 1
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| 362 | .Guest.ss.ValidSel resw 1
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| 363 | .Guest.ss.fFlags resw 1
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| 364 | .Guest.ss.u64Base resq 1
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| 365 | .Guest.ss.u32Limit resd 1
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| 366 | .Guest.ss.Attr resd 1
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| 367 | .Guest.ds.Sel resw 1
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| 368 | .Guest.ds.PaddingSel resw 1
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| 369 | .Guest.ds.ValidSel resw 1
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| 370 | .Guest.ds.fFlags resw 1
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| 371 | .Guest.ds.u64Base resq 1
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| 372 | .Guest.ds.u32Limit resd 1
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| 373 | .Guest.ds.Attr resd 1
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| 374 | .Guest.fs.Sel resw 1
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| 375 | .Guest.fs.PaddingSel resw 1
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| 376 | .Guest.fs.ValidSel resw 1
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| 377 | .Guest.fs.fFlags resw 1
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| 378 | .Guest.fs.u64Base resq 1
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| 379 | .Guest.fs.u32Limit resd 1
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| 380 | .Guest.fs.Attr resd 1
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| 381 | .Guest.gs.Sel resw 1
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| 382 | .Guest.gs.PaddingSel resw 1
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| 383 | .Guest.gs.ValidSel resw 1
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| 384 | .Guest.gs.fFlags resw 1
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| 385 | .Guest.gs.u64Base resq 1
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| 386 | .Guest.gs.u32Limit resd 1
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| 387 | .Guest.gs.Attr resd 1
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| 388 | .Guest.eip resq 1
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| 389 | .Guest.eflags resq 1
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| 390 | .Guest.cr0 resq 1
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| 391 | .Guest.cr2 resq 1
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| 392 | .Guest.cr3 resq 1
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| 393 | .Guest.cr4 resq 1
|
|---|
| 394 | .Guest.dr resq 8
|
|---|
| 395 | .Guest.gdtrPadding resw 3
|
|---|
| 396 | .Guest.gdtr resw 0
|
|---|
| 397 | .Guest.gdtr.cbGdt resw 1
|
|---|
| 398 | .Guest.gdtr.pGdt resq 1
|
|---|
| 399 | .Guest.idtrPadding resw 3
|
|---|
| 400 | .Guest.idtr resw 0
|
|---|
| 401 | .Guest.idtr.cbIdt resw 1
|
|---|
| 402 | .Guest.idtr.pIdt resq 1
|
|---|
| 403 | .Guest.ldtr.Sel resw 1
|
|---|
| 404 | .Guest.ldtr.PaddingSel resw 1
|
|---|
| 405 | .Guest.ldtr.ValidSel resw 1
|
|---|
| 406 | .Guest.ldtr.fFlags resw 1
|
|---|
| 407 | .Guest.ldtr.u64Base resq 1
|
|---|
| 408 | .Guest.ldtr.u32Limit resd 1
|
|---|
| 409 | .Guest.ldtr.Attr resd 1
|
|---|
| 410 | .Guest.tr.Sel resw 1
|
|---|
| 411 | .Guest.tr.PaddingSel resw 1
|
|---|
| 412 | .Guest.tr.ValidSel resw 1
|
|---|
| 413 | .Guest.tr.fFlags resw 1
|
|---|
| 414 | .Guest.tr.u64Base resq 1
|
|---|
| 415 | .Guest.tr.u32Limit resd 1
|
|---|
| 416 | .Guest.tr.Attr resd 1
|
|---|
| 417 | .Guest.SysEnter.cs resb 8
|
|---|
| 418 | .Guest.SysEnter.eip resb 8
|
|---|
| 419 | .Guest.SysEnter.esp resb 8
|
|---|
| 420 | .Guest.msrEFER resb 8
|
|---|
| 421 | .Guest.msrSTAR resb 8
|
|---|
| 422 | .Guest.msrPAT resb 8
|
|---|
| 423 | .Guest.msrLSTAR resb 8
|
|---|
| 424 | .Guest.msrCSTAR resb 8
|
|---|
| 425 | .Guest.msrSFMASK resb 8
|
|---|
| 426 | .Guest.msrKERNELGSBASE resb 8
|
|---|
| 427 | .Guest.msrApicBase resb 8
|
|---|
| 428 |
|
|---|
| 429 |
|
|---|
| 430 | alignb 64
|
|---|
| 431 | .GuestMsrs.au64 resq 64
|
|---|
| 432 |
|
|---|
| 433 | ;
|
|---|
| 434 | ; Other stuff.
|
|---|
| 435 | ;
|
|---|
| 436 | .fUseFlags resd 1
|
|---|
| 437 | .fChanged resd 1
|
|---|
| 438 | .offCPUM resd 1
|
|---|
| 439 | .u32RetCode resd 1
|
|---|
| 440 |
|
|---|
| 441 | %ifdef VBOX_WITH_VMMR0_DISABLE_LAPIC_NMI
|
|---|
| 442 | .pvApicBase RTR0PTR_RES 1
|
|---|
| 443 | .fApicDisVectors resd 1
|
|---|
| 444 | .fX2Apic resb 1
|
|---|
| 445 | %else
|
|---|
| 446 | .abPadding3 resb (RTR0PTR_CB + 4 + 1)
|
|---|
| 447 | %endif
|
|---|
| 448 |
|
|---|
| 449 | .fRawEntered resb 1
|
|---|
| 450 | .fRemEntered resb 1
|
|---|
| 451 |
|
|---|
| 452 | .abPadding2 resb (64 - 16 - RTR0PTR_CB - 4 - 1 - 2)
|
|---|
| 453 | endstruc
|
|---|
| 454 |
|
|---|
| 455 |
|
|---|
| 456 | ;;
|
|---|
| 457 | ; Converts the CPUM pointer to CPUMCPU
|
|---|
| 458 | ; @param %1 register name
|
|---|
| 459 | %macro CPUMCPU_FROM_CPUM 1
|
|---|
| 460 | add %1, dword [%1 + CPUM.offCPUMCPU0]
|
|---|
| 461 | %endmacro
|
|---|
| 462 |
|
|---|
| 463 | ;;
|
|---|
| 464 | ; Converts the CPUM pointer to CPUMCPU
|
|---|
| 465 | ; @param %1 register name (CPUM)
|
|---|
| 466 | ; @param %2 register name (CPUMCPU offset)
|
|---|
| 467 | %macro CPUMCPU_FROM_CPUM_WITH_OFFSET 2
|
|---|
| 468 | add %1, %2
|
|---|
| 469 | %endmacro
|
|---|
| 470 |
|
|---|
| 471 | ;;
|
|---|
| 472 | ; Converts the CPUMCPU pointer to CPUM
|
|---|
| 473 | ; @param %1 register name
|
|---|
| 474 | %macro CPUM_FROM_CPUMCPU 1
|
|---|
| 475 | sub %1, dword [%1 + CPUMCPU.offCPUM]
|
|---|
| 476 | %endmacro
|
|---|
| 477 |
|
|---|
| 478 | ;;
|
|---|
| 479 | ; Converts the CPUMCPU pointer to CPUM
|
|---|
| 480 | ; @param %1 register name (CPUM)
|
|---|
| 481 | ; @param %2 register name (CPUMCPU offset)
|
|---|
| 482 | %macro CPUM_FROM_CPUMCPU_WITH_OFFSET 2
|
|---|
| 483 | sub %1, %2
|
|---|
| 484 | %endmacro
|
|---|
