| 1 | ; $Id: CPUMInternal.mac 55229 2015-04-14 06:35:43Z vboxsync $
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| 2 | ;; @file
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| 3 | ; CPUM - Internal header file (asm).
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| 4 | ;
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| 5 |
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| 6 | ;
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| 7 | ; Copyright (C) 2006-2015 Oracle Corporation
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| 8 | ;
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| 9 | ; This file is part of VirtualBox Open Source Edition (OSE), as
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| 10 | ; available from http://www.virtualbox.org. This file is free software;
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| 11 | ; you can redistribute it and/or modify it under the terms of the GNU
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| 12 | ; General Public License (GPL) as published by the Free Software
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| 13 | ; Foundation, in version 2 as it comes in the "COPYING" file of the
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| 14 | ; VirtualBox OSE distribution. VirtualBox OSE is distributed in the
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| 15 | ; hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
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| 16 | ;
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| 17 |
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| 18 | %include "VBox/asmdefs.mac"
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| 19 | %include "VBox/vmm/cpum.mac"
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| 20 |
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| 21 | ;;
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| 22 | ; CPU info
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| 23 | struc CPUMINFO
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| 24 | .cMsrRanges resd 1 ; uint32_t
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| 25 | .fMsrMask resd 1 ; uint32_t
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| 26 | .cCpuIdLeaves resd 1 ; uint32_t
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| 27 | .iFirstExtCpuIdLeaf resd 1 ; uint32_t
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| 28 | .uPadding resd 1 ; uint32_t
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| 29 | .enmUnknownCpuIdMethod resd 1 ; CPUMUNKNOWNCPUID
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| 30 | .DefCpuId resb CPUMCPUID_size ; CPUMCPUID
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| 31 | .uScalableBusFreq resq 1 ; uint64_t
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| 32 | .paMsrRangesR0 RTR0PTR_RES 1 ; R0PTRTYPE(PCPUMMSRRANGE)
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| 33 | .paCpuIdLeavesR0 RTR0PTR_RES 1 ; R0PTRTYPE(PCPUMCPUIDLEAF)
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| 34 | .paMsrRangesR3 RTR3PTR_RES 1 ; R3PTRTYPE(PCPUMMSRRANGE)
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| 35 | .paCpuIdLeavesR3 RTR3PTR_RES 1 ; R3PTRTYPE(PCPUMCPUIDLEAF)
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| 36 | .paMsrRangesRC RTRCPTR_RES 1 ; RCPTRTYPE(PCPUMMSRRANGE)
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| 37 | .paCpuIdLeavesRC RTRCPTR_RES 1 ; RCPTRTYPE(PCPUMCPUIDLEAF)
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| 38 | endstruc
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| 39 |
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| 40 |
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| 41 | %define CPUM_USED_FPU RT_BIT(0)
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| 42 | %define CPUM_USED_FPU_SINCE_REM RT_BIT(1)
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| 43 | %define CPUM_USED_MANUAL_XMM_RESTORE RT_BIT(2)
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| 44 | %define CPUM_USE_SYSENTER RT_BIT(3)
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| 45 | %define CPUM_USE_SYSCALL RT_BIT(4)
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| 46 | %define CPUM_USE_DEBUG_REGS_HOST RT_BIT(5)
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| 47 | %define CPUM_USED_DEBUG_REGS_HOST RT_BIT(6)
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| 48 | %define CPUM_USE_DEBUG_REGS_HYPER RT_BIT(7)
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| 49 | %define CPUM_USED_DEBUG_REGS_HYPER RT_BIT(8)
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| 50 | %define CPUM_USED_DEBUG_REGS_GUEST RT_BIT(9)
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| 51 | %define CPUM_SYNC_FPU_STATE RT_BIT(16)
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| 52 | %define CPUM_SYNC_DEBUG_REGS_GUEST RT_BIT(17)
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| 53 | %define CPUM_SYNC_DEBUG_REGS_HYPER RT_BIT(18)
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| 54 | %define CPUM_USE_FFXSR_LEAKY RT_BIT(19)
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| 55 | %define CPUM_USE_SUPPORTS_LONGMODE RT_BIT(20)
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| 56 |
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| 57 | %define CPUM_HANDLER_DS 1
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| 58 | %define CPUM_HANDLER_ES 2
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| 59 | %define CPUM_HANDLER_FS 3
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| 60 | %define CPUM_HANDLER_GS 4
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| 61 | %define CPUM_HANDLER_IRET 5
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| 62 | %define CPUM_HANDLER_TYPEMASK 0ffh
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| 63 | %define CPUM_HANDLER_CTXCORE_IN_EBP RT_BIT(31)
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| 64 |
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| 65 | %define VMMGCRET_USED_FPU 040000000h
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| 66 |
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| 67 |
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| 68 | ;; if anyone figures how to do %if HC_ARCH_BITS == 64 || defined(VBOX_WITH_HYBRID_32BIT_KERNEL) in
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| 69 | ; nasm please tell / fix this hack.
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| 70 | %ifdef VBOX_WITH_HYBRID_32BIT_KERNEL
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| 71 | %define fVBOX_WITH_HYBRID_32BIT_KERNEL 1
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| 72 | %else
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| 73 | %define fVBOX_WITH_HYBRID_32BIT_KERNEL 0
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| 74 | %endif
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| 75 |
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| 76 | struc CPUM
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| 77 | ;...
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| 78 | .offCPUMCPU0 resd 1
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| 79 | .fHostUseFlags resd 1
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| 80 |
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| 81 | ; CR4 masks
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| 82 | .CR4.AndMask resd 1
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| 83 | .CR4.OrMask resd 1
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| 84 | ; entered rawmode?
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| 85 | .u8PortableCpuIdLevel resb 1
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| 86 | .fPendingRestore resb 1
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| 87 |
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| 88 | alignb 8
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| 89 | .fXStateGuestMask resq 1
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| 90 | .fXStateHostMask resq 1
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| 91 |
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| 92 | alignb 64
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| 93 | .HostFeatures resb 32
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| 94 | .GuestFeatures resb 32
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| 95 | .GuestInfo resb RTHCPTR_CB*4 + RTRCPTR_CB*2 + 4*12
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| 96 |
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| 97 | ; Patch manager saved state compatability CPUID leaf arrays
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| 98 | .aGuestCpuIdPatmStd resb 16*6
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| 99 | .aGuestCpuIdPatmExt resb 16*10
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| 100 | .aGuestCpuIdPatmCentaur resb 16*4
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| 101 |
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| 102 | alignb 8
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| 103 | .cMsrWrites resq 1
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| 104 | .cMsrWritesToIgnoredBits resq 1
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| 105 | .cMsrWritesRaiseGp resq 1
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| 106 | .cMsrWritesUnknown resq 1
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| 107 | .cMsrReads resq 1
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| 108 | .cMsrReadsRaiseGp resq 1
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| 109 | .cMsrReadsUnknown resq 1
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| 110 | endstruc
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| 111 |
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| 112 | struc CPUMCPU
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| 113 | ;
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| 114 | ; Guest context state
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| 115 | ; (Identical to the .Hyper chunk below.)
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| 116 | ;
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| 117 | .Guest resq 0
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| 118 | .Guest.eax resq 1
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| 119 | .Guest.ecx resq 1
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| 120 | .Guest.edx resq 1
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| 121 | .Guest.ebx resq 1
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| 122 | .Guest.esp resq 1
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| 123 | .Guest.ebp resq 1
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| 124 | .Guest.esi resq 1
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| 125 | .Guest.edi resq 1
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| 126 | .Guest.r8 resq 1
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| 127 | .Guest.r9 resq 1
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| 128 | .Guest.r10 resq 1
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| 129 | .Guest.r11 resq 1
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| 130 | .Guest.r12 resq 1
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| 131 | .Guest.r13 resq 1
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| 132 | .Guest.r14 resq 1
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| 133 | .Guest.r15 resq 1
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| 134 | .Guest.es.Sel resw 1
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| 135 | .Guest.es.PaddingSel resw 1
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| 136 | .Guest.es.ValidSel resw 1
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| 137 | .Guest.es.fFlags resw 1
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| 138 | .Guest.es.u64Base resq 1
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| 139 | .Guest.es.u32Limit resd 1
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| 140 | .Guest.es.Attr resd 1
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| 141 | .Guest.cs.Sel resw 1
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| 142 | .Guest.cs.PaddingSel resw 1
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| 143 | .Guest.cs.ValidSel resw 1
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| 144 | .Guest.cs.fFlags resw 1
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| 145 | .Guest.cs.u64Base resq 1
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| 146 | .Guest.cs.u32Limit resd 1
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| 147 | .Guest.cs.Attr resd 1
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| 148 | .Guest.ss.Sel resw 1
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| 149 | .Guest.ss.PaddingSel resw 1
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| 150 | .Guest.ss.ValidSel resw 1
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| 151 | .Guest.ss.fFlags resw 1
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| 152 | .Guest.ss.u64Base resq 1
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| 153 | .Guest.ss.u32Limit resd 1
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| 154 | .Guest.ss.Attr resd 1
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| 155 | .Guest.ds.Sel resw 1
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| 156 | .Guest.ds.PaddingSel resw 1
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| 157 | .Guest.ds.ValidSel resw 1
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| 158 | .Guest.ds.fFlags resw 1
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| 159 | .Guest.ds.u64Base resq 1
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| 160 | .Guest.ds.u32Limit resd 1
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| 161 | .Guest.ds.Attr resd 1
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| 162 | .Guest.fs.Sel resw 1
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| 163 | .Guest.fs.PaddingSel resw 1
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| 164 | .Guest.fs.ValidSel resw 1
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| 165 | .Guest.fs.fFlags resw 1
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| 166 | .Guest.fs.u64Base resq 1
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| 167 | .Guest.fs.u32Limit resd 1
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| 168 | .Guest.fs.Attr resd 1
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| 169 | .Guest.gs.Sel resw 1
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| 170 | .Guest.gs.PaddingSel resw 1
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| 171 | .Guest.gs.ValidSel resw 1
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| 172 | .Guest.gs.fFlags resw 1
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| 173 | .Guest.gs.u64Base resq 1
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| 174 | .Guest.gs.u32Limit resd 1
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| 175 | .Guest.gs.Attr resd 1
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| 176 | .Guest.eip resq 1
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| 177 | .Guest.eflags resq 1
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| 178 | .Guest.cr0 resq 1
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| 179 | .Guest.cr2 resq 1
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| 180 | .Guest.cr3 resq 1
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| 181 | .Guest.cr4 resq 1
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| 182 | .Guest.dr resq 8
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| 183 | .Guest.gdtrPadding resw 3
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| 184 | .Guest.gdtr resw 0
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| 185 | .Guest.gdtr.cbGdt resw 1
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| 186 | .Guest.gdtr.pGdt resq 1
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| 187 | .Guest.idtrPadding resw 3
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| 188 | .Guest.idtr resw 0
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| 189 | .Guest.idtr.cbIdt resw 1
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| 190 | .Guest.idtr.pIdt resq 1
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| 191 | .Guest.ldtr.Sel resw 1
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| 192 | .Guest.ldtr.PaddingSel resw 1
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| 193 | .Guest.ldtr.ValidSel resw 1
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| 194 | .Guest.ldtr.fFlags resw 1
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| 195 | .Guest.ldtr.u64Base resq 1
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| 196 | .Guest.ldtr.u32Limit resd 1
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| 197 | .Guest.ldtr.Attr resd 1
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| 198 | .Guest.tr.Sel resw 1
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| 199 | .Guest.tr.PaddingSel resw 1
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| 200 | .Guest.tr.ValidSel resw 1
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| 201 | .Guest.tr.fFlags resw 1
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| 202 | .Guest.tr.u64Base resq 1
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| 203 | .Guest.tr.u32Limit resd 1
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| 204 | .Guest.tr.Attr resd 1
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| 205 | .Guest.SysEnter.cs resb 8
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| 206 | .Guest.SysEnter.eip resb 8
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| 207 | .Guest.SysEnter.esp resb 8
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| 208 | .Guest.msrEFER resb 8
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| 209 | .Guest.msrSTAR resb 8
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| 210 | .Guest.msrPAT resb 8
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| 211 | .Guest.msrLSTAR resb 8
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| 212 | .Guest.msrCSTAR resb 8
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| 213 | .Guest.msrSFMASK resb 8
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| 214 | .Guest.msrKERNELGSBASE resb 8
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| 215 | .Guest.msrApicBase resb 8
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| 216 | .Guest.aXcr resq 2
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| 217 | .Guest.fXStateMask resq 1
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| 218 | .Guest.pXStateR0 RTR0PTR_RES 1
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| 219 | .Guest.pXStateR3 RTR3PTR_RES 1
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| 220 | .Guest.pXStateRC RTRCPTR_RES 1
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| 221 | .Guest.aoffXState resw 64
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| 222 |
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| 223 | alignb 64
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| 224 | .GuestMsrs resq 0
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| 225 | .GuestMsrs.au64 resq 64
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| 226 |
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| 227 | ;
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| 228 | ; Other stuff.
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| 229 | ;
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| 230 | .fUseFlags resd 1
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| 231 | .fChanged resd 1
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| 232 | .offCPUM resd 1
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| 233 | .u32RetCode resd 1
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| 234 |
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| 235 | %ifdef VBOX_WITH_VMMR0_DISABLE_LAPIC_NMI
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| 236 | .pvApicBase RTR0PTR_RES 1
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| 237 | .fApicDisVectors resd 1
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| 238 | .fX2Apic resb 1
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| 239 | %else
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| 240 | .abPadding3 resb (RTR0PTR_CB + 4 + 1)
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| 241 | %endif
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| 242 |
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| 243 | .fRawEntered resb 1
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| 244 | .fRemEntered resb 1
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| 245 |
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| 246 | .abPadding2 resb (64 - 16 - RTR0PTR_CB - 4 - 1 - 2)
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| 247 |
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| 248 | ;
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| 249 | ; Host context state
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| 250 | ;
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| 251 | alignb 64
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| 252 | .Host resb 0
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| 253 | %if HC_ARCH_BITS == 64 || fVBOX_WITH_HYBRID_32BIT_KERNEL
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| 254 | ;.Host.rax resq 1 - scratch
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| 255 | .Host.rbx resq 1
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| 256 | ;.Host.rcx resq 1 - scratch
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| 257 | ;.Host.rdx resq 1 - scratch
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| 258 | .Host.rdi resq 1
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| 259 | .Host.rsi resq 1
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| 260 | .Host.rbp resq 1
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| 261 | .Host.rsp resq 1
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| 262 | ;.Host.r8 resq 1 - scratch
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| 263 | ;.Host.r9 resq 1 - scratch
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| 264 | .Host.r10 resq 1
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| 265 | .Host.r11 resq 1
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| 266 | .Host.r12 resq 1
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| 267 | .Host.r13 resq 1
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| 268 | .Host.r14 resq 1
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| 269 | .Host.r15 resq 1
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| 270 | ;.Host.rip resd 1 - scratch
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| 271 | .Host.rflags resq 1
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| 272 | %endif
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| 273 | %if HC_ARCH_BITS == 32
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| 274 | ;.Host.eax resd 1 - scratch
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| 275 | .Host.ebx resd 1
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| 276 | ;.Host.edx resd 1 - scratch
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| 277 | ;.Host.ecx resd 1 - scratch
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| 278 | .Host.edi resd 1
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| 279 | .Host.esi resd 1
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| 280 | .Host.ebp resd 1
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| 281 | .Host.eflags resd 1
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| 282 | ;.Host.eip resd 1 - scratch
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| 283 | ; lss pair!
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| 284 | .Host.esp resd 1
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| 285 | %endif
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| 286 | .Host.ss resw 1
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| 287 | .Host.ssPadding resw 1
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| 288 | .Host.gs resw 1
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| 289 | .Host.gsPadding resw 1
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| 290 | .Host.fs resw 1
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| 291 | .Host.fsPadding resw 1
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| 292 | .Host.es resw 1
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| 293 | .Host.esPadding resw 1
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| 294 | .Host.ds resw 1
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| 295 | .Host.dsPadding resw 1
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| 296 | .Host.cs resw 1
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| 297 | .Host.csPadding resw 1
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| 298 |
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| 299 | %if HC_ARCH_BITS == 32 && fVBOX_WITH_HYBRID_32BIT_KERNEL == 0
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| 300 | .Host.cr0 resd 1
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| 301 | ;.Host.cr2 resd 1 - scratch
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| 302 | .Host.cr3 resd 1
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| 303 | .Host.cr4 resd 1
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| 304 |
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| 305 | .Host.dr0 resd 1
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| 306 | .Host.dr1 resd 1
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| 307 | .Host.dr2 resd 1
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| 308 | .Host.dr3 resd 1
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| 309 | .Host.dr6 resd 1
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| 310 | .Host.dr7 resd 1
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| 311 |
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| 312 | .Host.gdtr resb 6 ; GDT limit + linear address
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| 313 | .Host.gdtrPadding resw 1
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| 314 | .Host.idtr resb 6 ; IDT limit + linear address
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| 315 | .Host.idtrPadding resw 1
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| 316 | .Host.ldtr resw 1
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| 317 | .Host.ldtrPadding resw 1
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| 318 | .Host.tr resw 1
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| 319 | .Host.trPadding resw 1
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| 320 |
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| 321 | .Host.SysEnterPadding resd 1
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| 322 | .Host.SysEnter.cs resq 1
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| 323 | .Host.SysEnter.eip resq 1
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| 324 | .Host.SysEnter.esp resq 1
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| 325 | .Host.efer resq 1
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| 326 | .Host.auPadding resb (20)
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| 327 |
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| 328 | %else ; 64-bit
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| 329 |
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| 330 | .Host.cr0 resq 1
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| 331 | ;.Host.cr2 resq 1 - scratch
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| 332 | .Host.cr3 resq 1
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| 333 | .Host.cr4 resq 1
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| 334 | .Host.cr8 resq 1
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| 335 |
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| 336 | .Host.dr0 resq 1
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| 337 | .Host.dr1 resq 1
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| 338 | .Host.dr2 resq 1
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| 339 | .Host.dr3 resq 1
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| 340 | .Host.dr6 resq 1
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| 341 | .Host.dr7 resq 1
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| 342 |
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| 343 | .Host.gdtr resb 10 ; GDT limit + linear address
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| 344 | .Host.gdtrPadding resw 1
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| 345 | .Host.idtr resb 10 ; IDT limit + linear address
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| 346 | .Host.idtrPadding resw 1
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| 347 | .Host.ldtr resw 1
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| 348 | .Host.ldtrPadding resw 1
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| 349 | .Host.tr resw 1
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| 350 | .Host.trPadding resw 1
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| 351 |
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| 352 | .Host.SysEnter.cs resq 1
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| 353 | .Host.SysEnter.eip resq 1
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| 354 | .Host.SysEnter.esp resq 1
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| 355 | .Host.FSbase resq 1
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| 356 | .Host.GSbase resq 1
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| 357 | .Host.efer resq 1
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| 358 | %if fVBOX_WITH_HYBRID_32BIT_KERNEL
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| 359 | .Host.auPadding resb 54
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| 360 | %else
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| 361 | .Host.auPadding resb 4
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| 362 | %endif
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| 363 | %endif ; 64-bit
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| 364 | .Host.pXStateRC RTRCPTR_RES 1
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| 365 | alignb RTR0PTR_CB
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| 366 | .Host.pXStateR0 RTR0PTR_RES 1
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| 367 | .Host.pXStateR3 RTR3PTR_RES 1
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| 368 | alignb 8
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| 369 | .Host.xcr0 resq 1
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| 370 | .Host.fXStateMask resq 1
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| 371 |
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| 372 | ;
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| 373 | ; Hypervisor Context (same as .Guest above).
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| 374 | ;
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| 375 | alignb 64
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| 376 | .Hyper resq 0
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| 377 | .Hyper.eax resq 1
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| 378 | .Hyper.ecx resq 1
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| 379 | .Hyper.edx resq 1
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| 380 | .Hyper.ebx resq 1
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| 381 | .Hyper.esp resq 1
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| 382 | .Hyper.ebp resq 1
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| 383 | .Hyper.esi resq 1
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| 384 | .Hyper.edi resq 1
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| 385 | .Hyper.r8 resq 1
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| 386 | .Hyper.r9 resq 1
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| 387 | .Hyper.r10 resq 1
|
|---|
| 388 | .Hyper.r11 resq 1
|
|---|
| 389 | .Hyper.r12 resq 1
|
|---|
| 390 | .Hyper.r13 resq 1
|
|---|
| 391 | .Hyper.r14 resq 1
|
|---|
| 392 | .Hyper.r15 resq 1
|
|---|
| 393 | .Hyper.es.Sel resw 1
|
|---|
| 394 | .Hyper.es.PaddingSel resw 1
|
|---|
| 395 | .Hyper.es.ValidSel resw 1
|
|---|
| 396 | .Hyper.es.fFlags resw 1
|
|---|
| 397 | .Hyper.es.u64Base resq 1
|
|---|
| 398 | .Hyper.es.u32Limit resd 1
|
|---|
| 399 | .Hyper.es.Attr resd 1
|
|---|
| 400 | .Hyper.cs.Sel resw 1
|
|---|
| 401 | .Hyper.cs.PaddingSel resw 1
|
|---|
| 402 | .Hyper.cs.ValidSel resw 1
|
|---|
| 403 | .Hyper.cs.fFlags resw 1
|
|---|
| 404 | .Hyper.cs.u64Base resq 1
|
|---|
| 405 | .Hyper.cs.u32Limit resd 1
|
|---|
| 406 | .Hyper.cs.Attr resd 1
|
|---|
| 407 | .Hyper.ss.Sel resw 1
|
|---|
| 408 | .Hyper.ss.PaddingSel resw 1
|
|---|
| 409 | .Hyper.ss.ValidSel resw 1
|
|---|
| 410 | .Hyper.ss.fFlags resw 1
|
|---|
| 411 | .Hyper.ss.u64Base resq 1
|
|---|
| 412 | .Hyper.ss.u32Limit resd 1
|
|---|
| 413 | .Hyper.ss.Attr resd 1
|
|---|
| 414 | .Hyper.ds.Sel resw 1
|
|---|
| 415 | .Hyper.ds.PaddingSel resw 1
|
|---|
| 416 | .Hyper.ds.ValidSel resw 1
|
|---|
| 417 | .Hyper.ds.fFlags resw 1
|
|---|
| 418 | .Hyper.ds.u64Base resq 1
|
|---|
| 419 | .Hyper.ds.u32Limit resd 1
|
|---|
| 420 | .Hyper.ds.Attr resd 1
|
|---|
| 421 | .Hyper.fs.Sel resw 1
|
|---|
| 422 | .Hyper.fs.PaddingSel resw 1
|
|---|
| 423 | .Hyper.fs.ValidSel resw 1
|
|---|
| 424 | .Hyper.fs.fFlags resw 1
|
|---|
| 425 | .Hyper.fs.u64Base resq 1
|
|---|
| 426 | .Hyper.fs.u32Limit resd 1
|
|---|
| 427 | .Hyper.fs.Attr resd 1
|
|---|
| 428 | .Hyper.gs.Sel resw 1
|
|---|
| 429 | .Hyper.gs.PaddingSel resw 1
|
|---|
| 430 | .Hyper.gs.ValidSel resw 1
|
|---|
| 431 | .Hyper.gs.fFlags resw 1
|
|---|
| 432 | .Hyper.gs.u64Base resq 1
|
|---|
| 433 | .Hyper.gs.u32Limit resd 1
|
|---|
| 434 | .Hyper.gs.Attr resd 1
|
|---|
| 435 | .Hyper.eip resq 1
|
|---|
| 436 | .Hyper.eflags resq 1
|
|---|
| 437 | .Hyper.cr0 resq 1
|
|---|
| 438 | .Hyper.cr2 resq 1
|
|---|
| 439 | .Hyper.cr3 resq 1
|
|---|
| 440 | .Hyper.cr4 resq 1
|
|---|
| 441 | .Hyper.dr resq 8
|
|---|
| 442 | .Hyper.gdtrPadding resw 3
|
|---|
| 443 | .Hyper.gdtr resw 0
|
|---|
| 444 | .Hyper.gdtr.cbGdt resw 1
|
|---|
| 445 | .Hyper.gdtr.pGdt resq 1
|
|---|
| 446 | .Hyper.idtrPadding resw 3
|
|---|
| 447 | .Hyper.idtr resw 0
|
|---|
| 448 | .Hyper.idtr.cbIdt resw 1
|
|---|
| 449 | .Hyper.idtr.pIdt resq 1
|
|---|
| 450 | .Hyper.ldtr.Sel resw 1
|
|---|
| 451 | .Hyper.ldtr.PaddingSel resw 1
|
|---|
| 452 | .Hyper.ldtr.ValidSel resw 1
|
|---|
| 453 | .Hyper.ldtr.fFlags resw 1
|
|---|
| 454 | .Hyper.ldtr.u64Base resq 1
|
|---|
| 455 | .Hyper.ldtr.u32Limit resd 1
|
|---|
| 456 | .Hyper.ldtr.Attr resd 1
|
|---|
| 457 | .Hyper.tr.Sel resw 1
|
|---|
| 458 | .Hyper.tr.PaddingSel resw 1
|
|---|
| 459 | .Hyper.tr.ValidSel resw 1
|
|---|
| 460 | .Hyper.tr.fFlags resw 1
|
|---|
| 461 | .Hyper.tr.u64Base resq 1
|
|---|
| 462 | .Hyper.tr.u32Limit resd 1
|
|---|
| 463 | .Hyper.tr.Attr resd 1
|
|---|
| 464 | .Hyper.SysEnter.cs resb 8
|
|---|
| 465 | .Hyper.SysEnter.eip resb 8
|
|---|
| 466 | .Hyper.SysEnter.esp resb 8
|
|---|
| 467 | .Hyper.msrEFER resb 8
|
|---|
| 468 | .Hyper.msrSTAR resb 8
|
|---|
| 469 | .Hyper.msrPAT resb 8
|
|---|
| 470 | .Hyper.msrLSTAR resb 8
|
|---|
| 471 | .Hyper.msrCSTAR resb 8
|
|---|
| 472 | .Hyper.msrSFMASK resb 8
|
|---|
| 473 | .Hyper.msrKERNELGSBASE resb 8
|
|---|
| 474 | .Hyper.msrApicBase resb 8
|
|---|
| 475 | .Hyper.aXcr resq 2
|
|---|
| 476 | .Hyper.fXStateMask resq 1
|
|---|
| 477 | .Hyper.pXStateR0 RTR0PTR_RES 1
|
|---|
| 478 | .Hyper.pXStateR3 RTR3PTR_RES 1
|
|---|
| 479 | .Hyper.pXStateRC RTRCPTR_RES 1
|
|---|
| 480 | .Hyper.aoffXState resw 64
|
|---|
| 481 | alignb 64
|
|---|
| 482 |
|
|---|
| 483 | %ifdef VBOX_WITH_CRASHDUMP_MAGIC
|
|---|
| 484 | .aMagic resb 56
|
|---|
| 485 | .uMagic resq 1
|
|---|
| 486 | %endif
|
|---|
| 487 | endstruc
|
|---|
| 488 |
|
|---|
| 489 |
|
|---|
| 490 | ;;
|
|---|
| 491 | ; Converts the CPUM pointer to CPUMCPU
|
|---|
| 492 | ; @param %1 register name
|
|---|
| 493 | %macro CPUMCPU_FROM_CPUM 1
|
|---|
| 494 | add %1, dword [%1 + CPUM.offCPUMCPU0]
|
|---|
| 495 | %endmacro
|
|---|
| 496 |
|
|---|
| 497 | ;;
|
|---|
| 498 | ; Converts the CPUM pointer to CPUMCPU
|
|---|
| 499 | ; @param %1 register name (CPUM)
|
|---|
| 500 | ; @param %2 register name (CPUMCPU offset)
|
|---|
| 501 | %macro CPUMCPU_FROM_CPUM_WITH_OFFSET 2
|
|---|
| 502 | add %1, %2
|
|---|
| 503 | %endmacro
|
|---|
| 504 |
|
|---|
| 505 | ;;
|
|---|
| 506 | ; Converts the CPUMCPU pointer to CPUM
|
|---|
| 507 | ; @param %1 register name
|
|---|
| 508 | %macro CPUM_FROM_CPUMCPU 1
|
|---|
| 509 | sub %1, dword [%1 + CPUMCPU.offCPUM]
|
|---|
| 510 | %endmacro
|
|---|
| 511 |
|
|---|
| 512 | ;;
|
|---|
| 513 | ; Converts the CPUMCPU pointer to CPUM
|
|---|
| 514 | ; @param %1 register name (CPUM)
|
|---|
| 515 | ; @param %2 register name (CPUMCPU offset)
|
|---|
| 516 | %macro CPUM_FROM_CPUMCPU_WITH_OFFSET 2
|
|---|
| 517 | sub %1, %2
|
|---|
| 518 | %endmacro
|
|---|
| 519 |
|
|---|
