VirtualBox

source: vbox/trunk/src/VBox/VMM/include/CPUMInternal.mac@ 69518

Last change on this file since 69518 was 69221, checked in by vboxsync, 7 years ago

VMM: scm cleanups

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1; $Id: CPUMInternal.mac 69221 2017-10-24 15:07:46Z vboxsync $
2;; @file
3; CPUM - Internal header file (asm).
4;
5
6;
7; Copyright (C) 2006-2017 Oracle Corporation
8;
9; This file is part of VirtualBox Open Source Edition (OSE), as
10; available from http://www.virtualbox.org. This file is free software;
11; you can redistribute it and/or modify it under the terms of the GNU
12; General Public License (GPL) as published by the Free Software
13; Foundation, in version 2 as it comes in the "COPYING" file of the
14; VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15; hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16;
17
18%include "VBox/asmdefs.mac"
19%include "VBox/vmm/cpum.mac"
20
21;; Check sanity.
22%ifdef VBOX_WITH_KERNEL_USING_XMM
23 %ifndef IN_RING0
24 %error "What? We've got code assuming VBOX_WITH_KERNEL_USING_XMM is only defined in ring-0!"
25 %endif
26%endif
27
28;; For numeric expressions
29%ifdef RT_ARCH_AMD64
30 %define CPUM_IS_AMD64 1
31%else
32 %define CPUM_IS_AMD64 0
33%endif
34
35
36;;
37; CPU info
38struc CPUMINFO
39 .cMsrRanges resd 1 ; uint32_t
40 .fMsrMask resd 1 ; uint32_t
41 .fMxCsrMask resd 1 ; uint32_t
42 .cCpuIdLeaves resd 1 ; uint32_t
43 .iFirstExtCpuIdLeaf resd 1 ; uint32_t
44 .enmUnknownCpuIdMethod resd 1 ; CPUMUNKNOWNCPUID
45 .DefCpuId resb CPUMCPUID_size ; CPUMCPUID
46 .uScalableBusFreq resq 1 ; uint64_t
47 .paMsrRangesR0 RTR0PTR_RES 1 ; R0PTRTYPE(PCPUMMSRRANGE)
48 .paCpuIdLeavesR0 RTR0PTR_RES 1 ; R0PTRTYPE(PCPUMCPUIDLEAF)
49 .paMsrRangesR3 RTR3PTR_RES 1 ; R3PTRTYPE(PCPUMMSRRANGE)
50 .paCpuIdLeavesR3 RTR3PTR_RES 1 ; R3PTRTYPE(PCPUMCPUIDLEAF)
51 .paMsrRangesRC RTRCPTR_RES 1 ; RCPTRTYPE(PCPUMMSRRANGE)
52 .paCpuIdLeavesRC RTRCPTR_RES 1 ; RCPTRTYPE(PCPUMCPUIDLEAF)
53endstruc
54
55
56%define CPUM_USED_FPU_HOST RT_BIT(0)
57%define CPUM_USED_FPU_GUEST RT_BIT(10)
58%define CPUM_USED_FPU_SINCE_REM RT_BIT(1)
59%define CPUM_USED_MANUAL_XMM_RESTORE RT_BIT(2)
60%define CPUM_USE_SYSENTER RT_BIT(3)
61%define CPUM_USE_SYSCALL RT_BIT(4)
62%define CPUM_USE_DEBUG_REGS_HOST RT_BIT(5)
63%define CPUM_USED_DEBUG_REGS_HOST RT_BIT(6)
64%define CPUM_USE_DEBUG_REGS_HYPER RT_BIT(7)
65%define CPUM_USED_DEBUG_REGS_HYPER RT_BIT(8)
66%define CPUM_USED_DEBUG_REGS_GUEST RT_BIT(9)
67%define CPUM_SYNC_FPU_STATE RT_BIT(16)
68%define CPUM_SYNC_DEBUG_REGS_GUEST RT_BIT(17)
69%define CPUM_SYNC_DEBUG_REGS_HYPER RT_BIT(18)
70%define CPUM_USE_FFXSR_LEAKY RT_BIT(19)
71%define CPUM_USE_SUPPORTS_LONGMODE RT_BIT(20)
72
73%define CPUM_HANDLER_DS 1
74%define CPUM_HANDLER_ES 2
75%define CPUM_HANDLER_FS 3
76%define CPUM_HANDLER_GS 4
77%define CPUM_HANDLER_IRET 5
78%define CPUM_HANDLER_TYPEMASK 0ffh
79%define CPUM_HANDLER_CTXCORE_IN_EBP RT_BIT(31)
80
81
82struc CPUM
83 ;...
84 .offCPUMCPU0 resd 1
85 .fHostUseFlags resd 1
86
87 ; CR4 masks
88 .CR4.AndMask resd 1
89 .CR4.OrMask resd 1
90 ; entered rawmode?
91 .u8PortableCpuIdLevel resb 1
92 .fPendingRestore resb 1
93
94 alignb 8
95 .fXStateGuestMask resq 1
96 .fXStateHostMask resq 1
97
98 alignb 64
99 .HostFeatures resb 32
100 .GuestFeatures resb 32
101 .GuestInfo resb RTHCPTR_CB*4 + RTRCPTR_CB*2 + 4*12
102
103 ; Patch manager saved state compatability CPUID leaf arrays
104 .aGuestCpuIdPatmStd resb 16*6
105 .aGuestCpuIdPatmExt resb 16*10
106 .aGuestCpuIdPatmCentaur resb 16*4
107
108 alignb 8
109 .cMsrWrites resq 1
110 .cMsrWritesToIgnoredBits resq 1
111 .cMsrWritesRaiseGp resq 1
112 .cMsrWritesUnknown resq 1
113 .cMsrReads resq 1
114 .cMsrReadsRaiseGp resq 1
115 .cMsrReadsUnknown resq 1
116endstruc
117
118struc CPUMCPU
119 ;
120 ; Guest context state
121 ; (Identical to the .Hyper chunk below.)
122 ;
123 .Guest resq 0
124 .Guest.eax resq 1
125 .Guest.ecx resq 1
126 .Guest.edx resq 1
127 .Guest.ebx resq 1
128 .Guest.esp resq 1
129 .Guest.ebp resq 1
130 .Guest.esi resq 1
131 .Guest.edi resq 1
132 .Guest.r8 resq 1
133 .Guest.r9 resq 1
134 .Guest.r10 resq 1
135 .Guest.r11 resq 1
136 .Guest.r12 resq 1
137 .Guest.r13 resq 1
138 .Guest.r14 resq 1
139 .Guest.r15 resq 1
140 .Guest.es.Sel resw 1
141 .Guest.es.PaddingSel resw 1
142 .Guest.es.ValidSel resw 1
143 .Guest.es.fFlags resw 1
144 .Guest.es.u64Base resq 1
145 .Guest.es.u32Limit resd 1
146 .Guest.es.Attr resd 1
147 .Guest.cs.Sel resw 1
148 .Guest.cs.PaddingSel resw 1
149 .Guest.cs.ValidSel resw 1
150 .Guest.cs.fFlags resw 1
151 .Guest.cs.u64Base resq 1
152 .Guest.cs.u32Limit resd 1
153 .Guest.cs.Attr resd 1
154 .Guest.ss.Sel resw 1
155 .Guest.ss.PaddingSel resw 1
156 .Guest.ss.ValidSel resw 1
157 .Guest.ss.fFlags resw 1
158 .Guest.ss.u64Base resq 1
159 .Guest.ss.u32Limit resd 1
160 .Guest.ss.Attr resd 1
161 .Guest.ds.Sel resw 1
162 .Guest.ds.PaddingSel resw 1
163 .Guest.ds.ValidSel resw 1
164 .Guest.ds.fFlags resw 1
165 .Guest.ds.u64Base resq 1
166 .Guest.ds.u32Limit resd 1
167 .Guest.ds.Attr resd 1
168 .Guest.fs.Sel resw 1
169 .Guest.fs.PaddingSel resw 1
170 .Guest.fs.ValidSel resw 1
171 .Guest.fs.fFlags resw 1
172 .Guest.fs.u64Base resq 1
173 .Guest.fs.u32Limit resd 1
174 .Guest.fs.Attr resd 1
175 .Guest.gs.Sel resw 1
176 .Guest.gs.PaddingSel resw 1
177 .Guest.gs.ValidSel resw 1
178 .Guest.gs.fFlags resw 1
179 .Guest.gs.u64Base resq 1
180 .Guest.gs.u32Limit resd 1
181 .Guest.gs.Attr resd 1
182 .Guest.eip resq 1
183 .Guest.eflags resq 1
184 .Guest.cr0 resq 1
185 .Guest.cr2 resq 1
186 .Guest.cr3 resq 1
187 .Guest.cr4 resq 1
188 .Guest.dr resq 8
189 .Guest.gdtrPadding resw 3
190 .Guest.gdtr resw 0
191 .Guest.gdtr.cbGdt resw 1
192 .Guest.gdtr.pGdt resq 1
193 .Guest.idtrPadding resw 3
194 .Guest.idtr resw 0
195 .Guest.idtr.cbIdt resw 1
196 .Guest.idtr.pIdt resq 1
197 .Guest.ldtr.Sel resw 1
198 .Guest.ldtr.PaddingSel resw 1
199 .Guest.ldtr.ValidSel resw 1
200 .Guest.ldtr.fFlags resw 1
201 .Guest.ldtr.u64Base resq 1
202 .Guest.ldtr.u32Limit resd 1
203 .Guest.ldtr.Attr resd 1
204 .Guest.tr.Sel resw 1
205 .Guest.tr.PaddingSel resw 1
206 .Guest.tr.ValidSel resw 1
207 .Guest.tr.fFlags resw 1
208 .Guest.tr.u64Base resq 1
209 .Guest.tr.u32Limit resd 1
210 .Guest.tr.Attr resd 1
211 .Guest.SysEnter.cs resb 8
212 .Guest.SysEnter.eip resb 8
213 .Guest.SysEnter.esp resb 8
214 .Guest.msrEFER resb 8
215 .Guest.msrSTAR resb 8
216 .Guest.msrPAT resb 8
217 .Guest.msrLSTAR resb 8
218 .Guest.msrCSTAR resb 8
219 .Guest.msrSFMASK resb 8
220 .Guest.msrKERNELGSBASE resb 8
221 .Guest.uMsrPadding0 resb 8
222 .Guest.aXcr resq 2
223 .Guest.fXStateMask resq 1
224 .Guest.pXStateR0 RTR0PTR_RES 1
225 .Guest.pXStateR3 RTR3PTR_RES 1
226 .Guest.pXStateRC RTRCPTR_RES 1
227 .Guest.aoffXState resw 64
228%if HC_ARCH_BITS == 64
229 .Guest.abPadding resb 4
230%else
231 .Guest.abPadding resb 12
232%endif
233 .Guest.hwvirt.svm.uMsrHSavePa resq 1
234 .Guest.hwvirt.svm.GCPhysVmcb resq 1
235 .Guest.hwvirt.svm.pVmcbR0 RTR0PTR_RES 1
236 .Guest.hwvirt.svm.pVmcbR3 RTR3PTR_RES 1
237%if HC_ARCH_BITS == 32
238 .Guest.hwvirt.svm.abPadding0 resb 8
239%endif
240 .Guest.hwvirt.svm.HostState resb 184
241 .Guest.hwvirt.svm.fGif resb 1
242 .Guest.hwvirt.svm.u8Padding0 resb 1
243 .Guest.hwvirt.svm.cPauseFilter resw 1
244 .Guest.hwvirt.svm.cPauseFilterThreshold resw 1
245 .Guest.hwvirt.svm.fInterceptEvents resb 1
246 .Guest.hwvirt.svm.u8Padding1 resb 1
247 .Guest.hwvirt.svm.pvMsrBitmapR0 RTR0PTR_RES 1
248 .Guest.hwvirt.svm.pvMsrBitmapR3 RTR3PTR_RES 1
249 .Guest.hwvirt.svm.pvIoBitmapR0 RTR0PTR_RES 1
250 .Guest.hwvirt.svm.pvIoBitmapR3 RTR3PTR_RES 1
251 .Guest.hwvirt.svm.HCPhysVmcb RTHCPHYS_RES 1
252%if HC_ARCH_BITS == 32
253 .Guest.hwvirt.svm.abPadding2 resb 16
254%endif
255 .Guest.hwvirt.fLocalForcedActions resd 1
256 alignb 64
257
258 .GuestMsrs resq 0
259 .GuestMsrs.au64 resq 64
260
261 ;
262 ; Other stuff.
263 ;
264 .fUseFlags resd 1
265 .fChanged resd 1
266 .offCPUM resd 1
267 .u32RetCode resd 1
268
269%ifdef VBOX_WITH_VMMR0_DISABLE_LAPIC_NMI
270 .pvApicBase RTR0PTR_RES 1
271 .fApicDisVectors resd 1
272 .fX2Apic resb 1
273%else
274 .abPadding3 resb (RTR0PTR_CB + 4 + 1)
275%endif
276
277 .fRawEntered resb 1
278 .fRemEntered resb 1
279 .fCpuIdApicFeatureVisible resb 1
280
281 .abPadding2 resb (64 - 16 - RTR0PTR_CB - 4 - 1 - 3)
282
283 ;
284 ; Host context state
285 ;
286 alignb 64
287 .Host resb 0
288%if HC_ARCH_BITS == 64
289 ;.Host.rax resq 1 - scratch
290 .Host.rbx resq 1
291 ;.Host.rcx resq 1 - scratch
292 ;.Host.rdx resq 1 - scratch
293 .Host.rdi resq 1
294 .Host.rsi resq 1
295 .Host.rbp resq 1
296 .Host.rsp resq 1
297 ;.Host.r8 resq 1 - scratch
298 ;.Host.r9 resq 1 - scratch
299 .Host.r10 resq 1
300 .Host.r11 resq 1
301 .Host.r12 resq 1
302 .Host.r13 resq 1
303 .Host.r14 resq 1
304 .Host.r15 resq 1
305 ;.Host.rip resd 1 - scratch
306 .Host.rflags resq 1
307%endif
308%if HC_ARCH_BITS == 32
309 ;.Host.eax resd 1 - scratch
310 .Host.ebx resd 1
311 ;.Host.edx resd 1 - scratch
312 ;.Host.ecx resd 1 - scratch
313 .Host.edi resd 1
314 .Host.esi resd 1
315 .Host.ebp resd 1
316 .Host.eflags resd 1
317 ;.Host.eip resd 1 - scratch
318 ; lss pair!
319 .Host.esp resd 1
320%endif
321 .Host.ss resw 1
322 .Host.ssPadding resw 1
323 .Host.gs resw 1
324 .Host.gsPadding resw 1
325 .Host.fs resw 1
326 .Host.fsPadding resw 1
327 .Host.es resw 1
328 .Host.esPadding resw 1
329 .Host.ds resw 1
330 .Host.dsPadding resw 1
331 .Host.cs resw 1
332 .Host.csPadding resw 1
333
334%if HC_ARCH_BITS == 32
335 .Host.cr0 resd 1
336 ;.Host.cr2 resd 1 - scratch
337 .Host.cr3 resd 1
338 .Host.cr4 resd 1
339 .Host.cr0Fpu resd 1
340
341 .Host.dr0 resd 1
342 .Host.dr1 resd 1
343 .Host.dr2 resd 1
344 .Host.dr3 resd 1
345 .Host.dr6 resd 1
346 .Host.dr7 resd 1
347
348 .Host.gdtr resb 6 ; GDT limit + linear address
349 .Host.gdtrPadding resw 1
350 .Host.idtr resb 6 ; IDT limit + linear address
351 .Host.idtrPadding resw 1
352 .Host.ldtr resw 1
353 .Host.ldtrPadding resw 1
354 .Host.tr resw 1
355 .Host.trPadding resw 1
356
357 alignb 8
358 .Host.SysEnter.cs resq 1
359 .Host.SysEnter.eip resq 1
360 .Host.SysEnter.esp resq 1
361 .Host.efer resq 1
362 .Host.auPadding resb (20)
363
364%else ; 64-bit
365
366 .Host.cr0Fpu:
367 .Host.cr0 resq 1
368 ;.Host.cr2 resq 1 - scratch
369 .Host.cr3 resq 1
370 .Host.cr4 resq 1
371 .Host.cr8 resq 1
372
373 .Host.dr0 resq 1
374 .Host.dr1 resq 1
375 .Host.dr2 resq 1
376 .Host.dr3 resq 1
377 .Host.dr6 resq 1
378 .Host.dr7 resq 1
379
380 .Host.gdtr resb 10 ; GDT limit + linear address
381 .Host.gdtrPadding resw 1
382 .Host.idtr resb 10 ; IDT limit + linear address
383 .Host.idtrPadding resw 1
384 .Host.ldtr resw 1
385 .Host.ldtrPadding resw 1
386 .Host.tr resw 1
387 .Host.trPadding resw 1
388
389 .Host.SysEnter.cs resq 1
390 .Host.SysEnter.eip resq 1
391 .Host.SysEnter.esp resq 1
392 .Host.FSbase resq 1
393 .Host.GSbase resq 1
394 .Host.efer resq 1
395 .Host.auPadding resb 4
396%endif ; 64-bit
397 .Host.pXStateRC RTRCPTR_RES 1
398 alignb RTR0PTR_CB
399 .Host.pXStateR0 RTR0PTR_RES 1
400 .Host.pXStateR3 RTR3PTR_RES 1
401 alignb 8
402 .Host.xcr0 resq 1
403 .Host.fXStateMask resq 1
404
405 ;
406 ; Hypervisor Context (same as .Guest above).
407 ;
408 alignb 64
409 .Hyper resq 0
410 .Hyper.eax resq 1
411 .Hyper.ecx resq 1
412 .Hyper.edx resq 1
413 .Hyper.ebx resq 1
414 .Hyper.esp resq 1
415 .Hyper.ebp resq 1
416 .Hyper.esi resq 1
417 .Hyper.edi resq 1
418 .Hyper.r8 resq 1
419 .Hyper.r9 resq 1
420 .Hyper.r10 resq 1
421 .Hyper.r11 resq 1
422 .Hyper.r12 resq 1
423 .Hyper.r13 resq 1
424 .Hyper.r14 resq 1
425 .Hyper.r15 resq 1
426 .Hyper.es.Sel resw 1
427 .Hyper.es.PaddingSel resw 1
428 .Hyper.es.ValidSel resw 1
429 .Hyper.es.fFlags resw 1
430 .Hyper.es.u64Base resq 1
431 .Hyper.es.u32Limit resd 1
432 .Hyper.es.Attr resd 1
433 .Hyper.cs.Sel resw 1
434 .Hyper.cs.PaddingSel resw 1
435 .Hyper.cs.ValidSel resw 1
436 .Hyper.cs.fFlags resw 1
437 .Hyper.cs.u64Base resq 1
438 .Hyper.cs.u32Limit resd 1
439 .Hyper.cs.Attr resd 1
440 .Hyper.ss.Sel resw 1
441 .Hyper.ss.PaddingSel resw 1
442 .Hyper.ss.ValidSel resw 1
443 .Hyper.ss.fFlags resw 1
444 .Hyper.ss.u64Base resq 1
445 .Hyper.ss.u32Limit resd 1
446 .Hyper.ss.Attr resd 1
447 .Hyper.ds.Sel resw 1
448 .Hyper.ds.PaddingSel resw 1
449 .Hyper.ds.ValidSel resw 1
450 .Hyper.ds.fFlags resw 1
451 .Hyper.ds.u64Base resq 1
452 .Hyper.ds.u32Limit resd 1
453 .Hyper.ds.Attr resd 1
454 .Hyper.fs.Sel resw 1
455 .Hyper.fs.PaddingSel resw 1
456 .Hyper.fs.ValidSel resw 1
457 .Hyper.fs.fFlags resw 1
458 .Hyper.fs.u64Base resq 1
459 .Hyper.fs.u32Limit resd 1
460 .Hyper.fs.Attr resd 1
461 .Hyper.gs.Sel resw 1
462 .Hyper.gs.PaddingSel resw 1
463 .Hyper.gs.ValidSel resw 1
464 .Hyper.gs.fFlags resw 1
465 .Hyper.gs.u64Base resq 1
466 .Hyper.gs.u32Limit resd 1
467 .Hyper.gs.Attr resd 1
468 .Hyper.eip resq 1
469 .Hyper.eflags resq 1
470 .Hyper.cr0 resq 1
471 .Hyper.cr2 resq 1
472 .Hyper.cr3 resq 1
473 .Hyper.cr4 resq 1
474 .Hyper.dr resq 8
475 .Hyper.gdtrPadding resw 3
476 .Hyper.gdtr resw 0
477 .Hyper.gdtr.cbGdt resw 1
478 .Hyper.gdtr.pGdt resq 1
479 .Hyper.idtrPadding resw 3
480 .Hyper.idtr resw 0
481 .Hyper.idtr.cbIdt resw 1
482 .Hyper.idtr.pIdt resq 1
483 .Hyper.ldtr.Sel resw 1
484 .Hyper.ldtr.PaddingSel resw 1
485 .Hyper.ldtr.ValidSel resw 1
486 .Hyper.ldtr.fFlags resw 1
487 .Hyper.ldtr.u64Base resq 1
488 .Hyper.ldtr.u32Limit resd 1
489 .Hyper.ldtr.Attr resd 1
490 .Hyper.tr.Sel resw 1
491 .Hyper.tr.PaddingSel resw 1
492 .Hyper.tr.ValidSel resw 1
493 .Hyper.tr.fFlags resw 1
494 .Hyper.tr.u64Base resq 1
495 .Hyper.tr.u32Limit resd 1
496 .Hyper.tr.Attr resd 1
497 .Hyper.SysEnter.cs resb 8
498 .Hyper.SysEnter.eip resb 8
499 .Hyper.SysEnter.esp resb 8
500 .Hyper.msrEFER resb 8
501 .Hyper.msrSTAR resb 8
502 .Hyper.msrPAT resb 8
503 .Hyper.msrLSTAR resb 8
504 .Hyper.msrCSTAR resb 8
505 .Hyper.msrSFMASK resb 8
506 .Hyper.msrKERNELGSBASE resb 8
507 .Hyper.uMsrPadding0 resb 8
508 .Hyper.aXcr resq 2
509 .Hyper.fXStateMask resq 1
510 .Hyper.pXStateR0 RTR0PTR_RES 1
511 .Hyper.pXStateR3 RTR3PTR_RES 1
512 .Hyper.pXStateRC RTRCPTR_RES 1
513 .Hyper.aoffXState resw 64
514%if HC_ARCH_BITS == 64
515 .Hyper.abPadding resb 4
516%else
517 .Hyper.abPadding resb 12
518%endif
519 .Hyper.hwvirt.svm.uMsrHSavePa resq 1
520 .Hyper.hwvirt.svm.GCPhysVmcb resq 1
521 .Hyper.hwvirt.svm.pVmcbR0 RTR0PTR_RES 1
522 .Hyper.hwvirt.svm.pVmcbR3 RTR3PTR_RES 1
523%if HC_ARCH_BITS == 32
524 .Hyper.hwvirt.svm.abPadding0 resb 8
525%endif
526 .Hyper.hwvirt.svm.HostState resb 184
527 .Hyper.hwvirt.svm.fGif resb 1
528 .Hyper.hwvirt.svm.u8Padding0 resb 1
529 .Hyper.hwvirt.svm.cPauseFilter resw 1
530 .Hyper.hwvirt.svm.cPauseFilterThreshold resw 1
531 .Hyper.hwvirt.svm.fInterceptEvents resb 1
532 .Hyper.hwvirt.svm.u8Padding1 resb 1
533 .Hyper.hwvirt.svm.pvMsrBitmapR0 RTR0PTR_RES 1
534 .Hyper.hwvirt.svm.pvMsrBitmapR3 RTR3PTR_RES 1
535 .Hyper.hwvirt.svm.pvIoBitmapR0 RTR0PTR_RES 1
536 .Hyper.hwvirt.svm.pvIoBitmapR3 RTR3PTR_RES 1
537 .Hyper.hwvirt.svm.HCPhysVmcb RTHCPHYS_RES 1
538%if HC_ARCH_BITS == 32
539 .Hyper.hwvirt.svm.abPadding2 resb 16
540%endif
541 .Hyper.hwvirt.fLocalForcedActions resd 1
542 alignb 64
543
544%ifdef VBOX_WITH_CRASHDUMP_MAGIC
545 .aMagic resb 56
546 .uMagic resq 1
547%endif
548endstruc
549
550
551;;
552; Converts the CPUM pointer to CPUMCPU
553; @param %1 register name
554%macro CPUMCPU_FROM_CPUM 1
555 add %1, dword [%1 + CPUM.offCPUMCPU0]
556%endmacro
557
558;;
559; Converts the CPUM pointer to CPUMCPU
560; @param %1 register name (CPUM)
561; @param %2 register name (CPUMCPU offset)
562%macro CPUMCPU_FROM_CPUM_WITH_OFFSET 2
563 add %1, %2
564%endmacro
565
566;;
567; Converts the CPUMCPU pointer to CPUM
568; @param %1 register name
569%macro CPUM_FROM_CPUMCPU 1
570 sub %1, dword [%1 + CPUMCPU.offCPUM]
571%endmacro
572
573;;
574; Converts the CPUMCPU pointer to CPUM
575; @param %1 register name (CPUM)
576; @param %2 register name (CPUMCPU offset)
577%macro CPUM_FROM_CPUMCPU_WITH_OFFSET 2
578 sub %1, %2
579%endmacro
580
581
582
583%if 0 ; Currently not used anywhere.
584;;
585; Macro for FXSAVE/FXRSTOR leaky behaviour on AMD CPUs, see cpumR3CheckLeakyFpu().
586;
587; Cleans the FPU state, if necessary, before restoring the FPU.
588;
589; This macro ASSUMES CR0.TS is not set!
590;
591; @param xDX Pointer to CPUMCPU.
592; @uses xAX, EFLAGS
593;
594; Changes here should also be reflected in CPUMRCA.asm's copy!
595;
596%macro CLEANFPU 0
597 test dword [xDX + CPUMCPU.fUseFlags], CPUM_USE_FFXSR_LEAKY
598 jz .nothing_to_clean
599
600 xor eax, eax
601 fnstsw ax ; FSW -> AX.
602 test eax, RT_BIT(7) ; If FSW.ES (bit 7) is set, clear it to not cause FPU exceptions
603 ; while clearing & loading the FPU bits in 'clean_fpu' below.
604 jz .clean_fpu
605 fnclex
606
607.clean_fpu:
608 ffree st7 ; Clear FPU stack register(7)'s tag entry to prevent overflow if a wraparound occurs.
609 ; for the upcoming push (load)
610 fild dword [g_r32_Zero xWrtRIP] ; Explicit FPU load to overwrite FIP, FOP, FDP registers in the FPU.
611.nothing_to_clean:
612%endmacro
613%endif ; Unused.
614
615
616;;
617; Makes sure we don't trap (#NM) accessing the FPU.
618;
619; In ring-0 this is a bit of work since we may have try convince the host kernel
620; to do the work for us, also, we must report any CR0 changes back to HMR0VMX
621; via the VINF_CPUM_HOST_CR0_MODIFIED status code.
622;
623; If we end up clearing CR0.TS/EM ourselves in ring-0, we'll save the original
624; value in CPUMCPU.Host.cr0Fpu. If we don't, we'll store zero there. (See also
625; CPUMRZ_RESTORE_CR0_IF_TS_OR_EM_SET.)
626;
627; In raw-mode we will always have to clear TS and it will be recalculated
628; elsewhere and thus needs no saving.
629;
630; @param %1 Register to return the return status code in.
631; @param %2 Temporary scratch register.
632; @param %3 Ring-0 only, register pointing to the CPUMCPU structure
633; of the EMT we're on.
634; @uses EFLAGS, CR0, %1, %2
635;
636%macro CPUMRZ_TOUCH_FPU_CLEAR_CR0_FPU_TRAPS_SET_RC 3
637 %ifdef IN_RC
638 ;
639 ; raw-mode - always clear it. We won't be here otherwise.
640 ;
641 mov %2, cr0
642 and %2, ~(X86_CR0_TS | X86_CR0_EM)
643 mov cr0, %2
644
645 %else
646 ;
647 ; ring-0 - slightly complicated.
648 ;
649 xor %1, %1 ; 0 / VINF_SUCCESS. Wishing for no CR0 changes.
650 mov [%3 + CPUMCPU.Host.cr0Fpu], %1
651
652 mov %2, cr0
653 test %2, X86_CR0_TS | X86_CR0_EM ; Make sure its safe to access the FPU state.
654 jz %%no_cr0_change
655
656 %ifdef VMM_R0_TOUCH_FPU
657 ; Touch the state and check that the kernel updated CR0 for us.
658 movdqa xmm0, xmm0
659 mov %2, cr0
660 test %2, X86_CR0_TS | X86_CR0_EM
661 jz %%cr0_changed
662 %endif
663
664 ; Save CR0 and clear them flags ourselves.
665 mov [%3 + CPUMCPU.Host.cr0Fpu], %2
666 and %2, ~(X86_CR0_TS | X86_CR0_EM)
667 mov cr0, %2
668 %endif ; IN_RING0
669
670%%cr0_changed:
671 mov %1, VINF_CPUM_HOST_CR0_MODIFIED
672%%no_cr0_change:
673%endmacro
674
675
676;;
677; Restore CR0 if CR0.TS or CR0.EM were non-zero in the original state.
678;
679; @param %1 The original state to restore (or zero).
680;
681%macro CPUMRZ_RESTORE_CR0_IF_TS_OR_EM_SET 1
682 test %1, X86_CR0_TS | X86_CR0_EM
683 jz %%skip_cr0_restore
684 mov cr0, %1
685%%skip_cr0_restore:
686%endmacro
687
688
689;;
690; Saves the host state.
691;
692; @uses rax, rdx
693; @param pCpumCpu Define for the register containing the CPUMCPU pointer.
694; @param pXState Define for the register containing the extended state pointer.
695;
696%macro CPUMR0_SAVE_HOST 0
697 ;
698 ; Load a couple of registers we'll use later in all branches.
699 ;
700 %ifdef IN_RING0
701 mov pXState, [pCpumCpu + CPUMCPU.Host.pXStateR0]
702 %elifdef IN_RC
703 mov pXState, [pCpumCpu + CPUMCPU.Host.pXStateRC]
704 %else
705 %error "Unsupported context!"
706 %endif
707 mov eax, [pCpumCpu + CPUMCPU.Host.fXStateMask]
708
709 ;
710 ; XSAVE or FXSAVE?
711 ;
712 or eax, eax
713 jz %%host_fxsave
714
715 ; XSAVE
716 mov edx, [pCpumCpu + CPUMCPU.Host.fXStateMask + 4]
717 %ifdef RT_ARCH_AMD64
718 o64 xsave [pXState]
719 %else
720 xsave [pXState]
721 %endif
722 jmp %%host_done
723
724 ; FXSAVE
725%%host_fxsave:
726 %ifdef RT_ARCH_AMD64
727 o64 fxsave [pXState] ; Use explicit REX prefix. See @bugref{6398}.
728 %else
729 fxsave [pXState]
730 %endif
731
732%%host_done:
733%endmacro ; CPUMR0_SAVE_HOST
734
735
736;;
737; Loads the host state.
738;
739; @uses rax, rdx
740; @param pCpumCpu Define for the register containing the CPUMCPU pointer.
741; @param pXState Define for the register containing the extended state pointer.
742;
743%macro CPUMR0_LOAD_HOST 0
744 ;
745 ; Load a couple of registers we'll use later in all branches.
746 ;
747 %ifdef IN_RING0
748 mov pXState, [pCpumCpu + CPUMCPU.Host.pXStateR0]
749 %elifdef IN_RC
750 mov pXState, [pCpumCpu + CPUMCPU.Host.pXStateRC]
751 %else
752 %error "Unsupported context!"
753 %endif
754 mov eax, [pCpumCpu + CPUMCPU.Host.fXStateMask]
755
756 ;
757 ; XRSTOR or FXRSTOR?
758 ;
759 or eax, eax
760 jz %%host_fxrstor
761
762 ; XRSTOR
763 mov edx, [pCpumCpu + CPUMCPU.Host.fXStateMask + 4]
764 %ifdef RT_ARCH_AMD64
765 o64 xrstor [pXState]
766 %else
767 xrstor [pXState]
768 %endif
769 jmp %%host_done
770
771 ; FXRSTOR
772%%host_fxrstor:
773 %ifdef RT_ARCH_AMD64
774 o64 fxrstor [pXState] ; Use explicit REX prefix. See @bugref{6398}.
775 %else
776 fxrstor [pXState]
777 %endif
778
779%%host_done:
780%endmacro ; CPUMR0_LOAD_HOST
781
782
783
784;; Macro for XSAVE/FXSAVE for the guest FPU but tries to figure out whether to
785; save the 32-bit FPU state or 64-bit FPU state.
786;
787; @param %1 Pointer to CPUMCPU.
788; @param %2 Pointer to XState.
789; @param %3 Force AMD64
790; @param %4 The instruction to use (xsave or fxsave)
791; @uses xAX, xDX, EFLAGS, 20h of stack.
792;
793%macro SAVE_32_OR_64_FPU 4
794%if CPUM_IS_AMD64 || %3
795 ; Save the guest FPU (32-bit or 64-bit), preserves existing broken state. See @bugref{7138}.
796 test dword [pCpumCpu + CPUMCPU.fUseFlags], CPUM_USE_SUPPORTS_LONGMODE
797 jnz short %%save_long_mode_guest
798%endif
799 %4 [pXState]
800%if CPUM_IS_AMD64 || %3
801 jmp %%save_done_32bit_cs_ds
802
803%%save_long_mode_guest:
804 o64 %4 [pXState]
805
806 xor edx, edx
807 cmp dword [pXState + X86FXSTATE.FPUCS], 0
808 jne short %%save_done
809
810 sub rsp, 20h ; Only need 1ch bytes but keep stack aligned otherwise we #GP(0).
811 fnstenv [rsp]
812 movzx eax, word [rsp + 10h]
813 mov [pXState + X86FXSTATE.FPUCS], eax
814 movzx eax, word [rsp + 18h]
815 add rsp, 20h
816 mov [pXState + X86FXSTATE.FPUDS], eax
817%endif
818%%save_done_32bit_cs_ds:
819 mov edx, X86_FXSTATE_RSVD_32BIT_MAGIC
820%%save_done:
821 mov dword [pXState + X86_OFF_FXSTATE_RSVD], edx
822%endmacro ; SAVE_32_OR_64_FPU
823
824
825;;
826; Save the guest state.
827;
828; @uses rax, rdx
829; @param pCpumCpu Define for the register containing the CPUMCPU pointer.
830; @param pXState Define for the register containing the extended state pointer.
831;
832%macro CPUMR0_SAVE_GUEST 0
833 ;
834 ; Load a couple of registers we'll use later in all branches.
835 ;
836 %ifdef IN_RING0
837 mov pXState, [pCpumCpu + CPUMCPU.Guest.pXStateR0]
838 %elifdef IN_RC
839 mov pXState, [pCpumCpu + CPUMCPU.Guest.pXStateRC]
840 %else
841 %error "Unsupported context!"
842 %endif
843 mov eax, [pCpumCpu + CPUMCPU.Guest.fXStateMask]
844
845 ;
846 ; XSAVE or FXSAVE?
847 ;
848 or eax, eax
849 jz %%guest_fxsave
850
851 ; XSAVE
852 mov edx, [pCpumCpu + CPUMCPU.Guest.fXStateMask + 4]
853 %ifdef VBOX_WITH_KERNEL_USING_XMM
854 and eax, ~CPUM_VOLATILE_XSAVE_GUEST_COMPONENTS ; Already saved in HMR0A.asm.
855 %endif
856 SAVE_32_OR_64_FPU pCpumCpu, pXState, 0, xsave
857 jmp %%guest_done
858
859 ; FXSAVE
860%%guest_fxsave:
861 SAVE_32_OR_64_FPU pCpumCpu, pXState, 0, fxsave
862
863%%guest_done:
864%endmacro ; CPUMR0_SAVE_GUEST
865
866
867;;
868; Wrapper for selecting 32-bit or 64-bit XRSTOR/FXRSTOR according to what SAVE_32_OR_64_FPU did.
869;
870; @param %1 Pointer to CPUMCPU.
871; @param %2 Pointer to XState.
872; @param %3 Force AMD64.
873; @param %4 The instruction to use (xrstor or fxrstor).
874; @uses xAX, xDX, EFLAGS
875;
876%macro RESTORE_32_OR_64_FPU 4
877%if CPUM_IS_AMD64 || %3
878 ; Restore the guest FPU (32-bit or 64-bit), preserves existing broken state. See @bugref{7138}.
879 test dword [pCpumCpu + CPUMCPU.fUseFlags], CPUM_USE_SUPPORTS_LONGMODE
880 jz %%restore_32bit_fpu
881 cmp dword [pXState + X86_OFF_FXSTATE_RSVD], X86_FXSTATE_RSVD_32BIT_MAGIC
882 jne short %%restore_64bit_fpu
883%%restore_32bit_fpu:
884%endif
885 %4 [pXState]
886%if CPUM_IS_AMD64 || %3
887 ; TODO: Restore XMM8-XMM15!
888 jmp short %%restore_fpu_done
889%%restore_64bit_fpu:
890 o64 %4 [pXState]
891%%restore_fpu_done:
892%endif
893%endmacro ; RESTORE_32_OR_64_FPU
894
895
896;;
897; Loads the guest state.
898;
899; @uses rax, rdx
900; @param pCpumCpu Define for the register containing the CPUMCPU pointer.
901; @param pXState Define for the register containing the extended state pointer.
902;
903%macro CPUMR0_LOAD_GUEST 0
904 ;
905 ; Load a couple of registers we'll use later in all branches.
906 ;
907 %ifdef IN_RING0
908 mov pXState, [pCpumCpu + CPUMCPU.Guest.pXStateR0]
909 %elifdef IN_RC
910 mov pXState, [pCpumCpu + CPUMCPU.Guest.pXStateRC]
911 %else
912 %error "Unsupported context!"
913 %endif
914 mov eax, [pCpumCpu + CPUMCPU.Guest.fXStateMask]
915
916 ;
917 ; XRSTOR or FXRSTOR?
918 ;
919 or eax, eax
920 jz %%guest_fxrstor
921
922 ; XRSTOR
923 mov edx, [pCpumCpu + CPUMCPU.Guest.fXStateMask + 4]
924 %ifdef VBOX_WITH_KERNEL_USING_XMM
925 and eax, ~CPUM_VOLATILE_XSAVE_GUEST_COMPONENTS ; Will be loaded by HMR0A.asm.
926 %endif
927 RESTORE_32_OR_64_FPU pCpumCpu, pXState, 0, xrstor
928 jmp %%guest_done
929
930 ; FXRSTOR
931%%guest_fxrstor:
932 RESTORE_32_OR_64_FPU pCpumCpu, pXState, 0, fxrstor
933
934%%guest_done:
935%endmacro ; CPUMR0_LOAD_GUEST
936
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