CPUMInternal.mac@ 72915

Last change on this file since 72915 was 72643, checked in by vboxsync, 6 years ago
VMM: Make SVM R0 code use CPUMCTX_EXTRN_xxx flags and cleanups. bugref:9193
Property svn:eol-style set to `native` Property svn:keywords set to `Id Revision`
File size: 30.3 KB

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1	; $Id: CPUMInternal.mac 72643 2018-06-21 16:02:03Z vboxsync $
2	;; @file
3	; CPUM - Internal header file (asm).
4	;
5
6	;
7	; Copyright (C) 2006-2017 Oracle Corporation
8	;
9	; This file is part of VirtualBox Open Source Edition (OSE), as
10	; available from http://www.virtualbox.org. This file is free software;
11	; you can redistribute it and/or modify it under the terms of the GNU
12	; General Public License (GPL) as published by the Free Software
13	; Foundation, in version 2 as it comes in the "COPYING" file of the
14	; VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	; hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	;
17
18	%include "VBox/asmdefs.mac"
19	%include "VBox/vmm/cpum.mac"
20
21	;; Check sanity.
22	%ifdef VBOX_WITH_KERNEL_USING_XMM
23	%ifndef IN_RING0
24	%error "What? We've got code assuming VBOX_WITH_KERNEL_USING_XMM is only defined in ring-0!"
25	%endif
26	%endif
27
28	;; For numeric expressions
29	%ifdef RT_ARCH_AMD64
30	%define CPUM_IS_AMD64 1
31	%else
32	%define CPUM_IS_AMD64 0
33	%endif
34
35
36	;;
37	; CPU info
38	struc CPUMINFO
39	.cMsrRanges resd 1 ; uint32_t
40	.fMsrMask resd 1 ; uint32_t
41	.fMxCsrMask resd 1 ; uint32_t
42	.cCpuIdLeaves resd 1 ; uint32_t
43	.iFirstExtCpuIdLeaf resd 1 ; uint32_t
44	.enmUnknownCpuIdMethod resd 1 ; CPUMUNKNOWNCPUID
45	.DefCpuId resb CPUMCPUID_size ; CPUMCPUID
46	.uScalableBusFreq resq 1 ; uint64_t
47	.paMsrRangesR0 RTR0PTR_RES 1 ; R0PTRTYPE(PCPUMMSRRANGE)
48	.paCpuIdLeavesR0 RTR0PTR_RES 1 ; R0PTRTYPE(PCPUMCPUIDLEAF)
49	.paMsrRangesR3 RTR3PTR_RES 1 ; R3PTRTYPE(PCPUMMSRRANGE)
50	.paCpuIdLeavesR3 RTR3PTR_RES 1 ; R3PTRTYPE(PCPUMCPUIDLEAF)
51	.paMsrRangesRC RTRCPTR_RES 1 ; RCPTRTYPE(PCPUMMSRRANGE)
52	.paCpuIdLeavesRC RTRCPTR_RES 1 ; RCPTRTYPE(PCPUMCPUIDLEAF)
53	endstruc
54
55
56	%define CPUM_USED_FPU_HOST RT_BIT(0)
57	%define CPUM_USED_FPU_GUEST RT_BIT(10)
58	%define CPUM_USED_FPU_SINCE_REM RT_BIT(1)
59	%define CPUM_USED_MANUAL_XMM_RESTORE RT_BIT(2)
60	%define CPUM_USE_SYSENTER RT_BIT(3)
61	%define CPUM_USE_SYSCALL RT_BIT(4)
62	%define CPUM_USE_DEBUG_REGS_HOST RT_BIT(5)
63	%define CPUM_USED_DEBUG_REGS_HOST RT_BIT(6)
64	%define CPUM_USE_DEBUG_REGS_HYPER RT_BIT(7)
65	%define CPUM_USED_DEBUG_REGS_HYPER RT_BIT(8)
66	%define CPUM_USED_DEBUG_REGS_GUEST RT_BIT(9)
67	%define CPUM_SYNC_FPU_STATE RT_BIT(16)
68	%define CPUM_SYNC_DEBUG_REGS_GUEST RT_BIT(17)
69	%define CPUM_SYNC_DEBUG_REGS_HYPER RT_BIT(18)
70	%define CPUM_USE_FFXSR_LEAKY RT_BIT(19)
71	%define CPUM_USE_SUPPORTS_LONGMODE RT_BIT(20)
72
73	%define CPUM_HANDLER_DS 1
74	%define CPUM_HANDLER_ES 2
75	%define CPUM_HANDLER_FS 3
76	%define CPUM_HANDLER_GS 4
77	%define CPUM_HANDLER_IRET 5
78	%define CPUM_HANDLER_TYPEMASK 0ffh
79	%define CPUM_HANDLER_CTXCORE_IN_EBP RT_BIT(31)
80
81
82	struc CPUM
83	;...
84	.offCPUMCPU0 resd 1
85	.fHostUseFlags resd 1
86
87	; CR4 masks
88	.CR4.AndMask resd 1
89	.CR4.OrMask resd 1
90	; entered rawmode?
91	.u8PortableCpuIdLevel resb 1
92	.fPendingRestore resb 1
93
94	alignb 8
95	.fXStateGuestMask resq 1
96	.fXStateHostMask resq 1
97
98	alignb 64
99	.HostFeatures resb 32
100	.GuestFeatures resb 32
101	.GuestInfo resb RTHCPTR_CB4 + RTRCPTR_CB2 + 4*12
102
103	; Patch manager saved state compatability CPUID leaf arrays
104	.aGuestCpuIdPatmStd resb 16*6
105	.aGuestCpuIdPatmExt resb 16*10
106	.aGuestCpuIdPatmCentaur resb 16*4
107
108	alignb 8
109	.cMsrWrites resq 1
110	.cMsrWritesToIgnoredBits resq 1
111	.cMsrWritesRaiseGp resq 1
112	.cMsrWritesUnknown resq 1
113	.cMsrReads resq 1
114	.cMsrReadsRaiseGp resq 1
115	.cMsrReadsUnknown resq 1
116	endstruc
117
118	struc CPUMCPU
119	;
120	; Guest context state
121	; (Identical to the .Hyper chunk below and to CPUMCTX in cpum.mac.)
122	;
123	.Guest resq 0
124	.Guest.eax resq 1
125	.Guest.ecx resq 1
126	.Guest.edx resq 1
127	.Guest.ebx resq 1
128	.Guest.esp resq 1
129	.Guest.ebp resq 1
130	.Guest.esi resq 1
131	.Guest.edi resq 1
132	.Guest.r8 resq 1
133	.Guest.r9 resq 1
134	.Guest.r10 resq 1
135	.Guest.r11 resq 1
136	.Guest.r12 resq 1
137	.Guest.r13 resq 1
138	.Guest.r14 resq 1
139	.Guest.r15 resq 1
140	.Guest.es.Sel resw 1
141	.Guest.es.PaddingSel resw 1
142	.Guest.es.ValidSel resw 1
143	.Guest.es.fFlags resw 1
144	.Guest.es.u64Base resq 1
145	.Guest.es.u32Limit resd 1
146	.Guest.es.Attr resd 1
147	.Guest.cs.Sel resw 1
148	.Guest.cs.PaddingSel resw 1
149	.Guest.cs.ValidSel resw 1
150	.Guest.cs.fFlags resw 1
151	.Guest.cs.u64Base resq 1
152	.Guest.cs.u32Limit resd 1
153	.Guest.cs.Attr resd 1
154	.Guest.ss.Sel resw 1
155	.Guest.ss.PaddingSel resw 1
156	.Guest.ss.ValidSel resw 1
157	.Guest.ss.fFlags resw 1
158	.Guest.ss.u64Base resq 1
159	.Guest.ss.u32Limit resd 1
160	.Guest.ss.Attr resd 1
161	.Guest.ds.Sel resw 1
162	.Guest.ds.PaddingSel resw 1
163	.Guest.ds.ValidSel resw 1
164	.Guest.ds.fFlags resw 1
165	.Guest.ds.u64Base resq 1
166	.Guest.ds.u32Limit resd 1
167	.Guest.ds.Attr resd 1
168	.Guest.fs.Sel resw 1
169	.Guest.fs.PaddingSel resw 1
170	.Guest.fs.ValidSel resw 1
171	.Guest.fs.fFlags resw 1
172	.Guest.fs.u64Base resq 1
173	.Guest.fs.u32Limit resd 1
174	.Guest.fs.Attr resd 1
175	.Guest.gs.Sel resw 1
176	.Guest.gs.PaddingSel resw 1
177	.Guest.gs.ValidSel resw 1
178	.Guest.gs.fFlags resw 1
179	.Guest.gs.u64Base resq 1
180	.Guest.gs.u32Limit resd 1
181	.Guest.gs.Attr resd 1
182	.Guest.eip resq 1
183	.Guest.eflags resq 1
184	.Guest.cr0 resq 1
185	.Guest.cr2 resq 1
186	.Guest.cr3 resq 1
187	.Guest.cr4 resq 1
188	.Guest.dr resq 8
189	.Guest.gdtrPadding resw 3
190	.Guest.gdtr resw 0
191	.Guest.gdtr.cbGdt resw 1
192	.Guest.gdtr.pGdt resq 1
193	.Guest.idtrPadding resw 3
194	.Guest.idtr resw 0
195	.Guest.idtr.cbIdt resw 1
196	.Guest.idtr.pIdt resq 1
197	.Guest.ldtr.Sel resw 1
198	.Guest.ldtr.PaddingSel resw 1
199	.Guest.ldtr.ValidSel resw 1
200	.Guest.ldtr.fFlags resw 1
201	.Guest.ldtr.u64Base resq 1
202	.Guest.ldtr.u32Limit resd 1
203	.Guest.ldtr.Attr resd 1
204	.Guest.tr.Sel resw 1
205	.Guest.tr.PaddingSel resw 1
206	.Guest.tr.ValidSel resw 1
207	.Guest.tr.fFlags resw 1
208	.Guest.tr.u64Base resq 1
209	.Guest.tr.u32Limit resd 1
210	.Guest.tr.Attr resd 1
211	.Guest.SysEnter.cs resb 8
212	.Guest.SysEnter.eip resb 8
213	.Guest.SysEnter.esp resb 8
214	.Guest.msrEFER resb 8
215	.Guest.msrSTAR resb 8
216	.Guest.msrPAT resb 8
217	.Guest.msrLSTAR resb 8
218	.Guest.msrCSTAR resb 8
219	.Guest.msrSFMASK resb 8
220	.Guest.msrKERNELGSBASE resb 8
221	.Guest.uMsrPadding0 resb 8
222	alignb 8
223	.Guest.aXcr resq 2
224	.Guest.fXStateMask resq 1
225	.Guest.pXStateR0 RTR0PTR_RES 1
226	alignb 8
227	.Guest.pXStateR3 RTR3PTR_RES 1
228	alignb 8
229	.Guest.pXStateRC RTRCPTR_RES 1
230	.Guest.aoffXState resw 64
231	.Guest.fWorldSwitcher resd 1
232	.Guest.fExtrn resq 1
233	alignb 8
234	.Guest.hwvirt.svm.uMsrHSavePa resq 1
235	.Guest.hwvirt.svm.GCPhysVmcb resq 1
236	.Guest.hwvirt.svm.pVmcbR0 RTR0PTR_RES 1
237	alignb 8
238	.Guest.hwvirt.svm.pVmcbR3 RTR3PTR_RES 1
239	alignb 8
240	.Guest.hwvirt.svm.HostState resb 184
241	.Guest.hwvirt.svm.uPrevPauseTick resq 1
242	.Guest.hwvirt.svm.cPauseFilter resw 1
243	.Guest.hwvirt.svm.cPauseFilterThreshold resw 1
244	.Guest.hwvirt.svm.fInterceptEvents resb 1
245	alignb 8
246	.Guest.hwvirt.svm.pvMsrBitmapR0 RTR0PTR_RES 1
247	alignb 8
248	.Guest.hwvirt.svm.pvMsrBitmapR3 RTR3PTR_RES 1
249	alignb 8
250	.Guest.hwvirt.svm.pvIoBitmapR0 RTR0PTR_RES 1
251	alignb 8
252	.Guest.hwvirt.svm.pvIoBitmapR3 RTR3PTR_RES 1
253	alignb 8
254	.Guest.hwvirt.svm.HCPhysVmcb RTHCPHYS_RES 1
255	.Guest.hwvirt.fLocalForcedActions resd 1
256	.Guest.hwvirt.fGif resb 1
257	alignb 64
258
259	.GuestMsrs resq 0
260	.GuestMsrs.au64 resq 64
261
262	;
263	; Other stuff.
264	;
265	.fUseFlags resd 1
266	.fChanged resd 1
267	.offCPUM resd 1
268	.u32RetCode resd 1
269
270	%ifdef VBOX_WITH_VMMR0_DISABLE_LAPIC_NMI
271	.pvApicBase RTR0PTR_RES 1
272	.fApicDisVectors resd 1
273	.fX2Apic resb 1
274	%else
275	.abPadding3 resb (RTR0PTR_CB + 4 + 1)
276	%endif
277
278	.fRawEntered resb 1
279	.fRemEntered resb 1
280	.fCpuIdApicFeatureVisible resb 1
281
282	.abPadding2 resb (64 - 16 - RTR0PTR_CB - 4 - 1 - 3)
283
284	;
285	; Host context state
286	;
287	alignb 64
288	.Host resb 0
289	%if HC_ARCH_BITS == 64
290	;.Host.rax resq 1 - scratch
291	.Host.rbx resq 1
292	;.Host.rcx resq 1 - scratch
293	;.Host.rdx resq 1 - scratch
294	.Host.rdi resq 1
295	.Host.rsi resq 1
296	.Host.rbp resq 1
297	.Host.rsp resq 1
298	;.Host.r8 resq 1 - scratch
299	;.Host.r9 resq 1 - scratch
300	.Host.r10 resq 1
301	.Host.r11 resq 1
302	.Host.r12 resq 1
303	.Host.r13 resq 1
304	.Host.r14 resq 1
305	.Host.r15 resq 1
306	;.Host.rip resd 1 - scratch
307	.Host.rflags resq 1
308	%endif
309	%if HC_ARCH_BITS == 32
310	;.Host.eax resd 1 - scratch
311	.Host.ebx resd 1
312	;.Host.edx resd 1 - scratch
313	;.Host.ecx resd 1 - scratch
314	.Host.edi resd 1
315	.Host.esi resd 1
316	.Host.ebp resd 1
317	.Host.eflags resd 1
318	;.Host.eip resd 1 - scratch
319	; lss pair!
320	.Host.esp resd 1
321	%endif
322	.Host.ss resw 1
323	.Host.ssPadding resw 1
324	.Host.gs resw 1
325	.Host.gsPadding resw 1
326	.Host.fs resw 1
327	.Host.fsPadding resw 1
328	.Host.es resw 1
329	.Host.esPadding resw 1
330	.Host.ds resw 1
331	.Host.dsPadding resw 1
332	.Host.cs resw 1
333	.Host.csPadding resw 1
334
335	%if HC_ARCH_BITS == 32
336	.Host.cr0 resd 1
337	;.Host.cr2 resd 1 - scratch
338	.Host.cr3 resd 1
339	.Host.cr4 resd 1
340	.Host.cr0Fpu resd 1
341
342	.Host.dr0 resd 1
343	.Host.dr1 resd 1
344	.Host.dr2 resd 1
345	.Host.dr3 resd 1
346	.Host.dr6 resd 1
347	.Host.dr7 resd 1
348
349	.Host.gdtr resb 6 ; GDT limit + linear address
350	.Host.gdtrPadding resw 1
351	.Host.idtr resb 6 ; IDT limit + linear address
352	.Host.idtrPadding resw 1
353	.Host.ldtr resw 1
354	.Host.ldtrPadding resw 1
355	.Host.tr resw 1
356	.Host.trPadding resw 1
357
358	alignb 8
359	.Host.SysEnter.cs resq 1
360	.Host.SysEnter.eip resq 1
361	.Host.SysEnter.esp resq 1
362	.Host.efer resq 1
363	.Host.auPadding resb (20)
364
365	%else ; 64-bit
366
367	.Host.cr0Fpu:
368	.Host.cr0 resq 1
369	;.Host.cr2 resq 1 - scratch
370	.Host.cr3 resq 1
371	.Host.cr4 resq 1
372	.Host.cr8 resq 1
373
374	.Host.dr0 resq 1
375	.Host.dr1 resq 1
376	.Host.dr2 resq 1
377	.Host.dr3 resq 1
378	.Host.dr6 resq 1
379	.Host.dr7 resq 1
380
381	.Host.gdtr resb 10 ; GDT limit + linear address
382	.Host.gdtrPadding resw 1
383	.Host.idtr resb 10 ; IDT limit + linear address
384	.Host.idtrPadding resw 1
385	.Host.ldtr resw 1
386	.Host.ldtrPadding resw 1
387	.Host.tr resw 1
388	.Host.trPadding resw 1
389
390	.Host.SysEnter.cs resq 1
391	.Host.SysEnter.eip resq 1
392	.Host.SysEnter.esp resq 1
393	.Host.FSbase resq 1
394	.Host.GSbase resq 1
395	.Host.efer resq 1
396	.Host.auPadding resb 4
397	%endif ; 64-bit
398	.Host.pXStateRC RTRCPTR_RES 1
399	alignb RTR0PTR_CB
400	.Host.pXStateR0 RTR0PTR_RES 1
401	.Host.pXStateR3 RTR3PTR_RES 1
402	alignb 8
403	.Host.xcr0 resq 1
404	.Host.fXStateMask resq 1
405
406	;
407	; Hypervisor Context (same as .Guest above).
408	;
409	alignb 64
410	.Hyper resq 0
411	.Hyper.eax resq 1
412	.Hyper.ecx resq 1
413	.Hyper.edx resq 1
414	.Hyper.ebx resq 1
415	.Hyper.esp resq 1
416	.Hyper.ebp resq 1
417	.Hyper.esi resq 1
418	.Hyper.edi resq 1
419	.Hyper.r8 resq 1
420	.Hyper.r9 resq 1
421	.Hyper.r10 resq 1
422	.Hyper.r11 resq 1
423	.Hyper.r12 resq 1
424	.Hyper.r13 resq 1
425	.Hyper.r14 resq 1
426	.Hyper.r15 resq 1
427	.Hyper.es.Sel resw 1
428	.Hyper.es.PaddingSel resw 1
429	.Hyper.es.ValidSel resw 1
430	.Hyper.es.fFlags resw 1
431	.Hyper.es.u64Base resq 1
432	.Hyper.es.u32Limit resd 1
433	.Hyper.es.Attr resd 1
434	.Hyper.cs.Sel resw 1
435	.Hyper.cs.PaddingSel resw 1
436	.Hyper.cs.ValidSel resw 1
437	.Hyper.cs.fFlags resw 1
438	.Hyper.cs.u64Base resq 1
439	.Hyper.cs.u32Limit resd 1
440	.Hyper.cs.Attr resd 1
441	.Hyper.ss.Sel resw 1
442	.Hyper.ss.PaddingSel resw 1
443	.Hyper.ss.ValidSel resw 1
444	.Hyper.ss.fFlags resw 1
445	.Hyper.ss.u64Base resq 1
446	.Hyper.ss.u32Limit resd 1
447	.Hyper.ss.Attr resd 1
448	.Hyper.ds.Sel resw 1
449	.Hyper.ds.PaddingSel resw 1
450	.Hyper.ds.ValidSel resw 1
451	.Hyper.ds.fFlags resw 1
452	.Hyper.ds.u64Base resq 1
453	.Hyper.ds.u32Limit resd 1
454	.Hyper.ds.Attr resd 1
455	.Hyper.fs.Sel resw 1
456	.Hyper.fs.PaddingSel resw 1
457	.Hyper.fs.ValidSel resw 1
458	.Hyper.fs.fFlags resw 1
459	.Hyper.fs.u64Base resq 1
460	.Hyper.fs.u32Limit resd 1
461	.Hyper.fs.Attr resd 1
462	.Hyper.gs.Sel resw 1
463	.Hyper.gs.PaddingSel resw 1
464	.Hyper.gs.ValidSel resw 1
465	.Hyper.gs.fFlags resw 1
466	.Hyper.gs.u64Base resq 1
467	.Hyper.gs.u32Limit resd 1
468	.Hyper.gs.Attr resd 1
469	.Hyper.eip resq 1
470	.Hyper.eflags resq 1
471	.Hyper.cr0 resq 1
472	.Hyper.cr2 resq 1
473	.Hyper.cr3 resq 1
474	.Hyper.cr4 resq 1
475	.Hyper.dr resq 8
476	.Hyper.gdtrPadding resw 3
477	.Hyper.gdtr resw 0
478	.Hyper.gdtr.cbGdt resw 1
479	.Hyper.gdtr.pGdt resq 1
480	.Hyper.idtrPadding resw 3
481	.Hyper.idtr resw 0
482	.Hyper.idtr.cbIdt resw 1
483	.Hyper.idtr.pIdt resq 1
484	.Hyper.ldtr.Sel resw 1
485	.Hyper.ldtr.PaddingSel resw 1
486	.Hyper.ldtr.ValidSel resw 1
487	.Hyper.ldtr.fFlags resw 1
488	.Hyper.ldtr.u64Base resq 1
489	.Hyper.ldtr.u32Limit resd 1
490	.Hyper.ldtr.Attr resd 1
491	.Hyper.tr.Sel resw 1
492	.Hyper.tr.PaddingSel resw 1
493	.Hyper.tr.ValidSel resw 1
494	.Hyper.tr.fFlags resw 1
495	.Hyper.tr.u64Base resq 1
496	.Hyper.tr.u32Limit resd 1
497	.Hyper.tr.Attr resd 1
498	.Hyper.SysEnter.cs resb 8
499	.Hyper.SysEnter.eip resb 8
500	.Hyper.SysEnter.esp resb 8
501	.Hyper.msrEFER resb 8
502	.Hyper.msrSTAR resb 8
503	.Hyper.msrPAT resb 8
504	.Hyper.msrLSTAR resb 8
505	.Hyper.msrCSTAR resb 8
506	.Hyper.msrSFMASK resb 8
507	.Hyper.msrKERNELGSBASE resb 8
508	.Hyper.uMsrPadding0 resb 8
509	alignb 8
510	.Hyper.aXcr resq 2
511	.Hyper.fXStateMask resq 1
512	.Hyper.pXStateR0 RTR0PTR_RES 1
513	alignb 8
514	.Hyper.pXStateR3 RTR3PTR_RES 1
515	alignb 8
516	.Hyper.pXStateRC RTRCPTR_RES 1
517	.Hyper.aoffXState resw 64
518	.Hyper.fWorldSwitcher resd 1
519	.Hyper.fExtrn resq 1
520	alignb 8
521	.Hyper.hwvirt.svm.uMsrHSavePa resq 1
522	.Hyper.hwvirt.svm.GCPhysVmcb resq 1
523	.Hyper.hwvirt.svm.pVmcbR0 RTR0PTR_RES 1
524	alignb 8
525	.Hyper.hwvirt.svm.pVmcbR3 RTR3PTR_RES 1
526	alignb 8
527	.Hyper.hwvirt.svm.HostState resb 184
528	.Hyper.hwvirt.svm.uPrevPauseTick resq 1
529	.Hyper.hwvirt.svm.cPauseFilter resw 1
530	.Hyper.hwvirt.svm.cPauseFilterThreshold resw 1
531	.Hyper.hwvirt.svm.fInterceptEvents resb 1
532	alignb 8
533	.Hyper.hwvirt.svm.pvMsrBitmapR0 RTR0PTR_RES 1
534	alignb 8
535	.Hyper.hwvirt.svm.pvMsrBitmapR3 RTR3PTR_RES 1
536	alignb 8
537	.Hyper.hwvirt.svm.pvIoBitmapR0 RTR0PTR_RES 1
538	alignb 8
539	.Hyper.hwvirt.svm.pvIoBitmapR3 RTR3PTR_RES 1
540	alignb 8
541	.Hyper.hwvirt.svm.HCPhysVmcb RTHCPHYS_RES 1
542	.Hyper.hwvirt.fLocalForcedActions resd 1
543	.Hyper.hwvirt.fGif resb 1
544	alignb 64
545
546	%ifdef VBOX_WITH_CRASHDUMP_MAGIC
547	.aMagic resb 56
548	.uMagic resq 1
549	%endif
550	endstruc
551
552
553	;;
554	; Converts the CPUM pointer to CPUMCPU
555	; @param %1 register name
556	%macro CPUMCPU_FROM_CPUM 1
557	add %1, dword [%1 + CPUM.offCPUMCPU0]
558	%endmacro
559
560	;;
561	; Converts the CPUM pointer to CPUMCPU
562	; @param %1 register name (CPUM)
563	; @param %2 register name (CPUMCPU offset)
564	%macro CPUMCPU_FROM_CPUM_WITH_OFFSET 2
565	add %1, %2
566	%endmacro
567
568	;;
569	; Converts the CPUMCPU pointer to CPUM
570	; @param %1 register name
571	%macro CPUM_FROM_CPUMCPU 1
572	sub %1, dword [%1 + CPUMCPU.offCPUM]
573	%endmacro
574
575	;;
576	; Converts the CPUMCPU pointer to CPUM
577	; @param %1 register name (CPUM)
578	; @param %2 register name (CPUMCPU offset)
579	%macro CPUM_FROM_CPUMCPU_WITH_OFFSET 2
580	sub %1, %2
581	%endmacro
582
583
584
585	%if 0 ; Currently not used anywhere.
586	;;
587	; Macro for FXSAVE/FXRSTOR leaky behaviour on AMD CPUs, see cpumR3CheckLeakyFpu().
588	;
589	; Cleans the FPU state, if necessary, before restoring the FPU.
590	;
591	; This macro ASSUMES CR0.TS is not set!
592	;
593	; @param xDX Pointer to CPUMCPU.
594	; @uses xAX, EFLAGS
595	;
596	; Changes here should also be reflected in CPUMRCA.asm's copy!
597	;
598	%macro CLEANFPU 0
599	test dword [xDX + CPUMCPU.fUseFlags], CPUM_USE_FFXSR_LEAKY
600	jz .nothing_to_clean
601
602	xor eax, eax
603	fnstsw ax ; FSW -> AX.
604	test eax, RT_BIT(7) ; If FSW.ES (bit 7) is set, clear it to not cause FPU exceptions
605	; while clearing & loading the FPU bits in 'clean_fpu' below.
606	jz .clean_fpu
607	fnclex
608
609	.clean_fpu:
610	ffree st7 ; Clear FPU stack register(7)'s tag entry to prevent overflow if a wraparound occurs.
611	; for the upcoming push (load)
612	fild dword [g_r32_Zero xWrtRIP] ; Explicit FPU load to overwrite FIP, FOP, FDP registers in the FPU.
613	.nothing_to_clean:
614	%endmacro
615	%endif ; Unused.
616
617
618	;;
619	; Makes sure we don't trap (#NM) accessing the FPU.
620	;
621	; In ring-0 this is a bit of work since we may have try convince the host kernel
622	; to do the work for us, also, we must report any CR0 changes back to HMR0VMX
623	; via the VINF_CPUM_HOST_CR0_MODIFIED status code.
624	;
625	; If we end up clearing CR0.TS/EM ourselves in ring-0, we'll save the original
626	; value in CPUMCPU.Host.cr0Fpu. If we don't, we'll store zero there. (See also
627	; CPUMRZ_RESTORE_CR0_IF_TS_OR_EM_SET.)
628	;
629	; In raw-mode we will always have to clear TS and it will be recalculated
630	; elsewhere and thus needs no saving.
631	;
632	; @param %1 Register to return the return status code in.
633	; @param %2 Temporary scratch register.
634	; @param %3 Ring-0 only, register pointing to the CPUMCPU structure
635	; of the EMT we're on.
636	; @uses EFLAGS, CR0, %1, %2
637	;
638	%macro CPUMRZ_TOUCH_FPU_CLEAR_CR0_FPU_TRAPS_SET_RC 3
639	%ifdef IN_RC
640	;
641	; raw-mode - always clear it. We won't be here otherwise.
642	;
643	mov %2, cr0
644	and %2, ~(X86_CR0_TS \| X86_CR0_EM)
645	mov cr0, %2
646
647	%else
648	;
649	; ring-0 - slightly complicated.
650	;
651	xor %1, %1 ; 0 / VINF_SUCCESS. Wishing for no CR0 changes.
652	mov [%3 + CPUMCPU.Host.cr0Fpu], %1
653
654	mov %2, cr0
655	test %2, X86_CR0_TS \| X86_CR0_EM ; Make sure its safe to access the FPU state.
656	jz %%no_cr0_change
657
658	%ifdef VMM_R0_TOUCH_FPU
659	; Touch the state and check that the kernel updated CR0 for us.
660	movdqa xmm0, xmm0
661	mov %2, cr0
662	test %2, X86_CR0_TS \| X86_CR0_EM
663	jz %%cr0_changed
664	%endif
665
666	; Save CR0 and clear them flags ourselves.
667	mov [%3 + CPUMCPU.Host.cr0Fpu], %2
668	and %2, ~(X86_CR0_TS \| X86_CR0_EM)
669	mov cr0, %2
670	%endif ; IN_RING0
671
672	%%cr0_changed:
673	mov %1, VINF_CPUM_HOST_CR0_MODIFIED
674	%%no_cr0_change:
675	%endmacro
676
677
678	;;
679	; Restore CR0 if CR0.TS or CR0.EM were non-zero in the original state.
680	;
681	; @param %1 The original state to restore (or zero).
682	;
683	%macro CPUMRZ_RESTORE_CR0_IF_TS_OR_EM_SET 1
684	test %1, X86_CR0_TS \| X86_CR0_EM
685	jz %%skip_cr0_restore
686	mov cr0, %1
687	%%skip_cr0_restore:
688	%endmacro
689
690
691	;;
692	; Saves the host state.
693	;
694	; @uses rax, rdx
695	; @param pCpumCpu Define for the register containing the CPUMCPU pointer.
696	; @param pXState Define for the register containing the extended state pointer.
697	;
698	%macro CPUMR0_SAVE_HOST 0
699	;
700	; Load a couple of registers we'll use later in all branches.
701	;
702	%ifdef IN_RING0
703	mov pXState, [pCpumCpu + CPUMCPU.Host.pXStateR0]
704	%elifdef IN_RC
705	mov pXState, [pCpumCpu + CPUMCPU.Host.pXStateRC]
706	%else
707	%error "Unsupported context!"
708	%endif
709	mov eax, [pCpumCpu + CPUMCPU.Host.fXStateMask]
710
711	;
712	; XSAVE or FXSAVE?
713	;
714	or eax, eax
715	jz %%host_fxsave
716
717	; XSAVE
718	mov edx, [pCpumCpu + CPUMCPU.Host.fXStateMask + 4]
719	%ifdef RT_ARCH_AMD64
720	o64 xsave [pXState]
721	%else
722	xsave [pXState]
723	%endif
724	jmp %%host_done
725
726	; FXSAVE
727	%%host_fxsave:
728	%ifdef RT_ARCH_AMD64
729	o64 fxsave [pXState] ; Use explicit REX prefix. See @bugref{6398}.
730	%else
731	fxsave [pXState]
732	%endif
733
734	%%host_done:
735	%endmacro ; CPUMR0_SAVE_HOST
736
737
738	;;
739	; Loads the host state.
740	;
741	; @uses rax, rdx
742	; @param pCpumCpu Define for the register containing the CPUMCPU pointer.
743	; @param pXState Define for the register containing the extended state pointer.
744	;
745	%macro CPUMR0_LOAD_HOST 0
746	;
747	; Load a couple of registers we'll use later in all branches.
748	;
749	%ifdef IN_RING0
750	mov pXState, [pCpumCpu + CPUMCPU.Host.pXStateR0]
751	%elifdef IN_RC
752	mov pXState, [pCpumCpu + CPUMCPU.Host.pXStateRC]
753	%else
754	%error "Unsupported context!"
755	%endif
756	mov eax, [pCpumCpu + CPUMCPU.Host.fXStateMask]
757
758	;
759	; XRSTOR or FXRSTOR?
760	;
761	or eax, eax
762	jz %%host_fxrstor
763
764	; XRSTOR
765	mov edx, [pCpumCpu + CPUMCPU.Host.fXStateMask + 4]
766	%ifdef RT_ARCH_AMD64
767	o64 xrstor [pXState]
768	%else
769	xrstor [pXState]
770	%endif
771	jmp %%host_done
772
773	; FXRSTOR
774	%%host_fxrstor:
775	%ifdef RT_ARCH_AMD64
776	o64 fxrstor [pXState] ; Use explicit REX prefix. See @bugref{6398}.
777	%else
778	fxrstor [pXState]
779	%endif
780
781	%%host_done:
782	%endmacro ; CPUMR0_LOAD_HOST
783
784
785
786	;; Macro for XSAVE/FXSAVE for the guest FPU but tries to figure out whether to
787	; save the 32-bit FPU state or 64-bit FPU state.
788	;
789	; @param %1 Pointer to CPUMCPU.
790	; @param %2 Pointer to XState.
791	; @param %3 Force AMD64
792	; @param %4 The instruction to use (xsave or fxsave)
793	; @uses xAX, xDX, EFLAGS, 20h of stack.
794	;
795	%macro SAVE_32_OR_64_FPU 4
796	%if CPUM_IS_AMD64 \|\| %3
797	; Save the guest FPU (32-bit or 64-bit), preserves existing broken state. See @bugref{7138}.
798	test dword [pCpumCpu + CPUMCPU.fUseFlags], CPUM_USE_SUPPORTS_LONGMODE
799	jnz short %%save_long_mode_guest
800	%endif
801	%4 [pXState]
802	%if CPUM_IS_AMD64 \|\| %3
803	jmp %%save_done_32bit_cs_ds
804
805	%%save_long_mode_guest:
806	o64 %4 [pXState]
807
808	xor edx, edx
809	cmp dword [pXState + X86FXSTATE.FPUCS], 0
810	jne short %%save_done
811
812	sub rsp, 20h ; Only need 1ch bytes but keep stack aligned otherwise we #GP(0).
813	fnstenv [rsp]
814	movzx eax, word [rsp + 10h]
815	mov [pXState + X86FXSTATE.FPUCS], eax
816	movzx eax, word [rsp + 18h]
817	add rsp, 20h
818	mov [pXState + X86FXSTATE.FPUDS], eax
819	%endif
820	%%save_done_32bit_cs_ds:
821	mov edx, X86_FXSTATE_RSVD_32BIT_MAGIC
822	%%save_done:
823	mov dword [pXState + X86_OFF_FXSTATE_RSVD], edx
824	%endmacro ; SAVE_32_OR_64_FPU
825
826
827	;;
828	; Save the guest state.
829	;
830	; @uses rax, rdx
831	; @param pCpumCpu Define for the register containing the CPUMCPU pointer.
832	; @param pXState Define for the register containing the extended state pointer.
833	;
834	%macro CPUMR0_SAVE_GUEST 0
835	;
836	; Load a couple of registers we'll use later in all branches.
837	;
838	%ifdef IN_RING0
839	mov pXState, [pCpumCpu + CPUMCPU.Guest.pXStateR0]
840	%elifdef IN_RC
841	mov pXState, [pCpumCpu + CPUMCPU.Guest.pXStateRC]
842	%else
843	%error "Unsupported context!"
844	%endif
845	mov eax, [pCpumCpu + CPUMCPU.Guest.fXStateMask]
846
847	;
848	; XSAVE or FXSAVE?
849	;
850	or eax, eax
851	jz %%guest_fxsave
852
853	; XSAVE
854	mov edx, [pCpumCpu + CPUMCPU.Guest.fXStateMask + 4]
855	%ifdef VBOX_WITH_KERNEL_USING_XMM
856	and eax, ~CPUM_VOLATILE_XSAVE_GUEST_COMPONENTS ; Already saved in HMR0A.asm.
857	%endif
858	SAVE_32_OR_64_FPU pCpumCpu, pXState, 0, xsave
859	jmp %%guest_done
860
861	; FXSAVE
862	%%guest_fxsave:
863	SAVE_32_OR_64_FPU pCpumCpu, pXState, 0, fxsave
864
865	%%guest_done:
866	%endmacro ; CPUMR0_SAVE_GUEST
867
868
869	;;
870	; Wrapper for selecting 32-bit or 64-bit XRSTOR/FXRSTOR according to what SAVE_32_OR_64_FPU did.
871	;
872	; @param %1 Pointer to CPUMCPU.
873	; @param %2 Pointer to XState.
874	; @param %3 Force AMD64.
875	; @param %4 The instruction to use (xrstor or fxrstor).
876	; @uses xAX, xDX, EFLAGS
877	;
878	%macro RESTORE_32_OR_64_FPU 4
879	%if CPUM_IS_AMD64 \|\| %3
880	; Restore the guest FPU (32-bit or 64-bit), preserves existing broken state. See @bugref{7138}.
881	test dword [pCpumCpu + CPUMCPU.fUseFlags], CPUM_USE_SUPPORTS_LONGMODE
882	jz %%restore_32bit_fpu
883	cmp dword [pXState + X86_OFF_FXSTATE_RSVD], X86_FXSTATE_RSVD_32BIT_MAGIC
884	jne short %%restore_64bit_fpu
885	%%restore_32bit_fpu:
886	%endif
887	%4 [pXState]
888	%if CPUM_IS_AMD64 \|\| %3
889	; TODO: Restore XMM8-XMM15!
890	jmp short %%restore_fpu_done
891	%%restore_64bit_fpu:
892	o64 %4 [pXState]
893	%%restore_fpu_done:
894	%endif
895	%endmacro ; RESTORE_32_OR_64_FPU
896
897
898	;;
899	; Loads the guest state.
900	;
901	; @uses rax, rdx
902	; @param pCpumCpu Define for the register containing the CPUMCPU pointer.
903	; @param pXState Define for the register containing the extended state pointer.
904	;
905	%macro CPUMR0_LOAD_GUEST 0
906	;
907	; Load a couple of registers we'll use later in all branches.
908	;
909	%ifdef IN_RING0
910	mov pXState, [pCpumCpu + CPUMCPU.Guest.pXStateR0]
911	%elifdef IN_RC
912	mov pXState, [pCpumCpu + CPUMCPU.Guest.pXStateRC]
913	%else
914	%error "Unsupported context!"
915	%endif
916	mov eax, [pCpumCpu + CPUMCPU.Guest.fXStateMask]
917
918	;
919	; XRSTOR or FXRSTOR?
920	;
921	or eax, eax
922	jz %%guest_fxrstor
923
924	; XRSTOR
925	mov edx, [pCpumCpu + CPUMCPU.Guest.fXStateMask + 4]
926	%ifdef VBOX_WITH_KERNEL_USING_XMM
927	and eax, ~CPUM_VOLATILE_XSAVE_GUEST_COMPONENTS ; Will be loaded by HMR0A.asm.
928	%endif
929	RESTORE_32_OR_64_FPU pCpumCpu, pXState, 0, xrstor
930	jmp %%guest_done
931
932	; FXRSTOR
933	%%guest_fxrstor:
934	RESTORE_32_OR_64_FPU pCpumCpu, pXState, 0, fxrstor
935
936	%%guest_done:
937	%endmacro ; CPUMR0_LOAD_GUEST
938

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