CPUMInternal.mac@ 78359

Last change on this file since 78359 was 78220, checked in by vboxsync, 6 years ago
VMM: Nested VMX: bugref:9180 Hardware-assisted nested VT-x infrastructure changes and VM-entry implementation.
Property svn:eol-style set to `native` Property svn:keywords set to `Id Revision`
File size: 30.5 KB

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1	; $Id: CPUMInternal.mac 78220 2019-04-20 04:08:44Z vboxsync $
2	;; @file
3	; CPUM - Internal header file (asm).
4	;
5
6	;
7	; Copyright (C) 2006-2019 Oracle Corporation
8	;
9	; This file is part of VirtualBox Open Source Edition (OSE), as
10	; available from http://www.virtualbox.org. This file is free software;
11	; you can redistribute it and/or modify it under the terms of the GNU
12	; General Public License (GPL) as published by the Free Software
13	; Foundation, in version 2 as it comes in the "COPYING" file of the
14	; VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	; hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	;
17
18	%include "VBox/asmdefs.mac"
19	%include "VBox/vmm/cpum.mac"
20
21	;; Check sanity.
22	%ifdef VBOX_WITH_KERNEL_USING_XMM
23	%ifndef IN_RING0
24	%error "What? We've got code assuming VBOX_WITH_KERNEL_USING_XMM is only defined in ring-0!"
25	%endif
26	%endif
27
28	;; For numeric expressions
29	%ifdef RT_ARCH_AMD64
30	%define CPUM_IS_AMD64 1
31	%else
32	%define CPUM_IS_AMD64 0
33	%endif
34
35
36	;;
37	; CPU info
38	struc CPUMINFO
39	.cMsrRanges resd 1 ; uint32_t
40	.fMsrMask resd 1 ; uint32_t
41	.fMxCsrMask resd 1 ; uint32_t
42	.cCpuIdLeaves resd 1 ; uint32_t
43	.iFirstExtCpuIdLeaf resd 1 ; uint32_t
44	.enmUnknownCpuIdMethod resd 1 ; CPUMUNKNOWNCPUID
45	.DefCpuId resb CPUMCPUID_size ; CPUMCPUID
46	.uScalableBusFreq resq 1 ; uint64_t
47	.paMsrRangesR0 RTR0PTR_RES 1 ; R0PTRTYPE(PCPUMMSRRANGE)
48	.paCpuIdLeavesR0 RTR0PTR_RES 1 ; R0PTRTYPE(PCPUMCPUIDLEAF)
49	.paMsrRangesR3 RTR3PTR_RES 1 ; R3PTRTYPE(PCPUMMSRRANGE)
50	.paCpuIdLeavesR3 RTR3PTR_RES 1 ; R3PTRTYPE(PCPUMCPUIDLEAF)
51	.paMsrRangesRC RTRCPTR_RES 1 ; RCPTRTYPE(PCPUMMSRRANGE)
52	.paCpuIdLeavesRC RTRCPTR_RES 1 ; RCPTRTYPE(PCPUMCPUIDLEAF)
53	endstruc
54
55
56	%define CPUM_USED_FPU_HOST RT_BIT(0)
57	%define CPUM_USED_FPU_GUEST RT_BIT(10)
58	%define CPUM_USED_FPU_SINCE_REM RT_BIT(1)
59	%define CPUM_USED_MANUAL_XMM_RESTORE RT_BIT(2)
60	%define CPUM_USE_SYSENTER RT_BIT(3)
61	%define CPUM_USE_SYSCALL RT_BIT(4)
62	%define CPUM_USE_DEBUG_REGS_HOST RT_BIT(5)
63	%define CPUM_USED_DEBUG_REGS_HOST RT_BIT(6)
64	%define CPUM_USE_DEBUG_REGS_HYPER RT_BIT(7)
65	%define CPUM_USED_DEBUG_REGS_HYPER RT_BIT(8)
66	%define CPUM_USED_DEBUG_REGS_GUEST RT_BIT(9)
67	%define CPUM_SYNC_FPU_STATE RT_BIT(16)
68	%define CPUM_SYNC_DEBUG_REGS_GUEST RT_BIT(17)
69	%define CPUM_SYNC_DEBUG_REGS_HYPER RT_BIT(18)
70	%define CPUM_USE_FFXSR_LEAKY RT_BIT(19)
71	%define CPUM_USE_SUPPORTS_LONGMODE RT_BIT(20)
72
73	%define CPUM_HANDLER_DS 1
74	%define CPUM_HANDLER_ES 2
75	%define CPUM_HANDLER_FS 3
76	%define CPUM_HANDLER_GS 4
77	%define CPUM_HANDLER_IRET 5
78	%define CPUM_HANDLER_TYPEMASK 0ffh
79	%define CPUM_HANDLER_CTXCORE_IN_EBP RT_BIT(31)
80
81
82	struc CPUM
83	;...
84	.offCPUMCPU0 resd 1
85	.fHostUseFlags resd 1
86
87	; CR4 masks
88	.CR4.AndMask resd 1
89	.CR4.OrMask resd 1
90	; entered rawmode?
91	.u8PortableCpuIdLevel resb 1
92	.fPendingRestore resb 1
93
94	alignb 8
95	.fXStateGuestMask resq 1
96	.fXStateHostMask resq 1
97
98	alignb 64
99	.HostFeatures resb 48
100	.GuestFeatures resb 48
101	.GuestInfo resb RTHCPTR_CB4 + RTRCPTR_CB2 + 4*12
102
103	; Patch manager saved state compatability CPUID leaf arrays
104	.aGuestCpuIdPatmStd resb 16*6
105	.aGuestCpuIdPatmExt resb 16*10
106	.aGuestCpuIdPatmCentaur resb 16*4
107
108	alignb 8
109	.cMsrWrites resq 1
110	.cMsrWritesToIgnoredBits resq 1
111	.cMsrWritesRaiseGp resq 1
112	.cMsrWritesUnknown resq 1
113	.cMsrReads resq 1
114	.cMsrReadsRaiseGp resq 1
115	.cMsrReadsUnknown resq 1
116	endstruc
117
118	struc CPUMCPU
119	;
120	; Guest context state
121	; (Identical to the .Hyper chunk below and to CPUMCTX in cpum.mac.)
122	;
123	.Guest resq 0
124	.Guest.eax resq 1
125	.Guest.ecx resq 1
126	.Guest.edx resq 1
127	.Guest.ebx resq 1
128	.Guest.esp resq 1
129	.Guest.ebp resq 1
130	.Guest.esi resq 1
131	.Guest.edi resq 1
132	.Guest.r8 resq 1
133	.Guest.r9 resq 1
134	.Guest.r10 resq 1
135	.Guest.r11 resq 1
136	.Guest.r12 resq 1
137	.Guest.r13 resq 1
138	.Guest.r14 resq 1
139	.Guest.r15 resq 1
140	.Guest.es.Sel resw 1
141	.Guest.es.PaddingSel resw 1
142	.Guest.es.ValidSel resw 1
143	.Guest.es.fFlags resw 1
144	.Guest.es.u64Base resq 1
145	.Guest.es.u32Limit resd 1
146	.Guest.es.Attr resd 1
147	.Guest.cs.Sel resw 1
148	.Guest.cs.PaddingSel resw 1
149	.Guest.cs.ValidSel resw 1
150	.Guest.cs.fFlags resw 1
151	.Guest.cs.u64Base resq 1
152	.Guest.cs.u32Limit resd 1
153	.Guest.cs.Attr resd 1
154	.Guest.ss.Sel resw 1
155	.Guest.ss.PaddingSel resw 1
156	.Guest.ss.ValidSel resw 1
157	.Guest.ss.fFlags resw 1
158	.Guest.ss.u64Base resq 1
159	.Guest.ss.u32Limit resd 1
160	.Guest.ss.Attr resd 1
161	.Guest.ds.Sel resw 1
162	.Guest.ds.PaddingSel resw 1
163	.Guest.ds.ValidSel resw 1
164	.Guest.ds.fFlags resw 1
165	.Guest.ds.u64Base resq 1
166	.Guest.ds.u32Limit resd 1
167	.Guest.ds.Attr resd 1
168	.Guest.fs.Sel resw 1
169	.Guest.fs.PaddingSel resw 1
170	.Guest.fs.ValidSel resw 1
171	.Guest.fs.fFlags resw 1
172	.Guest.fs.u64Base resq 1
173	.Guest.fs.u32Limit resd 1
174	.Guest.fs.Attr resd 1
175	.Guest.gs.Sel resw 1
176	.Guest.gs.PaddingSel resw 1
177	.Guest.gs.ValidSel resw 1
178	.Guest.gs.fFlags resw 1
179	.Guest.gs.u64Base resq 1
180	.Guest.gs.u32Limit resd 1
181	.Guest.gs.Attr resd 1
182	.Guest.eip resq 1
183	.Guest.eflags resq 1
184	.Guest.cr0 resq 1
185	.Guest.cr2 resq 1
186	.Guest.cr3 resq 1
187	.Guest.cr4 resq 1
188	.Guest.dr resq 8
189	.Guest.gdtrPadding resw 3
190	.Guest.gdtr resw 0
191	.Guest.gdtr.cbGdt resw 1
192	.Guest.gdtr.pGdt resq 1
193	.Guest.idtrPadding resw 3
194	.Guest.idtr resw 0
195	.Guest.idtr.cbIdt resw 1
196	.Guest.idtr.pIdt resq 1
197	.Guest.ldtr.Sel resw 1
198	.Guest.ldtr.PaddingSel resw 1
199	.Guest.ldtr.ValidSel resw 1
200	.Guest.ldtr.fFlags resw 1
201	.Guest.ldtr.u64Base resq 1
202	.Guest.ldtr.u32Limit resd 1
203	.Guest.ldtr.Attr resd 1
204	.Guest.tr.Sel resw 1
205	.Guest.tr.PaddingSel resw 1
206	.Guest.tr.ValidSel resw 1
207	.Guest.tr.fFlags resw 1
208	.Guest.tr.u64Base resq 1
209	.Guest.tr.u32Limit resd 1
210	.Guest.tr.Attr resd 1
211	.Guest.SysEnter.cs resb 8
212	.Guest.SysEnter.eip resb 8
213	.Guest.SysEnter.esp resb 8
214	.Guest.msrEFER resb 8
215	.Guest.msrSTAR resb 8
216	.Guest.msrPAT resb 8
217	.Guest.msrLSTAR resb 8
218	.Guest.msrCSTAR resb 8
219	.Guest.msrSFMASK resb 8
220	.Guest.msrKERNELGSBASE resb 8
221	.Guest.uMsrPadding0 resb 8
222	alignb 8
223	.Guest.aXcr resq 2
224	.Guest.fXStateMask resq 1
225	.Guest.pXStateR0 RTR0PTR_RES 1
226	alignb 8
227	.Guest.pXStateR3 RTR3PTR_RES 1
228	alignb 8
229	.Guest.pXStateRC RTRCPTR_RES 1
230	.Guest.aoffXState resw 64
231	.Guest.fWorldSwitcher resd 1
232	.Guest.fExtrn resq 1
233	alignb 8
234	.Guest.hwvirt.svm.uMsrHSavePa resq 1
235	.Guest.hwvirt.svm.GCPhysVmcb resq 1
236	.Guest.hwvirt.svm.pVmcbR0 RTR0PTR_RES 1
237	alignb 8
238	.Guest.hwvirt.svm.pVmcbR3 RTR3PTR_RES 1
239	alignb 8
240	.Guest.hwvirt.svm.HostState resb 184
241	.Guest.hwvirt.svm.uPrevPauseTick resq 1
242	.Guest.hwvirt.svm.cPauseFilter resw 1
243	.Guest.hwvirt.svm.cPauseFilterThreshold resw 1
244	.Guest.hwvirt.svm.fInterceptEvents resb 1
245	alignb 8
246	.Guest.hwvirt.svm.pvMsrBitmapR0 RTR0PTR_RES 1
247	alignb 8
248	.Guest.hwvirt.svm.pvMsrBitmapR3 RTR3PTR_RES 1
249	alignb 8
250	.Guest.hwvirt.svm.pvIoBitmapR0 RTR0PTR_RES 1
251	alignb 8
252	.Guest.hwvirt.svm.pvIoBitmapR3 RTR3PTR_RES 1
253	alignb 8
254	.Guest.hwvirt.svm.HCPhysVmcb RTHCPHYS_RES 1
255	.Guest.hwvirt.svm.au64Padding0 resq 33
256	.Guest.hwvirt.enmHwvirt resd 1
257	.Guest.hwvirt.fGif resb 1
258	alignb 8
259	.Guest.hwvirt.fLocalForcedActions resd 1
260	alignb 64
261
262	.GuestMsrs resq 0
263	.GuestMsrs.au64 resq 64
264
265	;
266	; Other stuff.
267	;
268	.fUseFlags resd 1
269	.fChanged resd 1
270	.offCPUM resd 1
271	.u32RetCode resd 1
272
273	%ifdef VBOX_WITH_VMMR0_DISABLE_LAPIC_NMI
274	.pvApicBase RTR0PTR_RES 1
275	.fApicDisVectors resd 1
276	.fX2Apic resb 1
277	%else
278	.abPadding3 resb (RTR0PTR_CB + 4 + 1)
279	%endif
280
281	.fRawEntered resb 1
282	.fRemEntered resb 1
283	.fCpuIdApicFeatureVisible resb 1
284
285	.abPadding2 resb (64 - 16 - RTR0PTR_CB - 4 - 1 - 3)
286
287	;
288	; Host context state
289	;
290	alignb 64
291	.Host resb 0
292	%if HC_ARCH_BITS == 64
293	;.Host.rax resq 1 - scratch
294	.Host.rbx resq 1
295	;.Host.rcx resq 1 - scratch
296	;.Host.rdx resq 1 - scratch
297	.Host.rdi resq 1
298	.Host.rsi resq 1
299	.Host.rbp resq 1
300	.Host.rsp resq 1
301	;.Host.r8 resq 1 - scratch
302	;.Host.r9 resq 1 - scratch
303	.Host.r10 resq 1
304	.Host.r11 resq 1
305	.Host.r12 resq 1
306	.Host.r13 resq 1
307	.Host.r14 resq 1
308	.Host.r15 resq 1
309	;.Host.rip resd 1 - scratch
310	.Host.rflags resq 1
311	%endif
312	%if HC_ARCH_BITS == 32
313	;.Host.eax resd 1 - scratch
314	.Host.ebx resd 1
315	;.Host.edx resd 1 - scratch
316	;.Host.ecx resd 1 - scratch
317	.Host.edi resd 1
318	.Host.esi resd 1
319	.Host.ebp resd 1
320	.Host.eflags resd 1
321	;.Host.eip resd 1 - scratch
322	; lss pair!
323	.Host.esp resd 1
324	%endif
325	.Host.ss resw 1
326	.Host.ssPadding resw 1
327	.Host.gs resw 1
328	.Host.gsPadding resw 1
329	.Host.fs resw 1
330	.Host.fsPadding resw 1
331	.Host.es resw 1
332	.Host.esPadding resw 1
333	.Host.ds resw 1
334	.Host.dsPadding resw 1
335	.Host.cs resw 1
336	.Host.csPadding resw 1
337
338	%if HC_ARCH_BITS == 32
339	.Host.cr0 resd 1
340	;.Host.cr2 resd 1 - scratch
341	.Host.cr3 resd 1
342	.Host.cr4 resd 1
343	.Host.cr0Fpu resd 1
344
345	.Host.dr0 resd 1
346	.Host.dr1 resd 1
347	.Host.dr2 resd 1
348	.Host.dr3 resd 1
349	.Host.dr6 resd 1
350	.Host.dr7 resd 1
351
352	.Host.gdtr resb 6 ; GDT limit + linear address
353	.Host.gdtrPadding resw 1
354	.Host.idtr resb 6 ; IDT limit + linear address
355	.Host.idtrPadding resw 1
356	.Host.ldtr resw 1
357	.Host.ldtrPadding resw 1
358	.Host.tr resw 1
359	.Host.trPadding resw 1
360
361	alignb 8
362	.Host.SysEnter.cs resq 1
363	.Host.SysEnter.eip resq 1
364	.Host.SysEnter.esp resq 1
365	.Host.efer resq 1
366	.Host.auPadding resb (20)
367
368	%else ; 64-bit
369
370	.Host.cr0Fpu:
371	.Host.cr0 resq 1
372	;.Host.cr2 resq 1 - scratch
373	.Host.cr3 resq 1
374	.Host.cr4 resq 1
375	.Host.cr8 resq 1
376
377	.Host.dr0 resq 1
378	.Host.dr1 resq 1
379	.Host.dr2 resq 1
380	.Host.dr3 resq 1
381	.Host.dr6 resq 1
382	.Host.dr7 resq 1
383
384	.Host.gdtr resb 10 ; GDT limit + linear address
385	.Host.gdtrPadding resw 1
386	.Host.idtr resb 10 ; IDT limit + linear address
387	.Host.idtrPadding resw 1
388	.Host.ldtr resw 1
389	.Host.ldtrPadding resw 1
390	.Host.tr resw 1
391	.Host.trPadding resw 1
392
393	.Host.SysEnter.cs resq 1
394	.Host.SysEnter.eip resq 1
395	.Host.SysEnter.esp resq 1
396	.Host.FSbase resq 1
397	.Host.GSbase resq 1
398	.Host.efer resq 1
399	.Host.auPadding resb 4
400	%endif ; 64-bit
401	.Host.pXStateRC RTRCPTR_RES 1
402	alignb RTR0PTR_CB
403	.Host.pXStateR0 RTR0PTR_RES 1
404	.Host.pXStateR3 RTR3PTR_RES 1
405	alignb 8
406	.Host.xcr0 resq 1
407	.Host.fXStateMask resq 1
408
409	;
410	; Hypervisor Context (same as .Guest above).
411	;
412	alignb 64
413	.Hyper resq 0
414	.Hyper.eax resq 1
415	.Hyper.ecx resq 1
416	.Hyper.edx resq 1
417	.Hyper.ebx resq 1
418	.Hyper.esp resq 1
419	.Hyper.ebp resq 1
420	.Hyper.esi resq 1
421	.Hyper.edi resq 1
422	.Hyper.r8 resq 1
423	.Hyper.r9 resq 1
424	.Hyper.r10 resq 1
425	.Hyper.r11 resq 1
426	.Hyper.r12 resq 1
427	.Hyper.r13 resq 1
428	.Hyper.r14 resq 1
429	.Hyper.r15 resq 1
430	.Hyper.es.Sel resw 1
431	.Hyper.es.PaddingSel resw 1
432	.Hyper.es.ValidSel resw 1
433	.Hyper.es.fFlags resw 1
434	.Hyper.es.u64Base resq 1
435	.Hyper.es.u32Limit resd 1
436	.Hyper.es.Attr resd 1
437	.Hyper.cs.Sel resw 1
438	.Hyper.cs.PaddingSel resw 1
439	.Hyper.cs.ValidSel resw 1
440	.Hyper.cs.fFlags resw 1
441	.Hyper.cs.u64Base resq 1
442	.Hyper.cs.u32Limit resd 1
443	.Hyper.cs.Attr resd 1
444	.Hyper.ss.Sel resw 1
445	.Hyper.ss.PaddingSel resw 1
446	.Hyper.ss.ValidSel resw 1
447	.Hyper.ss.fFlags resw 1
448	.Hyper.ss.u64Base resq 1
449	.Hyper.ss.u32Limit resd 1
450	.Hyper.ss.Attr resd 1
451	.Hyper.ds.Sel resw 1
452	.Hyper.ds.PaddingSel resw 1
453	.Hyper.ds.ValidSel resw 1
454	.Hyper.ds.fFlags resw 1
455	.Hyper.ds.u64Base resq 1
456	.Hyper.ds.u32Limit resd 1
457	.Hyper.ds.Attr resd 1
458	.Hyper.fs.Sel resw 1
459	.Hyper.fs.PaddingSel resw 1
460	.Hyper.fs.ValidSel resw 1
461	.Hyper.fs.fFlags resw 1
462	.Hyper.fs.u64Base resq 1
463	.Hyper.fs.u32Limit resd 1
464	.Hyper.fs.Attr resd 1
465	.Hyper.gs.Sel resw 1
466	.Hyper.gs.PaddingSel resw 1
467	.Hyper.gs.ValidSel resw 1
468	.Hyper.gs.fFlags resw 1
469	.Hyper.gs.u64Base resq 1
470	.Hyper.gs.u32Limit resd 1
471	.Hyper.gs.Attr resd 1
472	.Hyper.eip resq 1
473	.Hyper.eflags resq 1
474	.Hyper.cr0 resq 1
475	.Hyper.cr2 resq 1
476	.Hyper.cr3 resq 1
477	.Hyper.cr4 resq 1
478	.Hyper.dr resq 8
479	.Hyper.gdtrPadding resw 3
480	.Hyper.gdtr resw 0
481	.Hyper.gdtr.cbGdt resw 1
482	.Hyper.gdtr.pGdt resq 1
483	.Hyper.idtrPadding resw 3
484	.Hyper.idtr resw 0
485	.Hyper.idtr.cbIdt resw 1
486	.Hyper.idtr.pIdt resq 1
487	.Hyper.ldtr.Sel resw 1
488	.Hyper.ldtr.PaddingSel resw 1
489	.Hyper.ldtr.ValidSel resw 1
490	.Hyper.ldtr.fFlags resw 1
491	.Hyper.ldtr.u64Base resq 1
492	.Hyper.ldtr.u32Limit resd 1
493	.Hyper.ldtr.Attr resd 1
494	.Hyper.tr.Sel resw 1
495	.Hyper.tr.PaddingSel resw 1
496	.Hyper.tr.ValidSel resw 1
497	.Hyper.tr.fFlags resw 1
498	.Hyper.tr.u64Base resq 1
499	.Hyper.tr.u32Limit resd 1
500	.Hyper.tr.Attr resd 1
501	.Hyper.SysEnter.cs resb 8
502	.Hyper.SysEnter.eip resb 8
503	.Hyper.SysEnter.esp resb 8
504	.Hyper.msrEFER resb 8
505	.Hyper.msrSTAR resb 8
506	.Hyper.msrPAT resb 8
507	.Hyper.msrLSTAR resb 8
508	.Hyper.msrCSTAR resb 8
509	.Hyper.msrSFMASK resb 8
510	.Hyper.msrKERNELGSBASE resb 8
511	.Hyper.uMsrPadding0 resb 8
512	alignb 8
513	.Hyper.aXcr resq 2
514	.Hyper.fXStateMask resq 1
515	.Hyper.pXStateR0 RTR0PTR_RES 1
516	alignb 8
517	.Hyper.pXStateR3 RTR3PTR_RES 1
518	alignb 8
519	.Hyper.pXStateRC RTRCPTR_RES 1
520	.Hyper.aoffXState resw 64
521	.Hyper.fWorldSwitcher resd 1
522	.Hyper.fExtrn resq 1
523	alignb 8
524	.Hyper.hwvirt.svm.uMsrHSavePa resq 1
525	.Hyper.hwvirt.svm.GCPhysVmcb resq 1
526	.Hyper.hwvirt.svm.pVmcbR0 RTR0PTR_RES 1
527	alignb 8
528	.Hyper.hwvirt.svm.pVmcbR3 RTR3PTR_RES 1
529	alignb 8
530	.Hyper.hwvirt.svm.HostState resb 184
531	.Hyper.hwvirt.svm.uPrevPauseTick resq 1
532	.Hyper.hwvirt.svm.cPauseFilter resw 1
533	.Hyper.hwvirt.svm.cPauseFilterThreshold resw 1
534	.Hyper.hwvirt.svm.fInterceptEvents resb 1
535	alignb 8
536	.Hyper.hwvirt.svm.pvMsrBitmapR0 RTR0PTR_RES 1
537	alignb 8
538	.Hyper.hwvirt.svm.pvMsrBitmapR3 RTR3PTR_RES 1
539	alignb 8
540	.Hyper.hwvirt.svm.pvIoBitmapR0 RTR0PTR_RES 1
541	alignb 8
542	.Hyper.hwvirt.svm.pvIoBitmapR3 RTR3PTR_RES 1
543	alignb 8
544	.Hyper.hwvirt.svm.HCPhysVmcb RTHCPHYS_RES 1
545	.Hyper.hwvirt.svm.au64Padding0 resq 33
546	.Hyper.hwvirt.enmHwvirt resd 1
547	.Hyper.hwvirt.fGif resb 1
548	alignb 8
549	.Hyper.hwvirt.fLocalForcedActions resd 1
550	alignb 64
551
552	%ifdef VBOX_WITH_CRASHDUMP_MAGIC
553	.aMagic resb 56
554	.uMagic resq 1
555	%endif
556	endstruc
557
558
559	;;
560	; Converts the CPUM pointer to CPUMCPU
561	; @param %1 register name
562	%macro CPUMCPU_FROM_CPUM 1
563	add %1, dword [%1 + CPUM.offCPUMCPU0]
564	%endmacro
565
566	;;
567	; Converts the CPUM pointer to CPUMCPU
568	; @param %1 register name (CPUM)
569	; @param %2 register name (CPUMCPU offset)
570	%macro CPUMCPU_FROM_CPUM_WITH_OFFSET 2
571	add %1, %2
572	%endmacro
573
574	;;
575	; Converts the CPUMCPU pointer to CPUM
576	; @param %1 register name
577	%macro CPUM_FROM_CPUMCPU 1
578	sub %1, dword [%1 + CPUMCPU.offCPUM]
579	%endmacro
580
581	;;
582	; Converts the CPUMCPU pointer to CPUM
583	; @param %1 register name (CPUM)
584	; @param %2 register name (CPUMCPU offset)
585	%macro CPUM_FROM_CPUMCPU_WITH_OFFSET 2
586	sub %1, %2
587	%endmacro
588
589
590
591	%if 0 ; Currently not used anywhere.
592	;;
593	; Macro for FXSAVE/FXRSTOR leaky behaviour on AMD CPUs, see cpumR3CheckLeakyFpu().
594	;
595	; Cleans the FPU state, if necessary, before restoring the FPU.
596	;
597	; This macro ASSUMES CR0.TS is not set!
598	;
599	; @param xDX Pointer to CPUMCPU.
600	; @uses xAX, EFLAGS
601	;
602	; Changes here should also be reflected in CPUMRCA.asm's copy!
603	;
604	%macro CLEANFPU 0
605	test dword [xDX + CPUMCPU.fUseFlags], CPUM_USE_FFXSR_LEAKY
606	jz .nothing_to_clean
607
608	xor eax, eax
609	fnstsw ax ; FSW -> AX.
610	test eax, RT_BIT(7) ; If FSW.ES (bit 7) is set, clear it to not cause FPU exceptions
611	; while clearing & loading the FPU bits in 'clean_fpu' below.
612	jz .clean_fpu
613	fnclex
614
615	.clean_fpu:
616	ffree st7 ; Clear FPU stack register(7)'s tag entry to prevent overflow if a wraparound occurs.
617	; for the upcoming push (load)
618	fild dword [g_r32_Zero xWrtRIP] ; Explicit FPU load to overwrite FIP, FOP, FDP registers in the FPU.
619	.nothing_to_clean:
620	%endmacro
621	%endif ; Unused.
622
623
624	;;
625	; Makes sure we don't trap (#NM) accessing the FPU.
626	;
627	; In ring-0 this is a bit of work since we may have try convince the host kernel
628	; to do the work for us, also, we must report any CR0 changes back to HMR0VMX
629	; via the VINF_CPUM_HOST_CR0_MODIFIED status code.
630	;
631	; If we end up clearing CR0.TS/EM ourselves in ring-0, we'll save the original
632	; value in CPUMCPU.Host.cr0Fpu. If we don't, we'll store zero there. (See also
633	; CPUMRZ_RESTORE_CR0_IF_TS_OR_EM_SET.)
634	;
635	; In raw-mode we will always have to clear TS and it will be recalculated
636	; elsewhere and thus needs no saving.
637	;
638	; @param %1 Register to return the return status code in.
639	; @param %2 Temporary scratch register.
640	; @param %3 Ring-0 only, register pointing to the CPUMCPU structure
641	; of the EMT we're on.
642	; @uses EFLAGS, CR0, %1, %2
643	;
644	%macro CPUMRZ_TOUCH_FPU_CLEAR_CR0_FPU_TRAPS_SET_RC 3
645	%ifdef IN_RC
646	;
647	; raw-mode - always clear it. We won't be here otherwise.
648	;
649	mov %2, cr0
650	and %2, ~(X86_CR0_TS \| X86_CR0_EM)
651	mov cr0, %2
652
653	%else
654	;
655	; ring-0 - slightly complicated.
656	;
657	xor %1, %1 ; 0 / VINF_SUCCESS. Wishing for no CR0 changes.
658	mov [%3 + CPUMCPU.Host.cr0Fpu], %1
659
660	mov %2, cr0
661	test %2, X86_CR0_TS \| X86_CR0_EM ; Make sure its safe to access the FPU state.
662	jz %%no_cr0_change
663
664	%ifdef VMM_R0_TOUCH_FPU
665	; Touch the state and check that the kernel updated CR0 for us.
666	movdqa xmm0, xmm0
667	mov %2, cr0
668	test %2, X86_CR0_TS \| X86_CR0_EM
669	jz %%cr0_changed
670	%endif
671
672	; Save CR0 and clear them flags ourselves.
673	mov [%3 + CPUMCPU.Host.cr0Fpu], %2
674	and %2, ~(X86_CR0_TS \| X86_CR0_EM)
675	mov cr0, %2
676	%endif ; IN_RING0
677
678	%%cr0_changed:
679	mov %1, VINF_CPUM_HOST_CR0_MODIFIED
680	%%no_cr0_change:
681	%endmacro
682
683
684	;;
685	; Restore CR0 if CR0.TS or CR0.EM were non-zero in the original state.
686	;
687	; @param %1 The original state to restore (or zero).
688	;
689	%macro CPUMRZ_RESTORE_CR0_IF_TS_OR_EM_SET 1
690	test %1, X86_CR0_TS \| X86_CR0_EM
691	jz %%skip_cr0_restore
692	mov cr0, %1
693	%%skip_cr0_restore:
694	%endmacro
695
696
697	;;
698	; Saves the host state.
699	;
700	; @uses rax, rdx
701	; @param pCpumCpu Define for the register containing the CPUMCPU pointer.
702	; @param pXState Define for the register containing the extended state pointer.
703	;
704	%macro CPUMR0_SAVE_HOST 0
705	;
706	; Load a couple of registers we'll use later in all branches.
707	;
708	%ifdef IN_RING0
709	mov pXState, [pCpumCpu + CPUMCPU.Host.pXStateR0]
710	%elifdef IN_RC
711	mov pXState, [pCpumCpu + CPUMCPU.Host.pXStateRC]
712	%else
713	%error "Unsupported context!"
714	%endif
715	mov eax, [pCpumCpu + CPUMCPU.Host.fXStateMask]
716
717	;
718	; XSAVE or FXSAVE?
719	;
720	or eax, eax
721	jz %%host_fxsave
722
723	; XSAVE
724	mov edx, [pCpumCpu + CPUMCPU.Host.fXStateMask + 4]
725	%ifdef RT_ARCH_AMD64
726	o64 xsave [pXState]
727	%else
728	xsave [pXState]
729	%endif
730	jmp %%host_done
731
732	; FXSAVE
733	%%host_fxsave:
734	%ifdef RT_ARCH_AMD64
735	o64 fxsave [pXState] ; Use explicit REX prefix. See @bugref{6398}.
736	%else
737	fxsave [pXState]
738	%endif
739
740	%%host_done:
741	%endmacro ; CPUMR0_SAVE_HOST
742
743
744	;;
745	; Loads the host state.
746	;
747	; @uses rax, rdx
748	; @param pCpumCpu Define for the register containing the CPUMCPU pointer.
749	; @param pXState Define for the register containing the extended state pointer.
750	;
751	%macro CPUMR0_LOAD_HOST 0
752	;
753	; Load a couple of registers we'll use later in all branches.
754	;
755	%ifdef IN_RING0
756	mov pXState, [pCpumCpu + CPUMCPU.Host.pXStateR0]
757	%elifdef IN_RC
758	mov pXState, [pCpumCpu + CPUMCPU.Host.pXStateRC]
759	%else
760	%error "Unsupported context!"
761	%endif
762	mov eax, [pCpumCpu + CPUMCPU.Host.fXStateMask]
763
764	;
765	; XRSTOR or FXRSTOR?
766	;
767	or eax, eax
768	jz %%host_fxrstor
769
770	; XRSTOR
771	mov edx, [pCpumCpu + CPUMCPU.Host.fXStateMask + 4]
772	%ifdef RT_ARCH_AMD64
773	o64 xrstor [pXState]
774	%else
775	xrstor [pXState]
776	%endif
777	jmp %%host_done
778
779	; FXRSTOR
780	%%host_fxrstor:
781	%ifdef RT_ARCH_AMD64
782	o64 fxrstor [pXState] ; Use explicit REX prefix. See @bugref{6398}.
783	%else
784	fxrstor [pXState]
785	%endif
786
787	%%host_done:
788	%endmacro ; CPUMR0_LOAD_HOST
789
790
791
792	;; Macro for XSAVE/FXSAVE for the guest FPU but tries to figure out whether to
793	; save the 32-bit FPU state or 64-bit FPU state.
794	;
795	; @param %1 Pointer to CPUMCPU.
796	; @param %2 Pointer to XState.
797	; @param %3 Force AMD64
798	; @param %4 The instruction to use (xsave or fxsave)
799	; @uses xAX, xDX, EFLAGS, 20h of stack.
800	;
801	%macro SAVE_32_OR_64_FPU 4
802	%if CPUM_IS_AMD64 \|\| %3
803	; Save the guest FPU (32-bit or 64-bit), preserves existing broken state. See @bugref{7138}.
804	test dword [pCpumCpu + CPUMCPU.fUseFlags], CPUM_USE_SUPPORTS_LONGMODE
805	jnz short %%save_long_mode_guest
806	%endif
807	%4 [pXState]
808	%if CPUM_IS_AMD64 \|\| %3
809	jmp %%save_done_32bit_cs_ds
810
811	%%save_long_mode_guest:
812	o64 %4 [pXState]
813
814	xor edx, edx
815	cmp dword [pXState + X86FXSTATE.FPUCS], 0
816	jne short %%save_done
817
818	sub rsp, 20h ; Only need 1ch bytes but keep stack aligned otherwise we #GP(0).
819	fnstenv [rsp]
820	movzx eax, word [rsp + 10h]
821	mov [pXState + X86FXSTATE.FPUCS], eax
822	movzx eax, word [rsp + 18h]
823	add rsp, 20h
824	mov [pXState + X86FXSTATE.FPUDS], eax
825	%endif
826	%%save_done_32bit_cs_ds:
827	mov edx, X86_FXSTATE_RSVD_32BIT_MAGIC
828	%%save_done:
829	mov dword [pXState + X86_OFF_FXSTATE_RSVD], edx
830	%endmacro ; SAVE_32_OR_64_FPU
831
832
833	;;
834	; Save the guest state.
835	;
836	; @uses rax, rdx
837	; @param pCpumCpu Define for the register containing the CPUMCPU pointer.
838	; @param pXState Define for the register containing the extended state pointer.
839	;
840	%macro CPUMR0_SAVE_GUEST 0
841	;
842	; Load a couple of registers we'll use later in all branches.
843	;
844	%ifdef IN_RING0
845	mov pXState, [pCpumCpu + CPUMCPU.Guest.pXStateR0]
846	%elifdef IN_RC
847	mov pXState, [pCpumCpu + CPUMCPU.Guest.pXStateRC]
848	%else
849	%error "Unsupported context!"
850	%endif
851	mov eax, [pCpumCpu + CPUMCPU.Guest.fXStateMask]
852
853	;
854	; XSAVE or FXSAVE?
855	;
856	or eax, eax
857	jz %%guest_fxsave
858
859	; XSAVE
860	mov edx, [pCpumCpu + CPUMCPU.Guest.fXStateMask + 4]
861	%ifdef VBOX_WITH_KERNEL_USING_XMM
862	and eax, ~CPUM_VOLATILE_XSAVE_GUEST_COMPONENTS ; Already saved in HMR0A.asm.
863	%endif
864	SAVE_32_OR_64_FPU pCpumCpu, pXState, 0, xsave
865	jmp %%guest_done
866
867	; FXSAVE
868	%%guest_fxsave:
869	SAVE_32_OR_64_FPU pCpumCpu, pXState, 0, fxsave
870
871	%%guest_done:
872	%endmacro ; CPUMR0_SAVE_GUEST
873
874
875	;;
876	; Wrapper for selecting 32-bit or 64-bit XRSTOR/FXRSTOR according to what SAVE_32_OR_64_FPU did.
877	;
878	; @param %1 Pointer to CPUMCPU.
879	; @param %2 Pointer to XState.
880	; @param %3 Force AMD64.
881	; @param %4 The instruction to use (xrstor or fxrstor).
882	; @uses xAX, xDX, EFLAGS
883	;
884	%macro RESTORE_32_OR_64_FPU 4
885	%if CPUM_IS_AMD64 \|\| %3
886	; Restore the guest FPU (32-bit or 64-bit), preserves existing broken state. See @bugref{7138}.
887	test dword [pCpumCpu + CPUMCPU.fUseFlags], CPUM_USE_SUPPORTS_LONGMODE
888	jz %%restore_32bit_fpu
889	cmp dword [pXState + X86_OFF_FXSTATE_RSVD], X86_FXSTATE_RSVD_32BIT_MAGIC
890	jne short %%restore_64bit_fpu
891	%%restore_32bit_fpu:
892	%endif
893	%4 [pXState]
894	%if CPUM_IS_AMD64 \|\| %3
895	; TODO: Restore XMM8-XMM15!
896	jmp short %%restore_fpu_done
897	%%restore_64bit_fpu:
898	o64 %4 [pXState]
899	%%restore_fpu_done:
900	%endif
901	%endmacro ; RESTORE_32_OR_64_FPU
902
903
904	;;
905	; Loads the guest state.
906	;
907	; @uses rax, rdx
908	; @param pCpumCpu Define for the register containing the CPUMCPU pointer.
909	; @param pXState Define for the register containing the extended state pointer.
910	;
911	%macro CPUMR0_LOAD_GUEST 0
912	;
913	; Load a couple of registers we'll use later in all branches.
914	;
915	%ifdef IN_RING0
916	mov pXState, [pCpumCpu + CPUMCPU.Guest.pXStateR0]
917	%elifdef IN_RC
918	mov pXState, [pCpumCpu + CPUMCPU.Guest.pXStateRC]
919	%else
920	%error "Unsupported context!"
921	%endif
922	mov eax, [pCpumCpu + CPUMCPU.Guest.fXStateMask]
923
924	;
925	; XRSTOR or FXRSTOR?
926	;
927	or eax, eax
928	jz %%guest_fxrstor
929
930	; XRSTOR
931	mov edx, [pCpumCpu + CPUMCPU.Guest.fXStateMask + 4]
932	%ifdef VBOX_WITH_KERNEL_USING_XMM
933	and eax, ~CPUM_VOLATILE_XSAVE_GUEST_COMPONENTS ; Will be loaded by HMR0A.asm.
934	%endif
935	RESTORE_32_OR_64_FPU pCpumCpu, pXState, 0, xrstor
936	jmp %%guest_done
937
938	; FXRSTOR
939	%%guest_fxrstor:
940	RESTORE_32_OR_64_FPU pCpumCpu, pXState, 0, fxrstor
941
942	%%guest_done:
943	%endmacro ; CPUMR0_LOAD_GUEST
944

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