CPUMInternal.mac@ 80507

Last change on this file since 80507 was 80191, checked in by vboxsync, 5 years ago
VMM/r3: Refactored VMCPU enumeration in preparation that aCpus will be replaced with a pointer array. Removed two raw-mode offset members from the CPUM and CPUMCPU sub-structures. bugref:9217 bugref:9517
Property svn:eol-style set to `native` Property svn:keywords set to `Id Revision`
File size: 22.3 KB

Line
1	; $Id: CPUMInternal.mac 80191 2019-08-08 00:36:57Z vboxsync $
2	;; @file
3	; CPUM - Internal header file (asm).
4	;
5
6	;
7	; Copyright (C) 2006-2019 Oracle Corporation
8	;
9	; This file is part of VirtualBox Open Source Edition (OSE), as
10	; available from http://www.virtualbox.org. This file is free software;
11	; you can redistribute it and/or modify it under the terms of the GNU
12	; General Public License (GPL) as published by the Free Software
13	; Foundation, in version 2 as it comes in the "COPYING" file of the
14	; VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	; hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	;
17
18	%include "VBox/asmdefs.mac"
19	%include "VBox/vmm/cpum.mac"
20
21	;; Check sanity.
22	%ifdef VBOX_WITH_KERNEL_USING_XMM
23	%ifndef IN_RING0
24	%error "What? We've got code assuming VBOX_WITH_KERNEL_USING_XMM is only defined in ring-0!"
25	%endif
26	%endif
27
28	;; For numeric expressions
29	%ifdef RT_ARCH_AMD64
30	%define CPUM_IS_AMD64 1
31	%else
32	%define CPUM_IS_AMD64 0
33	%endif
34
35
36	;;
37	; CPU info
38	struc CPUMINFO
39	.cMsrRanges resd 1 ; uint32_t
40	.fMsrMask resd 1 ; uint32_t
41	.fMxCsrMask resd 1 ; uint32_t
42	.cCpuIdLeaves resd 1 ; uint32_t
43	.iFirstExtCpuIdLeaf resd 1 ; uint32_t
44	.enmUnknownCpuIdMethod resd 1 ; CPUMUNKNOWNCPUID
45	.DefCpuId resb CPUMCPUID_size ; CPUMCPUID
46	.uScalableBusFreq resq 1 ; uint64_t
47	.paMsrRangesR0 RTR0PTR_RES 1 ; R0PTRTYPE(PCPUMMSRRANGE)
48	.paCpuIdLeavesR0 RTR0PTR_RES 1 ; R0PTRTYPE(PCPUMCPUIDLEAF)
49	.paMsrRangesR3 RTR3PTR_RES 1 ; R3PTRTYPE(PCPUMMSRRANGE)
50	.paCpuIdLeavesR3 RTR3PTR_RES 1 ; R3PTRTYPE(PCPUMCPUIDLEAF)
51	endstruc
52
53
54	%define CPUM_USED_FPU_HOST RT_BIT(0)
55	%define CPUM_USED_FPU_GUEST RT_BIT(10)
56	%define CPUM_USED_FPU_SINCE_REM RT_BIT(1)
57	%define CPUM_USED_MANUAL_XMM_RESTORE RT_BIT(2)
58	%define CPUM_USE_SYSENTER RT_BIT(3)
59	%define CPUM_USE_SYSCALL RT_BIT(4)
60	%define CPUM_USE_DEBUG_REGS_HOST RT_BIT(5)
61	%define CPUM_USED_DEBUG_REGS_HOST RT_BIT(6)
62	%define CPUM_USE_DEBUG_REGS_HYPER RT_BIT(7)
63	%define CPUM_USED_DEBUG_REGS_HYPER RT_BIT(8)
64	%define CPUM_USED_DEBUG_REGS_GUEST RT_BIT(9)
65	%define CPUM_SYNC_FPU_STATE RT_BIT(16)
66	%define CPUM_SYNC_DEBUG_REGS_GUEST RT_BIT(17)
67	%define CPUM_SYNC_DEBUG_REGS_HYPER RT_BIT(18)
68	%define CPUM_USE_FFXSR_LEAKY RT_BIT(19)
69	%define CPUM_USE_SUPPORTS_LONGMODE RT_BIT(20)
70
71	%define CPUM_HANDLER_DS 1
72	%define CPUM_HANDLER_ES 2
73	%define CPUM_HANDLER_FS 3
74	%define CPUM_HANDLER_GS 4
75	%define CPUM_HANDLER_IRET 5
76	%define CPUM_HANDLER_TYPEMASK 0ffh
77	%define CPUM_HANDLER_CTXCORE_IN_EBP RT_BIT(31)
78
79
80	struc CPUM
81	;...
82	.fHostUseFlags resd 1
83
84	; CR4 masks
85	.CR4.AndMask resd 1
86	.CR4.OrMask resd 1
87	.u8PortableCpuIdLevel resb 1
88	.fPendingRestore resb 1
89
90	alignb 8
91	.fXStateGuestMask resq 1
92	.fXStateHostMask resq 1
93
94	alignb 64
95	.HostFeatures resb 48
96	.GuestFeatures resb 48
97	.GuestInfo resb RTHCPTR_CB4 + 412
98
99	; Patch manager saved state compatability CPUID leaf arrays
100	.aGuestCpuIdPatmStd resb 16*6
101	.aGuestCpuIdPatmExt resb 16*10
102	.aGuestCpuIdPatmCentaur resb 16*4
103
104	alignb 8
105	.cMsrWrites resq 1
106	.cMsrWritesToIgnoredBits resq 1
107	.cMsrWritesRaiseGp resq 1
108	.cMsrWritesUnknown resq 1
109	.cMsrReads resq 1
110	.cMsrReadsRaiseGp resq 1
111	.cMsrReadsUnknown resq 1
112	endstruc
113
114	struc CPUMCPU
115	;
116	; Guest context state
117	; (Identical to the .Hyper chunk below and to CPUMCTX in cpum.mac.)
118	;
119	.Guest resq 0
120	.Guest.eax resq 1
121	.Guest.ecx resq 1
122	.Guest.edx resq 1
123	.Guest.ebx resq 1
124	.Guest.esp resq 1
125	.Guest.ebp resq 1
126	.Guest.esi resq 1
127	.Guest.edi resq 1
128	.Guest.r8 resq 1
129	.Guest.r9 resq 1
130	.Guest.r10 resq 1
131	.Guest.r11 resq 1
132	.Guest.r12 resq 1
133	.Guest.r13 resq 1
134	.Guest.r14 resq 1
135	.Guest.r15 resq 1
136	.Guest.es.Sel resw 1
137	.Guest.es.PaddingSel resw 1
138	.Guest.es.ValidSel resw 1
139	.Guest.es.fFlags resw 1
140	.Guest.es.u64Base resq 1
141	.Guest.es.u32Limit resd 1
142	.Guest.es.Attr resd 1
143	.Guest.cs.Sel resw 1
144	.Guest.cs.PaddingSel resw 1
145	.Guest.cs.ValidSel resw 1
146	.Guest.cs.fFlags resw 1
147	.Guest.cs.u64Base resq 1
148	.Guest.cs.u32Limit resd 1
149	.Guest.cs.Attr resd 1
150	.Guest.ss.Sel resw 1
151	.Guest.ss.PaddingSel resw 1
152	.Guest.ss.ValidSel resw 1
153	.Guest.ss.fFlags resw 1
154	.Guest.ss.u64Base resq 1
155	.Guest.ss.u32Limit resd 1
156	.Guest.ss.Attr resd 1
157	.Guest.ds.Sel resw 1
158	.Guest.ds.PaddingSel resw 1
159	.Guest.ds.ValidSel resw 1
160	.Guest.ds.fFlags resw 1
161	.Guest.ds.u64Base resq 1
162	.Guest.ds.u32Limit resd 1
163	.Guest.ds.Attr resd 1
164	.Guest.fs.Sel resw 1
165	.Guest.fs.PaddingSel resw 1
166	.Guest.fs.ValidSel resw 1
167	.Guest.fs.fFlags resw 1
168	.Guest.fs.u64Base resq 1
169	.Guest.fs.u32Limit resd 1
170	.Guest.fs.Attr resd 1
171	.Guest.gs.Sel resw 1
172	.Guest.gs.PaddingSel resw 1
173	.Guest.gs.ValidSel resw 1
174	.Guest.gs.fFlags resw 1
175	.Guest.gs.u64Base resq 1
176	.Guest.gs.u32Limit resd 1
177	.Guest.gs.Attr resd 1
178	.Guest.eip resq 1
179	.Guest.eflags resq 1
180	.Guest.cr0 resq 1
181	.Guest.cr2 resq 1
182	.Guest.cr3 resq 1
183	.Guest.cr4 resq 1
184	.Guest.dr resq 8
185	.Guest.gdtrPadding resw 3
186	.Guest.gdtr resw 0
187	.Guest.gdtr.cbGdt resw 1
188	.Guest.gdtr.pGdt resq 1
189	.Guest.idtrPadding resw 3
190	.Guest.idtr resw 0
191	.Guest.idtr.cbIdt resw 1
192	.Guest.idtr.pIdt resq 1
193	.Guest.ldtr.Sel resw 1
194	.Guest.ldtr.PaddingSel resw 1
195	.Guest.ldtr.ValidSel resw 1
196	.Guest.ldtr.fFlags resw 1
197	.Guest.ldtr.u64Base resq 1
198	.Guest.ldtr.u32Limit resd 1
199	.Guest.ldtr.Attr resd 1
200	.Guest.tr.Sel resw 1
201	.Guest.tr.PaddingSel resw 1
202	.Guest.tr.ValidSel resw 1
203	.Guest.tr.fFlags resw 1
204	.Guest.tr.u64Base resq 1
205	.Guest.tr.u32Limit resd 1
206	.Guest.tr.Attr resd 1
207	.Guest.SysEnter.cs resb 8
208	.Guest.SysEnter.eip resb 8
209	.Guest.SysEnter.esp resb 8
210	.Guest.msrEFER resb 8
211	.Guest.msrSTAR resb 8
212	.Guest.msrPAT resb 8
213	.Guest.msrLSTAR resb 8
214	.Guest.msrCSTAR resb 8
215	.Guest.msrSFMASK resb 8
216	.Guest.msrKERNELGSBASE resb 8
217	.Guest.uMsrPadding0 resb 8
218	alignb 8
219	.Guest.aXcr resq 2
220	.Guest.fXStateMask resq 1
221	.Guest.pXStateR0 RTR0PTR_RES 1
222	alignb 8
223	.Guest.pXStateR3 RTR3PTR_RES 1
224	alignb 8
225	.Guest.aoffXState resw 64
226	.Guest.fWorldSwitcher resd 1
227	alignb 8
228	.Guest.fExtrn resq 1
229	alignb 8
230	.Guest.hwvirt.svm.uMsrHSavePa resq 1
231	.Guest.hwvirt.svm.GCPhysVmcb resq 1
232	.Guest.hwvirt.svm.pVmcbR0 RTR0PTR_RES 1
233	alignb 8
234	.Guest.hwvirt.svm.pVmcbR3 RTR3PTR_RES 1
235	alignb 8
236	.Guest.hwvirt.svm.HostState resb 184
237	.Guest.hwvirt.svm.uPrevPauseTick resq 1
238	.Guest.hwvirt.svm.cPauseFilter resw 1
239	.Guest.hwvirt.svm.cPauseFilterThreshold resw 1
240	.Guest.hwvirt.svm.fInterceptEvents resb 1
241	alignb 8
242	.Guest.hwvirt.svm.pvMsrBitmapR0 RTR0PTR_RES 1
243	alignb 8
244	.Guest.hwvirt.svm.pvMsrBitmapR3 RTR3PTR_RES 1
245	alignb 8
246	.Guest.hwvirt.svm.pvIoBitmapR0 RTR0PTR_RES 1
247	alignb 8
248	.Guest.hwvirt.svm.pvIoBitmapR3 RTR3PTR_RES 1
249	alignb 8
250	.Guest.hwvirt.svm.HCPhysVmcb RTHCPHYS_RES 1
251	.Guest.hwvirt.svm.abPadding0 resb 272
252	.Guest.hwvirt.enmHwvirt resd 1
253	.Guest.hwvirt.fGif resb 1
254	alignb 8
255	.Guest.hwvirt.fLocalForcedActions resd 1
256	alignb 64
257
258	.GuestMsrs resq 0
259	.GuestMsrs.au64 resq 64
260
261	;
262	; Other stuff.
263	;
264	.fUseFlags resd 1
265	.fChanged resd 1
266	.u32RetCode resd 1
267
268	%ifdef VBOX_WITH_VMMR0_DISABLE_LAPIC_NMI
269	.fApicDisVectors resd 1
270	.pvApicBase RTR0PTR_RES 1
271	.fX2Apic resb 1
272	%else
273	.abPadding3 resb (4 + RTR0PTR_CB + 1)
274	%endif
275
276	.fRemEntered resb 1
277	.fCpuIdApicFeatureVisible resb 1
278
279	.abPadding2 resb (64 - 16 - RTR0PTR_CB - 4 - 1 - 2 + 4)
280
281	;
282	; Host context state
283	;
284	alignb 64
285	.Host resb 0
286	;.Host.rax resq 1 - scratch
287	.Host.rbx resq 1
288	;.Host.rcx resq 1 - scratch
289	;.Host.rdx resq 1 - scratch
290	.Host.rdi resq 1
291	.Host.rsi resq 1
292	.Host.rbp resq 1
293	.Host.rsp resq 1
294	;.Host.r8 resq 1 - scratch
295	;.Host.r9 resq 1 - scratch
296	.Host.r10 resq 1
297	.Host.r11 resq 1
298	.Host.r12 resq 1
299	.Host.r13 resq 1
300	.Host.r14 resq 1
301	.Host.r15 resq 1
302	;.Host.rip resd 1 - scratch
303	.Host.rflags resq 1
304	.Host.ss resw 1
305	.Host.ssPadding resw 1
306	.Host.gs resw 1
307	.Host.gsPadding resw 1
308	.Host.fs resw 1
309	.Host.fsPadding resw 1
310	.Host.es resw 1
311	.Host.esPadding resw 1
312	.Host.ds resw 1
313	.Host.dsPadding resw 1
314	.Host.cs resw 1
315	.Host.csPadding resw 1
316
317	.Host.cr0Fpu:
318	.Host.cr0 resq 1
319	;.Host.cr2 resq 1 - scratch
320	.Host.cr3 resq 1
321	.Host.cr4 resq 1
322	.Host.cr8 resq 1
323
324	.Host.dr0 resq 1
325	.Host.dr1 resq 1
326	.Host.dr2 resq 1
327	.Host.dr3 resq 1
328	.Host.dr6 resq 1
329	.Host.dr7 resq 1
330
331	.Host.gdtr resb 10 ; GDT limit + linear address
332	.Host.gdtrPadding resw 1
333	.Host.idtr resb 10 ; IDT limit + linear address
334	.Host.idtrPadding resw 1
335	.Host.ldtr resw 1
336	.Host.ldtrPadding resw 1
337	.Host.tr resw 1
338	.Host.trPadding resw 1
339
340	.Host.SysEnter.cs resq 1
341	.Host.SysEnter.eip resq 1
342	.Host.SysEnter.esp resq 1
343	.Host.FSbase resq 1
344	.Host.GSbase resq 1
345	.Host.efer resq 1
346	.Host.auPadding resb 4
347	alignb RTR0PTR_CB
348	.Host.pXStateR0 RTR0PTR_RES 1
349	.Host.pXStateR3 RTR3PTR_RES 1
350	alignb 8
351	.Host.xcr0 resq 1
352	.Host.fXStateMask resq 1
353
354	;
355	; Hypervisor Context.
356	;
357	alignb 64
358	.Hyper resq 0
359	.Hyper.dr resq 8
360	.Hyper.cr3 resq 1
361	alignb 64
362
363	%ifdef VBOX_WITH_CRASHDUMP_MAGIC
364	.aMagic resb 56
365	.uMagic resq 1
366	%endif
367	endstruc
368
369
370
371	%if 0 ; Currently not used anywhere.
372	;;
373	; Macro for FXSAVE/FXRSTOR leaky behaviour on AMD CPUs, see cpumR3CheckLeakyFpu().
374	;
375	; Cleans the FPU state, if necessary, before restoring the FPU.
376	;
377	; This macro ASSUMES CR0.TS is not set!
378	;
379	; @param xDX Pointer to CPUMCPU.
380	; @uses xAX, EFLAGS
381	;
382	; Changes here should also be reflected in CPUMRCA.asm's copy!
383	;
384	%macro CLEANFPU 0
385	test dword [xDX + CPUMCPU.fUseFlags], CPUM_USE_FFXSR_LEAKY
386	jz .nothing_to_clean
387
388	xor eax, eax
389	fnstsw ax ; FSW -> AX.
390	test eax, RT_BIT(7) ; If FSW.ES (bit 7) is set, clear it to not cause FPU exceptions
391	; while clearing & loading the FPU bits in 'clean_fpu' below.
392	jz .clean_fpu
393	fnclex
394
395	.clean_fpu:
396	ffree st7 ; Clear FPU stack register(7)'s tag entry to prevent overflow if a wraparound occurs.
397	; for the upcoming push (load)
398	fild dword [g_r32_Zero xWrtRIP] ; Explicit FPU load to overwrite FIP, FOP, FDP registers in the FPU.
399	.nothing_to_clean:
400	%endmacro
401	%endif ; Unused.
402
403
404	;;
405	; Makes sure we don't trap (#NM) accessing the FPU.
406	;
407	; In ring-0 this is a bit of work since we may have try convince the host kernel
408	; to do the work for us, also, we must report any CR0 changes back to HMR0VMX
409	; via the VINF_CPUM_HOST_CR0_MODIFIED status code.
410	;
411	; If we end up clearing CR0.TS/EM ourselves in ring-0, we'll save the original
412	; value in CPUMCPU.Host.cr0Fpu. If we don't, we'll store zero there. (See also
413	; CPUMRZ_RESTORE_CR0_IF_TS_OR_EM_SET.)
414	;
415	; In raw-mode we will always have to clear TS and it will be recalculated
416	; elsewhere and thus needs no saving.
417	;
418	; @param %1 Register to return the return status code in.
419	; @param %2 Temporary scratch register.
420	; @param %3 Ring-0 only, register pointing to the CPUMCPU structure
421	; of the EMT we're on.
422	; @uses EFLAGS, CR0, %1, %2
423	;
424	%macro CPUMRZ_TOUCH_FPU_CLEAR_CR0_FPU_TRAPS_SET_RC 3
425	;
426	; ring-0 - slightly complicated (than old raw-mode).
427	;
428	xor %1, %1 ; 0 / VINF_SUCCESS. Wishing for no CR0 changes.
429	mov [%3 + CPUMCPU.Host.cr0Fpu], %1
430
431	mov %2, cr0
432	test %2, X86_CR0_TS \| X86_CR0_EM ; Make sure its safe to access the FPU state.
433	jz %%no_cr0_change
434
435	%ifdef VMM_R0_TOUCH_FPU
436	; Touch the state and check that the kernel updated CR0 for us.
437	movdqa xmm0, xmm0
438	mov %2, cr0
439	test %2, X86_CR0_TS \| X86_CR0_EM
440	jz %%cr0_changed
441	%endif
442
443	; Save CR0 and clear them flags ourselves.
444	mov [%3 + CPUMCPU.Host.cr0Fpu], %2
445	and %2, ~(X86_CR0_TS \| X86_CR0_EM)
446	mov cr0, %2
447
448	%%cr0_changed:
449	mov %1, VINF_CPUM_HOST_CR0_MODIFIED
450	%%no_cr0_change:
451	%endmacro
452
453
454	;;
455	; Restore CR0 if CR0.TS or CR0.EM were non-zero in the original state.
456	;
457	; @param %1 The original state to restore (or zero).
458	;
459	%macro CPUMRZ_RESTORE_CR0_IF_TS_OR_EM_SET 1
460	test %1, X86_CR0_TS \| X86_CR0_EM
461	jz %%skip_cr0_restore
462	mov cr0, %1
463	%%skip_cr0_restore:
464	%endmacro
465
466
467	;;
468	; Saves the host state.
469	;
470	; @uses rax, rdx
471	; @param pCpumCpu Define for the register containing the CPUMCPU pointer.
472	; @param pXState Define for the register containing the extended state pointer.
473	;
474	%macro CPUMR0_SAVE_HOST 0
475	;
476	; Load a couple of registers we'll use later in all branches.
477	;
478	%ifdef IN_RING0
479	mov pXState, [pCpumCpu + CPUMCPU.Host.pXStateR0]
480	%else
481	%error "Unsupported context!"
482	%endif
483	mov eax, [pCpumCpu + CPUMCPU.Host.fXStateMask]
484
485	;
486	; XSAVE or FXSAVE?
487	;
488	or eax, eax
489	jz %%host_fxsave
490
491	; XSAVE
492	mov edx, [pCpumCpu + CPUMCPU.Host.fXStateMask + 4]
493	%ifdef RT_ARCH_AMD64
494	o64 xsave [pXState]
495	%else
496	xsave [pXState]
497	%endif
498	jmp %%host_done
499
500	; FXSAVE
501	%%host_fxsave:
502	%ifdef RT_ARCH_AMD64
503	o64 fxsave [pXState] ; Use explicit REX prefix. See @bugref{6398}.
504	%else
505	fxsave [pXState]
506	%endif
507
508	%%host_done:
509	%endmacro ; CPUMR0_SAVE_HOST
510
511
512	;;
513	; Loads the host state.
514	;
515	; @uses rax, rdx
516	; @param pCpumCpu Define for the register containing the CPUMCPU pointer.
517	; @param pXState Define for the register containing the extended state pointer.
518	;
519	%macro CPUMR0_LOAD_HOST 0
520	;
521	; Load a couple of registers we'll use later in all branches.
522	;
523	%ifdef IN_RING0
524	mov pXState, [pCpumCpu + CPUMCPU.Host.pXStateR0]
525	%else
526	%error "Unsupported context!"
527	%endif
528	mov eax, [pCpumCpu + CPUMCPU.Host.fXStateMask]
529
530	;
531	; XRSTOR or FXRSTOR?
532	;
533	or eax, eax
534	jz %%host_fxrstor
535
536	; XRSTOR
537	mov edx, [pCpumCpu + CPUMCPU.Host.fXStateMask + 4]
538	%ifdef RT_ARCH_AMD64
539	o64 xrstor [pXState]
540	%else
541	xrstor [pXState]
542	%endif
543	jmp %%host_done
544
545	; FXRSTOR
546	%%host_fxrstor:
547	%ifdef RT_ARCH_AMD64
548	o64 fxrstor [pXState] ; Use explicit REX prefix. See @bugref{6398}.
549	%else
550	fxrstor [pXState]
551	%endif
552
553	%%host_done:
554	%endmacro ; CPUMR0_LOAD_HOST
555
556
557
558	;; Macro for XSAVE/FXSAVE for the guest FPU but tries to figure out whether to
559	; save the 32-bit FPU state or 64-bit FPU state.
560	;
561	; @param %1 Pointer to CPUMCPU.
562	; @param %2 Pointer to XState.
563	; @param %3 Force AMD64
564	; @param %4 The instruction to use (xsave or fxsave)
565	; @uses xAX, xDX, EFLAGS, 20h of stack.
566	;
567	%macro SAVE_32_OR_64_FPU 4
568	%if CPUM_IS_AMD64 \|\| %3
569	; Save the guest FPU (32-bit or 64-bit), preserves existing broken state. See @bugref{7138}.
570	test dword [pCpumCpu + CPUMCPU.fUseFlags], CPUM_USE_SUPPORTS_LONGMODE
571	jnz short %%save_long_mode_guest
572	%endif
573	%4 [pXState]
574	%if CPUM_IS_AMD64 \|\| %3
575	jmp %%save_done_32bit_cs_ds
576
577	%%save_long_mode_guest:
578	o64 %4 [pXState]
579
580	xor edx, edx
581	cmp dword [pXState + X86FXSTATE.FPUCS], 0
582	jne short %%save_done
583
584	sub rsp, 20h ; Only need 1ch bytes but keep stack aligned otherwise we #GP(0).
585	fnstenv [rsp]
586	movzx eax, word [rsp + 10h]
587	mov [pXState + X86FXSTATE.FPUCS], eax
588	movzx eax, word [rsp + 18h]
589	add rsp, 20h
590	mov [pXState + X86FXSTATE.FPUDS], eax
591	%endif
592	%%save_done_32bit_cs_ds:
593	mov edx, X86_FXSTATE_RSVD_32BIT_MAGIC
594	%%save_done:
595	mov dword [pXState + X86_OFF_FXSTATE_RSVD], edx
596	%endmacro ; SAVE_32_OR_64_FPU
597
598
599	;;
600	; Save the guest state.
601	;
602	; @uses rax, rdx
603	; @param pCpumCpu Define for the register containing the CPUMCPU pointer.
604	; @param pXState Define for the register containing the extended state pointer.
605	;
606	%macro CPUMR0_SAVE_GUEST 0
607	;
608	; Load a couple of registers we'll use later in all branches.
609	;
610	%ifdef IN_RING0
611	mov pXState, [pCpumCpu + CPUMCPU.Guest.pXStateR0]
612	%else
613	%error "Unsupported context!"
614	%endif
615	mov eax, [pCpumCpu + CPUMCPU.Guest.fXStateMask]
616
617	;
618	; XSAVE or FXSAVE?
619	;
620	or eax, eax
621	jz %%guest_fxsave
622
623	; XSAVE
624	mov edx, [pCpumCpu + CPUMCPU.Guest.fXStateMask + 4]
625	%ifdef VBOX_WITH_KERNEL_USING_XMM
626	and eax, ~CPUM_VOLATILE_XSAVE_GUEST_COMPONENTS ; Already saved in HMR0A.asm.
627	%endif
628	SAVE_32_OR_64_FPU pCpumCpu, pXState, 0, xsave
629	jmp %%guest_done
630
631	; FXSAVE
632	%%guest_fxsave:
633	SAVE_32_OR_64_FPU pCpumCpu, pXState, 0, fxsave
634
635	%%guest_done:
636	%endmacro ; CPUMR0_SAVE_GUEST
637
638
639	;;
640	; Wrapper for selecting 32-bit or 64-bit XRSTOR/FXRSTOR according to what SAVE_32_OR_64_FPU did.
641	;
642	; @param %1 Pointer to CPUMCPU.
643	; @param %2 Pointer to XState.
644	; @param %3 Force AMD64.
645	; @param %4 The instruction to use (xrstor or fxrstor).
646	; @uses xAX, xDX, EFLAGS
647	;
648	%macro RESTORE_32_OR_64_FPU 4
649	%if CPUM_IS_AMD64 \|\| %3
650	; Restore the guest FPU (32-bit or 64-bit), preserves existing broken state. See @bugref{7138}.
651	test dword [pCpumCpu + CPUMCPU.fUseFlags], CPUM_USE_SUPPORTS_LONGMODE
652	jz %%restore_32bit_fpu
653	cmp dword [pXState + X86_OFF_FXSTATE_RSVD], X86_FXSTATE_RSVD_32BIT_MAGIC
654	jne short %%restore_64bit_fpu
655	%%restore_32bit_fpu:
656	%endif
657	%4 [pXState]
658	%if CPUM_IS_AMD64 \|\| %3
659	; TODO: Restore XMM8-XMM15!
660	jmp short %%restore_fpu_done
661	%%restore_64bit_fpu:
662	o64 %4 [pXState]
663	%%restore_fpu_done:
664	%endif
665	%endmacro ; RESTORE_32_OR_64_FPU
666
667
668	;;
669	; Loads the guest state.
670	;
671	; @uses rax, rdx
672	; @param pCpumCpu Define for the register containing the CPUMCPU pointer.
673	; @param pXState Define for the register containing the extended state pointer.
674	;
675	%macro CPUMR0_LOAD_GUEST 0
676	;
677	; Load a couple of registers we'll use later in all branches.
678	;
679	%ifdef IN_RING0
680	mov pXState, [pCpumCpu + CPUMCPU.Guest.pXStateR0]
681	%else
682	%error "Unsupported context!"
683	%endif
684	mov eax, [pCpumCpu + CPUMCPU.Guest.fXStateMask]
685
686	;
687	; XRSTOR or FXRSTOR?
688	;
689	or eax, eax
690	jz %%guest_fxrstor
691
692	; XRSTOR
693	mov edx, [pCpumCpu + CPUMCPU.Guest.fXStateMask + 4]
694	%ifdef VBOX_WITH_KERNEL_USING_XMM
695	and eax, ~CPUM_VOLATILE_XSAVE_GUEST_COMPONENTS ; Will be loaded by HMR0A.asm.
696	%endif
697	RESTORE_32_OR_64_FPU pCpumCpu, pXState, 0, xrstor
698	jmp %%guest_done
699
700	; FXRSTOR
701	%%guest_fxrstor:
702	RESTORE_32_OR_64_FPU pCpumCpu, pXState, 0, fxrstor
703
704	%%guest_done:
705	%endmacro ; CPUMR0_LOAD_GUEST
706

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