VirtualBox

source: vbox/trunk/src/VBox/VMM/include/EMHandleRCTmpl.h@ 72422

Last change on this file since 72422 was 72208, checked in by vboxsync, 7 years ago

VMM: VBOX_WITH_NESTED_HWVIRT_SVM.
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1/* $Id: EMHandleRCTmpl.h 72208 2018-05-15 04:11:35Z vboxsync $ */
2/** @file
3 * EM - emR3[Raw|Hm|Nem]HandleRC template.
4 */
5
6/*
7 * Copyright (C) 2006-2018 Oracle Corporation
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 */
17
18#ifndef ___EMHandleRCTmpl_h
19#define ___EMHandleRCTmpl_h
20
21#if defined(EMHANDLERC_WITH_PATM) + defined(EMHANDLERC_WITH_HM) + defined(EMHANDLERC_WITH_NEM) != 1
22# error "Exactly one of these must be defined: EMHANDLERC_WITH_PATM, EMHANDLERC_WITH_HM, EMHANDLERC_WITH_NEM"
23#endif
24
25
26/**
27 * Process a subset of the raw-mode and hm return codes.
28 *
29 * Since we have to share this with raw-mode single stepping, this inline
30 * function has been created to avoid code duplication.
31 *
32 * @returns VINF_SUCCESS if it's ok to continue raw mode.
33 * @returns VBox status code to return to the EM main loop.
34 *
35 * @param pVM The cross context VM structure.
36 * @param pVCpu The cross context virtual CPU structure.
37 * @param pCtx Pointer to the guest CPU context.
38 * @param rc The return code.
39 */
40#ifdef EMHANDLERC_WITH_PATM
41int emR3RawHandleRC(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx, int rc)
42#elif defined(EMHANDLERC_WITH_HM) || defined(DOXYGEN_RUNNING)
43int emR3HmHandleRC(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx, int rc)
44#elif defined(EMHANDLERC_WITH_NEM)
45int emR3NemHandleRC(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx, int rc)
46#endif
47{
48 switch (rc)
49 {
50 /*
51 * Common & simple ones.
52 */
53 case VINF_SUCCESS:
54 break;
55 case VINF_EM_RESCHEDULE_RAW:
56 case VINF_EM_RESCHEDULE_HM:
57 case VINF_EM_RAW_INTERRUPT:
58 case VINF_EM_RAW_TO_R3:
59 case VINF_EM_RAW_TIMER_PENDING:
60 case VINF_EM_PENDING_REQUEST:
61 rc = VINF_SUCCESS;
62 break;
63
64#ifdef EMHANDLERC_WITH_PATM
65 /*
66 * Privileged instruction.
67 */
68 case VINF_EM_RAW_EXCEPTION_PRIVILEGED:
69 case VINF_PATM_PATCH_TRAP_GP:
70 rc = emR3RawPrivileged(pVM, pVCpu);
71 break;
72
73 case VINF_EM_RAW_GUEST_TRAP:
74 /*
75 * Got a trap which needs dispatching.
76 */
77 if (PATMR3IsInsidePatchJump(pVM, pCtx->eip, NULL))
78 {
79 AssertReleaseMsgFailed(("FATAL ERROR: executing random instruction inside generated patch jump %08X\n", CPUMGetGuestEIP(pVCpu)));
80 rc = VERR_EM_RAW_PATCH_CONFLICT;
81 break;
82 }
83 rc = emR3RawGuestTrap(pVM, pVCpu);
84 break;
85
86 /*
87 * Trap in patch code.
88 */
89 case VINF_PATM_PATCH_TRAP_PF:
90 case VINF_PATM_PATCH_INT3:
91 rc = emR3RawPatchTrap(pVM, pVCpu, pCtx, rc);
92 break;
93
94 case VINF_PATM_DUPLICATE_FUNCTION:
95 Assert(PATMIsPatchGCAddr(pVM, pCtx->eip));
96 rc = PATMR3DuplicateFunctionRequest(pVM, pCtx);
97 AssertRC(rc);
98 rc = VINF_SUCCESS;
99 break;
100
101 case VINF_PATM_CHECK_PATCH_PAGE:
102 rc = PATMR3HandleMonitoredPage(pVM);
103 AssertRC(rc);
104 rc = VINF_SUCCESS;
105 break;
106
107 /*
108 * Patch manager.
109 */
110 case VERR_EM_RAW_PATCH_CONFLICT:
111 AssertReleaseMsgFailed(("%Rrc handling is not yet implemented\n", rc));
112 break;
113#endif /* EMHANDLERC_WITH_PATM */
114
115#ifdef EMHANDLERC_WITH_PATM
116 /*
117 * Memory mapped I/O access - attempt to patch the instruction
118 */
119 case VINF_PATM_HC_MMIO_PATCH_READ:
120 rc = PATMR3InstallPatch(pVM, SELMToFlat(pVM, DISSELREG_CS, CPUMCTX2CORE(pCtx), pCtx->eip),
121 PATMFL_MMIO_ACCESS
122 | (CPUMGetGuestCodeBits(pVCpu) == 32 ? PATMFL_CODE32 : 0));
123 if (RT_FAILURE(rc))
124 rc = emR3ExecuteInstruction(pVM, pVCpu, "MMIO");
125 break;
126
127 case VINF_PATM_HC_MMIO_PATCH_WRITE:
128 AssertFailed(); /* not yet implemented. */
129 rc = emR3ExecuteInstruction(pVM, pVCpu, "MMIO");
130 break;
131#endif /* EMHANDLERC_WITH_PATM */
132
133#ifndef EMHANDLERC_WITH_NEM
134 /*
135 * Conflict or out of page tables.
136 *
137 * VM_FF_PGM_SYNC_CR3 is set by the hypervisor and all we need to
138 * do here is to execute the pending forced actions.
139 */
140 case VINF_PGM_SYNC_CR3:
141 AssertMsg(VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_PGM_SYNC_CR3 | VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL),
142 ("VINF_PGM_SYNC_CR3 and no VMCPU_FF_PGM_SYNC_CR3*!\n"));
143 rc = VINF_SUCCESS;
144 break;
145
146 /*
147 * PGM pool flush pending (guest SMP only).
148 */
149 /** @todo jumping back and forth between ring 0 and 3 can burn a lot of cycles
150 * if the EMT thread that's supposed to handle the flush is currently not active
151 * (e.g. waiting to be scheduled) -> fix this properly!
152 *
153 * bird: Since the clearing is global and done via a rendezvous any CPU can do
154 * it. They would have to choose who to call VMMR3EmtRendezvous and send
155 * the rest to VMMR3EmtRendezvousFF ... Hmm ... that's not going to work
156 * all that well since the latter will race the setup done by the
157 * first. Guess that means we need some new magic in that area for
158 * handling this case. :/
159 */
160 case VINF_PGM_POOL_FLUSH_PENDING:
161 rc = VINF_SUCCESS;
162 break;
163
164 /*
165 * Paging mode change.
166 */
167 case VINF_PGM_CHANGE_MODE:
168 rc = PGMChangeMode(pVCpu, pCtx->cr0, pCtx->cr4, pCtx->msrEFER);
169 if (rc == VINF_SUCCESS)
170 rc = VINF_EM_RESCHEDULE;
171 AssertMsg(RT_FAILURE(rc) || (rc >= VINF_EM_FIRST && rc <= VINF_EM_LAST), ("%Rrc\n", rc));
172 break;
173#endif /* !EMHANDLERC_WITH_NEM */
174
175#ifdef EMHANDLERC_WITH_PATM
176 /*
177 * CSAM wants to perform a task in ring-3. It has set an FF action flag.
178 */
179 case VINF_CSAM_PENDING_ACTION:
180 rc = VINF_SUCCESS;
181 break;
182
183 /*
184 * Invoked Interrupt gate - must directly (!) go to the recompiler.
185 */
186 case VINF_EM_RAW_INTERRUPT_PENDING:
187 case VINF_EM_RAW_RING_SWITCH_INT:
188 Assert(TRPMHasTrap(pVCpu));
189 Assert(!PATMIsPatchGCAddr(pVM, pCtx->eip));
190
191 if (TRPMHasTrap(pVCpu))
192 {
193 /* If the guest gate is marked unpatched, then we will check again if we can patch it. */
194 uint8_t u8Interrupt = TRPMGetTrapNo(pVCpu);
195 if (TRPMR3GetGuestTrapHandler(pVM, u8Interrupt) == TRPM_INVALID_HANDLER)
196 {
197 CSAMR3CheckGates(pVM, u8Interrupt, 1);
198 Log(("emR3RawHandleRC: recheck gate %x -> valid=%d\n", u8Interrupt, TRPMR3GetGuestTrapHandler(pVM, u8Interrupt) != TRPM_INVALID_HANDLER));
199 /* Note: If it was successful, then we could go back to raw mode, but let's keep things simple for now. */
200 }
201 }
202 rc = VINF_EM_RESCHEDULE_REM;
203 break;
204
205 /*
206 * Other ring switch types.
207 */
208 case VINF_EM_RAW_RING_SWITCH:
209 rc = emR3RawRingSwitch(pVM, pVCpu);
210 break;
211#endif /* EMHANDLERC_WITH_PATM */
212
213 /*
214 * I/O Port access - emulate the instruction.
215 */
216 case VINF_IOM_R3_IOPORT_READ:
217 case VINF_IOM_R3_IOPORT_WRITE:
218 rc = emR3ExecuteIOInstruction(pVM, pVCpu);
219 break;
220
221 /*
222 * Memory mapped I/O access - emulate the instruction.
223 */
224 case VINF_IOM_R3_MMIO_READ:
225 case VINF_IOM_R3_MMIO_WRITE:
226 case VINF_IOM_R3_MMIO_READ_WRITE:
227 rc = emR3ExecuteInstruction(pVM, pVCpu, "MMIO");
228 break;
229
230 /*
231 * Machine specific register access - emulate the instruction.
232 */
233 case VINF_CPUM_R3_MSR_READ:
234 case VINF_CPUM_R3_MSR_WRITE:
235 rc = emR3ExecuteInstruction(pVM, pVCpu, "MSR");
236 break;
237
238 /*
239 * GIM hypercall.
240 */
241 case VINF_GIM_R3_HYPERCALL:
242 {
243 /*
244 * Currently hypercall instruction (vmmcall) emulation is compiled and
245 * implemented only when nested hw. virt feature is enabled in IEM.
246 *
247 * On Intel or when nested hardware virtualization support isn't compiled
248 * we still need to implement hypercalls rather than throw a #UD.
249 */
250#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
251 if (pVM->cpum.ro.GuestFeatures.fSvm)
252 {
253 rc = emR3ExecuteInstruction(pVM, pVCpu, "Hypercall");
254 break;
255 }
256#endif
257 /** @todo IEM/REM need to handle VMCALL/VMMCALL, see
258 * @bugref{7270#c168}. */
259 uint8_t cbInstr = 0;
260 VBOXSTRICTRC rcStrict = GIMExecHypercallInstr(pVCpu, pCtx, &cbInstr);
261 if (rcStrict == VINF_SUCCESS)
262 {
263 Assert(cbInstr);
264 pCtx->rip += cbInstr;
265 /* Update interrupt inhibition. */
266 if ( VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS)
267 && pCtx->rip != EMGetInhibitInterruptsPC(pVCpu))
268 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS);
269 rc = VINF_SUCCESS;
270 }
271 else if (rcStrict == VINF_GIM_HYPERCALL_CONTINUING)
272 rc = VINF_SUCCESS;
273 else
274 {
275 Assert(rcStrict != VINF_GIM_R3_HYPERCALL);
276 rc = VBOXSTRICTRC_VAL(rcStrict);
277 }
278 break;
279 }
280
281#ifdef EMHANDLERC_WITH_HM
282 /*
283 * (MM)IO intensive code block detected; fall back to the recompiler for better performance
284 */
285 case VINF_EM_RAW_EMULATE_IO_BLOCK:
286 rc = HMR3EmulateIoBlock(pVM, pCtx);
287 break;
288
289 case VINF_EM_HM_PATCH_TPR_INSTR:
290 rc = HMR3PatchTprInstr(pVM, pVCpu, pCtx);
291 break;
292#endif
293
294#ifdef EMHANDLERC_WITH_PATM
295 /*
296 * Execute instruction.
297 */
298 case VINF_EM_RAW_EMULATE_INSTR_LDT_FAULT:
299 rc = emR3ExecuteInstruction(pVM, pVCpu, "LDT FAULT: ");
300 break;
301 case VINF_EM_RAW_EMULATE_INSTR_GDT_FAULT:
302 rc = emR3ExecuteInstruction(pVM, pVCpu, "GDT FAULT: ");
303 break;
304 case VINF_EM_RAW_EMULATE_INSTR_IDT_FAULT:
305 rc = emR3ExecuteInstruction(pVM, pVCpu, "IDT FAULT: ");
306 break;
307 case VINF_EM_RAW_EMULATE_INSTR_TSS_FAULT:
308 rc = emR3ExecuteInstruction(pVM, pVCpu, "TSS FAULT: ");
309 break;
310#endif
311
312#ifdef EMHANDLERC_WITH_PATM
313 case VINF_PATM_PENDING_IRQ_AFTER_IRET:
314 rc = emR3ExecuteInstruction(pVM, pVCpu, "EMUL: ", VINF_PATM_PENDING_IRQ_AFTER_IRET);
315 break;
316
317 case VINF_PATCH_EMULATE_INSTR:
318#else
319 case VINF_EM_RAW_GUEST_TRAP:
320#endif
321 case VINF_EM_RAW_EMULATE_INSTR:
322 rc = emR3ExecuteInstruction(pVM, pVCpu, "EMUL: ");
323 break;
324
325 case VINF_EM_RAW_INJECT_TRPM_EVENT:
326 rc = VBOXSTRICTRC_VAL(IEMInjectTrpmEvent(pVCpu));
327 /* The following condition should be removed when IEM_IMPLEMENTS_TASKSWITCH becomes true. */
328 if (rc == VERR_IEM_ASPECT_NOT_IMPLEMENTED)
329 rc = emR3ExecuteInstruction(pVM, pVCpu, "EVENT: ");
330 break;
331
332
333#ifdef EMHANDLERC_WITH_PATM
334 /*
335 * Stale selector and iret traps => REM.
336 */
337 case VINF_EM_RAW_STALE_SELECTOR:
338 case VINF_EM_RAW_IRET_TRAP:
339 /* We will not go to the recompiler if EIP points to patch code. */
340 if (PATMIsPatchGCAddr(pVM, pCtx->eip))
341 {
342 pCtx->eip = PATMR3PatchToGCPtr(pVM, (RTGCPTR)pCtx->eip, 0);
343 }
344 LogFlow(("emR3RawHandleRC: %Rrc -> %Rrc\n", rc, VINF_EM_RESCHEDULE_REM));
345 rc = VINF_EM_RESCHEDULE_REM;
346 break;
347
348 /*
349 * Conflict in GDT, resync and continue.
350 */
351 case VINF_SELM_SYNC_GDT:
352 AssertMsg(VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_SELM_SYNC_GDT | VMCPU_FF_SELM_SYNC_LDT | VMCPU_FF_SELM_SYNC_TSS),
353 ("VINF_SELM_SYNC_GDT without VMCPU_FF_SELM_SYNC_GDT/LDT/TSS!\n"));
354 rc = VINF_SUCCESS;
355 break;
356#endif
357
358 /*
359 * Up a level.
360 */
361 case VINF_EM_TERMINATE:
362 case VINF_EM_OFF:
363 case VINF_EM_RESET:
364 case VINF_EM_SUSPEND:
365 case VINF_EM_HALT:
366 case VINF_EM_RESUME:
367 case VINF_EM_NO_MEMORY:
368 case VINF_EM_RESCHEDULE:
369 case VINF_EM_RESCHEDULE_REM:
370 case VINF_EM_WAIT_SIPI:
371 break;
372
373 /*
374 * Up a level and invoke the debugger.
375 */
376 case VINF_EM_DBG_STEPPED:
377 case VINF_EM_DBG_BREAKPOINT:
378 case VINF_EM_DBG_STEP:
379 case VINF_EM_DBG_HYPER_BREAKPOINT:
380 case VINF_EM_DBG_HYPER_STEPPED:
381 case VINF_EM_DBG_HYPER_ASSERTION:
382 case VINF_EM_DBG_STOP:
383 case VINF_EM_DBG_EVENT:
384 break;
385
386 /*
387 * Up a level, dump and debug.
388 */
389 case VERR_TRPM_DONT_PANIC:
390 case VERR_TRPM_PANIC:
391 case VERR_VMM_RING0_ASSERTION:
392 case VINF_EM_TRIPLE_FAULT:
393 case VERR_VMM_HYPER_CR3_MISMATCH:
394 case VERR_VMM_RING3_CALL_DISABLED:
395 case VERR_IEM_INSTR_NOT_IMPLEMENTED:
396 case VERR_IEM_ASPECT_NOT_IMPLEMENTED:
397 case VERR_EM_GUEST_CPU_HANG:
398 break;
399
400#ifdef EMHANDLERC_WITH_HM
401 /*
402 * Up a level, after Hm have done some release logging.
403 */
404 case VERR_VMX_INVALID_VMCS_FIELD:
405 case VERR_VMX_INVALID_VMCS_PTR:
406 case VERR_VMX_INVALID_VMXON_PTR:
407 case VERR_VMX_UNEXPECTED_INTERRUPTION_EXIT_TYPE:
408 case VERR_VMX_UNEXPECTED_EXCEPTION:
409 case VERR_VMX_UNEXPECTED_EXIT:
410 case VERR_VMX_INVALID_GUEST_STATE:
411 case VERR_VMX_UNABLE_TO_START_VM:
412 case VERR_SVM_UNKNOWN_EXIT:
413 case VERR_SVM_UNEXPECTED_EXIT:
414 case VERR_SVM_UNEXPECTED_PATCH_TYPE:
415 case VERR_SVM_UNEXPECTED_XCPT_EXIT:
416 HMR3CheckError(pVM, rc);
417 break;
418
419 /* Up a level; fatal */
420 case VERR_VMX_IN_VMX_ROOT_MODE:
421 case VERR_SVM_IN_USE:
422 case VERR_SVM_UNABLE_TO_START_VM:
423 break;
424#endif
425
426 /*
427 * These two should be handled via the force flag already, but just in
428 * case they end up here deal with it.
429 */
430 case VINF_IOM_R3_IOPORT_COMMIT_WRITE:
431 case VINF_IOM_R3_MMIO_COMMIT_WRITE:
432 AssertFailed();
433 rc = VBOXSTRICTRC_TODO(IOMR3ProcessForceFlag(pVM, pVCpu, rc));
434 break;
435
436 /*
437 * Anything which is not known to us means an internal error
438 * and the termination of the VM!
439 */
440 default:
441 AssertMsgFailed(("Unknown GC return code: %Rra\n", rc));
442 break;
443 }
444 return rc;
445}
446
447#endif
448
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