EMHandleRCTmpl.h@ 42107

Last change on this file since 42107 was 41906, checked in by vboxsync, 13 years ago
CPUM: Combined the visible and hidden selector register data into one structure. Preparing for lazily resolving+caching of hidden registers in raw-mode.
Property svn:eol-style set to `native` Property svn:keywords set to `Author Date Id Revision`
File size: 12.1 KB

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1	/* $Id: EMHandleRCTmpl.h 41906 2012-06-24 15:44:03Z vboxsync $ */
2	/** @file
3	* EM - emR3[Raw\|Hwaccm]HandleRC template.
4	*/
5
6	/*
7	* Copyright (C) 2006-2009 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*/
17
18	#ifndef ___EMHandleRCTmpl_h
19	#define ___EMHandleRCTmpl_h
20
21	/**
22	* Process a subset of the raw-mode and hwaccm return codes.
23	*
24	* Since we have to share this with raw-mode single stepping, this inline
25	* function has been created to avoid code duplication.
26	*
27	* @returns VINF_SUCCESS if it's ok to continue raw mode.
28	* @returns VBox status code to return to the EM main loop.
29	*
30	* @param pVM Pointer to the VM.
31	* @param pVCpu Pointer to the VMCPU.
32	* @param rc The return code.
33	* @param pCtx Pointer to the guest CPU context.
34	*/
35	#ifdef EMHANDLERC_WITH_PATM
36	int emR3RawHandleRC(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx, int rc)
37	#elif defined(EMHANDLERC_WITH_HWACCM)
38	int emR3HwaccmHandleRC(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx, int rc)
39	#endif
40	{
41	switch (rc)
42	{
43	/*
44	* Common & simple ones.
45	*/
46	case VINF_SUCCESS:
47	break;
48	case VINF_EM_RESCHEDULE_RAW:
49	case VINF_EM_RESCHEDULE_HWACC:
50	case VINF_EM_RAW_INTERRUPT:
51	case VINF_EM_RAW_TO_R3:
52	case VINF_EM_RAW_TIMER_PENDING:
53	case VINF_EM_PENDING_REQUEST:
54	rc = VINF_SUCCESS;
55	break;
56
57	#ifdef EMHANDLERC_WITH_PATM
58	/*
59	* Privileged instruction.
60	*/
61	case VINF_EM_RAW_EXCEPTION_PRIVILEGED:
62	case VINF_PATM_PATCH_TRAP_GP:
63	rc = emR3RawPrivileged(pVM, pVCpu);
64	break;
65
66	case VINF_EM_RAW_GUEST_TRAP:
67	/*
68	* Got a trap which needs dispatching.
69	*/
70	if (PATMR3IsInsidePatchJump(pVM, pCtx->eip, NULL))
71	{
72	AssertReleaseMsgFailed(("FATAL ERROR: executing random instruction inside generated patch jump %08X\n", CPUMGetGuestEIP(pVCpu)));
73	rc = VERR_EM_RAW_PATCH_CONFLICT;
74	break;
75	}
76	rc = emR3RawGuestTrap(pVM, pVCpu);
77	break;
78
79	/*
80	* Trap in patch code.
81	*/
82	case VINF_PATM_PATCH_TRAP_PF:
83	case VINF_PATM_PATCH_INT3:
84	rc = emR3PatchTrap(pVM, pVCpu, pCtx, rc);
85	break;
86
87	case VINF_PATM_DUPLICATE_FUNCTION:
88	Assert(PATMIsPatchGCAddr(pVM, pCtx->eip));
89	rc = PATMR3DuplicateFunctionRequest(pVM, pCtx);
90	AssertRC(rc);
91	rc = VINF_SUCCESS;
92	break;
93
94	case VINF_PATM_CHECK_PATCH_PAGE:
95	rc = PATMR3HandleMonitoredPage(pVM);
96	AssertRC(rc);
97	rc = VINF_SUCCESS;
98	break;
99
100	/*
101	* Patch manager.
102	*/
103	case VERR_EM_RAW_PATCH_CONFLICT:
104	AssertReleaseMsgFailed(("%Rrc handling is not yet implemented\n", rc));
105	break;
106	#endif /* EMHANDLERC_WITH_PATM */
107
108	#ifdef EMHANDLERC_WITH_PATM
109	/*
110	* Memory mapped I/O access - attempt to patch the instruction
111	*/
112	case VINF_PATM_HC_MMIO_PATCH_READ:
113	rc = PATMR3InstallPatch(pVM, SELMToFlat(pVM, DISSELREG_CS, CPUMCTX2CORE(pCtx), pCtx->eip),
114	PATMFL_MMIO_ACCESS
115	\| ( SELMGetCpuModeFromSelector(pVCpu, pCtx->eflags, pCtx->cs.Sel, &pCtx->cs)
116	== DISCPUMODE_32BIT ? PATMFL_CODE32 : 0));
117	if (RT_FAILURE(rc))
118	rc = emR3ExecuteInstruction(pVM, pVCpu, "MMIO");
119	break;
120
121	case VINF_PATM_HC_MMIO_PATCH_WRITE:
122	AssertFailed(); /* not yet implemented. */
123	rc = emR3ExecuteInstruction(pVM, pVCpu, "MMIO");
124	break;
125	#endif /* EMHANDLERC_WITH_PATM */
126
127	/*
128	* Conflict or out of page tables.
129	*
130	* VM_FF_PGM_SYNC_CR3 is set by the hypervisor and all we need to
131	* do here is to execute the pending forced actions.
132	*/
133	case VINF_PGM_SYNC_CR3:
134	AssertMsg(VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_PGM_SYNC_CR3 \| VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL),
135	("VINF_PGM_SYNC_CR3 and no VMCPU_FF_PGM_SYNC_CR3*!\n"));
136	rc = VINF_SUCCESS;
137	break;
138
139	/*
140	* PGM pool flush pending (guest SMP only).
141	*/
142	/** @todo jumping back and forth between ring 0 and 3 can burn a lot of cycles
143	* if the EMT thread that's supposed to handle the flush is currently not active
144	* (e.g. waiting to be scheduled) -> fix this properly!
145	*
146	* bird: Since the clearing is global and done via a rendezvous any CPU can do
147	* it. They would have to choose who to call VMMR3EmtRendezvous and send
148	* the rest to VMMR3EmtRendezvousFF ... Hmm ... that's not going to work
149	* all that well since the latter will race the setup done by the
150	* first. Guess that means we need some new magic in that area for
151	* handling this case. :/
152	*/
153	case VINF_PGM_POOL_FLUSH_PENDING:
154	rc = VINF_SUCCESS;
155	break;
156
157	/*
158	* Paging mode change.
159	*/
160	case VINF_PGM_CHANGE_MODE:
161	rc = PGMChangeMode(pVCpu, pCtx->cr0, pCtx->cr4, pCtx->msrEFER);
162	if (rc == VINF_SUCCESS)
163	rc = VINF_EM_RESCHEDULE;
164	AssertMsg(RT_FAILURE(rc) \|\| (rc >= VINF_EM_FIRST && rc <= VINF_EM_LAST), ("%Rrc\n", rc));
165	break;
166
167	#ifdef EMHANDLERC_WITH_PATM
168	/*
169	* CSAM wants to perform a task in ring-3. It has set an FF action flag.
170	*/
171	case VINF_CSAM_PENDING_ACTION:
172	rc = VINF_SUCCESS;
173	break;
174
175	/*
176	* Invoked Interrupt gate - must directly (!) go to the recompiler.
177	*/
178	case VINF_EM_RAW_INTERRUPT_PENDING:
179	case VINF_EM_RAW_RING_SWITCH_INT:
180	Assert(TRPMHasTrap(pVCpu));
181	Assert(!PATMIsPatchGCAddr(pVM, pCtx->eip));
182
183	if (TRPMHasTrap(pVCpu))
184	{
185	/* If the guest gate is marked unpatched, then we will check again if we can patch it. */
186	uint8_t u8Interrupt = TRPMGetTrapNo(pVCpu);
187	if (TRPMR3GetGuestTrapHandler(pVM, u8Interrupt) == TRPM_INVALID_HANDLER)
188	{
189	CSAMR3CheckGates(pVM, u8Interrupt, 1);
190	Log(("emR3RawHandleRC: recheck gate %x -> valid=%d\n", u8Interrupt, TRPMR3GetGuestTrapHandler(pVM, u8Interrupt) != TRPM_INVALID_HANDLER));
191	/* Note: If it was successful, then we could go back to raw mode, but let's keep things simple for now. */
192	}
193	}
194	rc = VINF_EM_RESCHEDULE_REM;
195	break;
196
197	/*
198	* Other ring switch types.
199	*/
200	case VINF_EM_RAW_RING_SWITCH:
201	rc = emR3RawRingSwitch(pVM, pVCpu);
202	break;
203	#endif /* EMHANDLERC_WITH_PATM */
204
205	/*
206	* I/O Port access - emulate the instruction.
207	*/
208	case VINF_IOM_R3_IOPORT_READ:
209	case VINF_IOM_R3_IOPORT_WRITE:
210	rc = emR3ExecuteIOInstruction(pVM, pVCpu);
211	break;
212
213	/*
214	* Memory mapped I/O access - emulate the instruction.
215	*/
216	case VINF_IOM_R3_MMIO_READ:
217	case VINF_IOM_R3_MMIO_WRITE:
218	case VINF_IOM_R3_MMIO_READ_WRITE:
219	rc = emR3ExecuteInstruction(pVM, pVCpu, "MMIO");
220	break;
221
222	#ifdef EMHANDLERC_WITH_HWACCM
223	/*
224	* (MM)IO intensive code block detected; fall back to the recompiler for better performance
225	*/
226	case VINF_EM_RAW_EMULATE_IO_BLOCK:
227	rc = HWACCMR3EmulateIoBlock(pVM, pCtx);
228	break;
229
230	case VINF_EM_HWACCM_PATCH_TPR_INSTR:
231	rc = HWACCMR3PatchTprInstr(pVM, pVCpu, pCtx);
232	break;
233	#endif
234
235	#ifdef EMHANDLERC_WITH_PATM
236	/*
237	* Execute instruction.
238	*/
239	case VINF_EM_RAW_EMULATE_INSTR_LDT_FAULT:
240	rc = emR3ExecuteInstruction(pVM, pVCpu, "LDT FAULT: ");
241	break;
242	case VINF_EM_RAW_EMULATE_INSTR_GDT_FAULT:
243	rc = emR3ExecuteInstruction(pVM, pVCpu, "GDT FAULT: ");
244	break;
245	case VINF_EM_RAW_EMULATE_INSTR_IDT_FAULT:
246	rc = emR3ExecuteInstruction(pVM, pVCpu, "IDT FAULT: ");
247	break;
248	case VINF_EM_RAW_EMULATE_INSTR_TSS_FAULT:
249	rc = emR3ExecuteInstruction(pVM, pVCpu, "TSS FAULT: ");
250	break;
251	case VINF_EM_RAW_EMULATE_INSTR_PD_FAULT:
252	rc = emR3ExecuteInstruction(pVM, pVCpu, "PD FAULT: ");
253	break;
254	case VINF_EM_RAW_EMULATE_INSTR_HLT:
255	/** @todo skip instruction and go directly to the halt state. (see REM for implementation details) */
256	rc = emR3RawPrivileged(pVM, pVCpu);
257	break;
258	#endif
259
260	#ifdef EMHANDLERC_WITH_PATM
261	case VINF_PATM_PENDING_IRQ_AFTER_IRET:
262	rc = emR3ExecuteInstruction(pVM, pVCpu, "EMUL: ", VINF_PATM_PENDING_IRQ_AFTER_IRET);
263	break;
264
265	case VINF_PATCH_EMULATE_INSTR:
266	#else
267	case VINF_EM_RAW_GUEST_TRAP:
268	#endif
269	case VINF_EM_RAW_EMULATE_INSTR:
270	rc = emR3ExecuteInstruction(pVM, pVCpu, "EMUL: ");
271	break;
272
273	#ifdef EMHANDLERC_WITH_PATM
274	/*
275	* Stale selector and iret traps => REM.
276	*/
277	case VINF_EM_RAW_STALE_SELECTOR:
278	case VINF_EM_RAW_IRET_TRAP:
279	/* We will not go to the recompiler if EIP points to patch code. */
280	if (PATMIsPatchGCAddr(pVM, pCtx->eip))
281	{
282	pCtx->eip = PATMR3PatchToGCPtr(pVM, (RTGCPTR)pCtx->eip, 0);
283	}
284	LogFlow(("emR3RawHandleRC: %Rrc -> %Rrc\n", rc, VINF_EM_RESCHEDULE_REM));
285	rc = VINF_EM_RESCHEDULE_REM;
286	break;
287	#endif
288
289	/*
290	* Up a level.
291	*/
292	case VINF_EM_TERMINATE:
293	case VINF_EM_OFF:
294	case VINF_EM_RESET:
295	case VINF_EM_SUSPEND:
296	case VINF_EM_HALT:
297	case VINF_EM_RESUME:
298	case VINF_EM_NO_MEMORY:
299	case VINF_EM_RESCHEDULE:
300	case VINF_EM_RESCHEDULE_REM:
301	case VINF_EM_WAIT_SIPI:
302	break;
303
304	/*
305	* Up a level and invoke the debugger.
306	*/
307	case VINF_EM_DBG_STEPPED:
308	case VINF_EM_DBG_BREAKPOINT:
309	case VINF_EM_DBG_STEP:
310	case VINF_EM_DBG_HYPER_BREAKPOINT:
311	case VINF_EM_DBG_HYPER_STEPPED:
312	case VINF_EM_DBG_HYPER_ASSERTION:
313	case VINF_EM_DBG_STOP:
314	break;
315
316	/*
317	* Up a level, dump and debug.
318	*/
319	case VERR_TRPM_DONT_PANIC:
320	case VERR_TRPM_PANIC:
321	case VERR_VMM_RING0_ASSERTION:
322	case VERR_VMM_HYPER_CR3_MISMATCH:
323	case VERR_VMM_RING3_CALL_DISABLED:
324	case VERR_IEM_INSTR_NOT_IMPLEMENTED:
325	case VERR_IEM_ASPECT_NOT_IMPLEMENTED:
326	break;
327
328	#ifdef EMHANDLERC_WITH_HWACCM
329	/*
330	* Up a level, after HwAccM have done some release logging.
331	*/
332	case VERR_VMX_INVALID_VMCS_FIELD:
333	case VERR_VMX_INVALID_VMCS_PTR:
334	case VERR_VMX_INVALID_VMXON_PTR:
335	case VERR_VMX_UNEXPECTED_INTERRUPTION_EXIT_CODE:
336	case VERR_VMX_UNEXPECTED_EXCEPTION:
337	case VERR_VMX_UNEXPECTED_EXIT_CODE:
338	case VERR_VMX_INVALID_GUEST_STATE:
339	case VERR_VMX_UNABLE_TO_START_VM:
340	case VERR_VMX_UNABLE_TO_RESUME_VM:
341	HWACCMR3CheckError(pVM, rc);
342	break;
343
344	/* Up a level; fatal */
345	case VERR_VMX_IN_VMX_ROOT_MODE:
346	case VERR_SVM_IN_USE:
347	case VERR_SVM_UNABLE_TO_START_VM:
348	break;
349	#endif
350
351	/*
352	* Anything which is not known to us means an internal error
353	* and the termination of the VM!
354	*/
355	default:
356	AssertMsgFailed(("Unknown GC return code: %Rra\n", rc));
357	break;
358	}
359	return rc;
360	}
361
362	#endif
363

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source: vbox/trunk/src/VBox/VMM/include/EMHandleRCTmpl.h@ 42107

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