EMHandleRCTmpl.h@ 61703

Last change on this file since 61703 was 61544, checked in by vboxsync, 8 years ago
VMM/GIM: Fix up hypercall rc handling and also a bug while disassembling hypercalls. IEM/REM being able to handle VMCALL/VMMCALL to hook into GIM is still a todo but this change temporarily works around by adding new GIM and GIM provider interfaces to kinda do the same work. The Xcpt handlers were not re-used as they check for whether or not the provider requested UD trapping in the first place.
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1	/* $Id: EMHandleRCTmpl.h 61544 2016-06-07 14:42:20Z vboxsync $ */
2	/** @file
3	* EM - emR3[Raw\|Hm]HandleRC template.
4	*/
5
6	/*
7	* Copyright (C) 2006-2015 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*/
17
18	#ifndef ___EMHandleRCTmpl_h
19	#define ___EMHandleRCTmpl_h
20
21	#if defined(EMHANDLERC_WITH_PATM) && defined(EMHANDLERC_WITH_HM)
22	# error "Only one define"
23	#endif
24
25
26	/**
27	* Process a subset of the raw-mode and hm return codes.
28	*
29	* Since we have to share this with raw-mode single stepping, this inline
30	* function has been created to avoid code duplication.
31	*
32	* @returns VINF_SUCCESS if it's ok to continue raw mode.
33	* @returns VBox status code to return to the EM main loop.
34	*
35	* @param pVM The cross context VM structure.
36	* @param pVCpu The cross context virtual CPU structure.
37	* @param pCtx Pointer to the guest CPU context.
38	* @param rc The return code.
39	*/
40	#ifdef EMHANDLERC_WITH_PATM
41	int emR3RawHandleRC(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx, int rc)
42	#elif defined(EMHANDLERC_WITH_HM) \|\| defined(DOXYGEN_RUNNING)
43	int emR3HmHandleRC(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx, int rc)
44	#endif
45	{
46	switch (rc)
47	{
48	/*
49	* Common & simple ones.
50	*/
51	case VINF_SUCCESS:
52	break;
53	case VINF_EM_RESCHEDULE_RAW:
54	case VINF_EM_RESCHEDULE_HM:
55	case VINF_EM_RAW_INTERRUPT:
56	case VINF_EM_RAW_TO_R3:
57	case VINF_EM_RAW_TIMER_PENDING:
58	case VINF_EM_PENDING_REQUEST:
59	rc = VINF_SUCCESS;
60	break;
61
62	#ifdef EMHANDLERC_WITH_PATM
63	/*
64	* Privileged instruction.
65	*/
66	case VINF_EM_RAW_EXCEPTION_PRIVILEGED:
67	case VINF_PATM_PATCH_TRAP_GP:
68	rc = emR3RawPrivileged(pVM, pVCpu);
69	break;
70
71	case VINF_EM_RAW_GUEST_TRAP:
72	/*
73	* Got a trap which needs dispatching.
74	*/
75	if (PATMR3IsInsidePatchJump(pVM, pCtx->eip, NULL))
76	{
77	AssertReleaseMsgFailed(("FATAL ERROR: executing random instruction inside generated patch jump %08X\n", CPUMGetGuestEIP(pVCpu)));
78	rc = VERR_EM_RAW_PATCH_CONFLICT;
79	break;
80	}
81	rc = emR3RawGuestTrap(pVM, pVCpu);
82	break;
83
84	/*
85	* Trap in patch code.
86	*/
87	case VINF_PATM_PATCH_TRAP_PF:
88	case VINF_PATM_PATCH_INT3:
89	rc = emR3RawPatchTrap(pVM, pVCpu, pCtx, rc);
90	break;
91
92	case VINF_PATM_DUPLICATE_FUNCTION:
93	Assert(PATMIsPatchGCAddr(pVM, pCtx->eip));
94	rc = PATMR3DuplicateFunctionRequest(pVM, pCtx);
95	AssertRC(rc);
96	rc = VINF_SUCCESS;
97	break;
98
99	case VINF_PATM_CHECK_PATCH_PAGE:
100	rc = PATMR3HandleMonitoredPage(pVM);
101	AssertRC(rc);
102	rc = VINF_SUCCESS;
103	break;
104
105	/*
106	* Patch manager.
107	*/
108	case VERR_EM_RAW_PATCH_CONFLICT:
109	AssertReleaseMsgFailed(("%Rrc handling is not yet implemented\n", rc));
110	break;
111	#endif /* EMHANDLERC_WITH_PATM */
112
113	#ifdef EMHANDLERC_WITH_PATM
114	/*
115	* Memory mapped I/O access - attempt to patch the instruction
116	*/
117	case VINF_PATM_HC_MMIO_PATCH_READ:
118	rc = PATMR3InstallPatch(pVM, SELMToFlat(pVM, DISSELREG_CS, CPUMCTX2CORE(pCtx), pCtx->eip),
119	PATMFL_MMIO_ACCESS
120	\| (CPUMGetGuestCodeBits(pVCpu) == 32 ? PATMFL_CODE32 : 0));
121	if (RT_FAILURE(rc))
122	rc = emR3ExecuteInstruction(pVM, pVCpu, "MMIO");
123	break;
124
125	case VINF_PATM_HC_MMIO_PATCH_WRITE:
126	AssertFailed(); /* not yet implemented. */
127	rc = emR3ExecuteInstruction(pVM, pVCpu, "MMIO");
128	break;
129	#endif /* EMHANDLERC_WITH_PATM */
130
131	/*
132	* Conflict or out of page tables.
133	*
134	* VM_FF_PGM_SYNC_CR3 is set by the hypervisor and all we need to
135	* do here is to execute the pending forced actions.
136	*/
137	case VINF_PGM_SYNC_CR3:
138	AssertMsg(VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_PGM_SYNC_CR3 \| VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL),
139	("VINF_PGM_SYNC_CR3 and no VMCPU_FF_PGM_SYNC_CR3*!\n"));
140	rc = VINF_SUCCESS;
141	break;
142
143	/*
144	* PGM pool flush pending (guest SMP only).
145	*/
146	/** @todo jumping back and forth between ring 0 and 3 can burn a lot of cycles
147	* if the EMT thread that's supposed to handle the flush is currently not active
148	* (e.g. waiting to be scheduled) -> fix this properly!
149	*
150	* bird: Since the clearing is global and done via a rendezvous any CPU can do
151	* it. They would have to choose who to call VMMR3EmtRendezvous and send
152	* the rest to VMMR3EmtRendezvousFF ... Hmm ... that's not going to work
153	* all that well since the latter will race the setup done by the
154	* first. Guess that means we need some new magic in that area for
155	* handling this case. :/
156	*/
157	case VINF_PGM_POOL_FLUSH_PENDING:
158	rc = VINF_SUCCESS;
159	break;
160
161	/*
162	* Paging mode change.
163	*/
164	case VINF_PGM_CHANGE_MODE:
165	rc = PGMChangeMode(pVCpu, pCtx->cr0, pCtx->cr4, pCtx->msrEFER);
166	if (rc == VINF_SUCCESS)
167	rc = VINF_EM_RESCHEDULE;
168	AssertMsg(RT_FAILURE(rc) \|\| (rc >= VINF_EM_FIRST && rc <= VINF_EM_LAST), ("%Rrc\n", rc));
169	break;
170
171	#ifdef EMHANDLERC_WITH_PATM
172	/*
173	* CSAM wants to perform a task in ring-3. It has set an FF action flag.
174	*/
175	case VINF_CSAM_PENDING_ACTION:
176	rc = VINF_SUCCESS;
177	break;
178
179	/*
180	* Invoked Interrupt gate - must directly (!) go to the recompiler.
181	*/
182	case VINF_EM_RAW_INTERRUPT_PENDING:
183	case VINF_EM_RAW_RING_SWITCH_INT:
184	Assert(TRPMHasTrap(pVCpu));
185	Assert(!PATMIsPatchGCAddr(pVM, pCtx->eip));
186
187	if (TRPMHasTrap(pVCpu))
188	{
189	/* If the guest gate is marked unpatched, then we will check again if we can patch it. */
190	uint8_t u8Interrupt = TRPMGetTrapNo(pVCpu);
191	if (TRPMR3GetGuestTrapHandler(pVM, u8Interrupt) == TRPM_INVALID_HANDLER)
192	{
193	CSAMR3CheckGates(pVM, u8Interrupt, 1);
194	Log(("emR3RawHandleRC: recheck gate %x -> valid=%d\n", u8Interrupt, TRPMR3GetGuestTrapHandler(pVM, u8Interrupt) != TRPM_INVALID_HANDLER));
195	/* Note: If it was successful, then we could go back to raw mode, but let's keep things simple for now. */
196	}
197	}
198	rc = VINF_EM_RESCHEDULE_REM;
199	break;
200
201	/*
202	* Other ring switch types.
203	*/
204	case VINF_EM_RAW_RING_SWITCH:
205	rc = emR3RawRingSwitch(pVM, pVCpu);
206	break;
207	#endif /* EMHANDLERC_WITH_PATM */
208
209	/*
210	* I/O Port access - emulate the instruction.
211	*/
212	case VINF_IOM_R3_IOPORT_READ:
213	case VINF_IOM_R3_IOPORT_WRITE:
214	rc = emR3ExecuteIOInstruction(pVM, pVCpu);
215	break;
216
217	/*
218	* Memory mapped I/O access - emulate the instruction.
219	*/
220	case VINF_IOM_R3_MMIO_READ:
221	case VINF_IOM_R3_MMIO_WRITE:
222	case VINF_IOM_R3_MMIO_READ_WRITE:
223	rc = emR3ExecuteInstruction(pVM, pVCpu, "MMIO");
224	break;
225
226	/*
227	* Machine specific register access - emulate the instruction.
228	*/
229	case VINF_CPUM_R3_MSR_READ:
230	case VINF_CPUM_R3_MSR_WRITE:
231	rc = emR3ExecuteInstruction(pVM, pVCpu, "MSR");
232	break;
233
234	/*
235	* GIM hypercall.
236	*/
237	case VINF_GIM_R3_HYPERCALL:
238	{
239	/** @todo IEM/REM need to handle VMCALL/VMMCALL, see
240	* @bugref{7270#c168}. */
241	uint8_t cbInstr = 0;
242	VBOXSTRICTRC rcStrict = GIMExecHypercallInstr(pVCpu, pCtx, &cbInstr);
243	if (rcStrict == VINF_SUCCESS)
244	{
245	Assert(cbInstr);
246	pCtx->rip += cbInstr;
247	/* Update interrupt inhibition. */
248	if ( VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS)
249	&& pCtx->rip != EMGetInhibitInterruptsPC(pVCpu))
250	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS);
251	rc = VINF_SUCCESS;
252	}
253	else if (rcStrict == VINF_GIM_HYPERCALL_CONTINUING)
254	rc = VINF_SUCCESS;
255	else
256	{
257	Assert(rcStrict != VINF_GIM_R3_HYPERCALL);
258	rc = VBOXSTRICTRC_VAL(rcStrict);
259	}
260	break;
261	}
262
263	#ifdef EMHANDLERC_WITH_HM
264	/*
265	* (MM)IO intensive code block detected; fall back to the recompiler for better performance
266	*/
267	case VINF_EM_RAW_EMULATE_IO_BLOCK:
268	rc = HMR3EmulateIoBlock(pVM, pCtx);
269	break;
270
271	case VINF_EM_HM_PATCH_TPR_INSTR:
272	rc = HMR3PatchTprInstr(pVM, pVCpu, pCtx);
273	break;
274	#endif
275
276	#ifdef EMHANDLERC_WITH_PATM
277	/*
278	* Execute instruction.
279	*/
280	case VINF_EM_RAW_EMULATE_INSTR_LDT_FAULT:
281	rc = emR3ExecuteInstruction(pVM, pVCpu, "LDT FAULT: ");
282	break;
283	case VINF_EM_RAW_EMULATE_INSTR_GDT_FAULT:
284	rc = emR3ExecuteInstruction(pVM, pVCpu, "GDT FAULT: ");
285	break;
286	case VINF_EM_RAW_EMULATE_INSTR_IDT_FAULT:
287	rc = emR3ExecuteInstruction(pVM, pVCpu, "IDT FAULT: ");
288	break;
289	case VINF_EM_RAW_EMULATE_INSTR_TSS_FAULT:
290	rc = emR3ExecuteInstruction(pVM, pVCpu, "TSS FAULT: ");
291	break;
292	#endif
293
294	#ifdef EMHANDLERC_WITH_PATM
295	case VINF_PATM_PENDING_IRQ_AFTER_IRET:
296	rc = emR3ExecuteInstruction(pVM, pVCpu, "EMUL: ", VINF_PATM_PENDING_IRQ_AFTER_IRET);
297	break;
298
299	case VINF_PATCH_EMULATE_INSTR:
300	#else
301	case VINF_EM_RAW_GUEST_TRAP:
302	#endif
303	case VINF_EM_RAW_EMULATE_INSTR:
304	rc = emR3ExecuteInstruction(pVM, pVCpu, "EMUL: ");
305	break;
306
307	case VINF_EM_RAW_INJECT_TRPM_EVENT:
308	rc = VBOXSTRICTRC_VAL(IEMInjectTrpmEvent(pVCpu));
309	/* The following condition should be removed when IEM_IMPLEMENTS_TASKSWITCH becomes true. */
310	if (rc == VERR_IEM_ASPECT_NOT_IMPLEMENTED)
311	rc = emR3ExecuteInstruction(pVM, pVCpu, "EVENT: ");
312	break;
313
314
315	#ifdef EMHANDLERC_WITH_PATM
316	/*
317	* Stale selector and iret traps => REM.
318	*/
319	case VINF_EM_RAW_STALE_SELECTOR:
320	case VINF_EM_RAW_IRET_TRAP:
321	/* We will not go to the recompiler if EIP points to patch code. */
322	if (PATMIsPatchGCAddr(pVM, pCtx->eip))
323	{
324	pCtx->eip = PATMR3PatchToGCPtr(pVM, (RTGCPTR)pCtx->eip, 0);
325	}
326	LogFlow(("emR3RawHandleRC: %Rrc -> %Rrc\n", rc, VINF_EM_RESCHEDULE_REM));
327	rc = VINF_EM_RESCHEDULE_REM;
328	break;
329
330	/*
331	* Conflict in GDT, resync and continue.
332	*/
333	case VINF_SELM_SYNC_GDT:
334	AssertMsg(VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_SELM_SYNC_GDT \| VMCPU_FF_SELM_SYNC_LDT \| VMCPU_FF_SELM_SYNC_TSS),
335	("VINF_SELM_SYNC_GDT without VMCPU_FF_SELM_SYNC_GDT/LDT/TSS!\n"));
336	rc = VINF_SUCCESS;
337	break;
338	#endif
339
340	/*
341	* Up a level.
342	*/
343	case VINF_EM_TERMINATE:
344	case VINF_EM_OFF:
345	case VINF_EM_RESET:
346	case VINF_EM_SUSPEND:
347	case VINF_EM_HALT:
348	case VINF_EM_RESUME:
349	case VINF_EM_NO_MEMORY:
350	case VINF_EM_RESCHEDULE:
351	case VINF_EM_RESCHEDULE_REM:
352	case VINF_EM_WAIT_SIPI:
353	break;
354
355	/*
356	* Up a level and invoke the debugger.
357	*/
358	case VINF_EM_DBG_STEPPED:
359	case VINF_EM_DBG_BREAKPOINT:
360	case VINF_EM_DBG_STEP:
361	case VINF_EM_DBG_HYPER_BREAKPOINT:
362	case VINF_EM_DBG_HYPER_STEPPED:
363	case VINF_EM_DBG_HYPER_ASSERTION:
364	case VINF_EM_DBG_STOP:
365	case VINF_EM_DBG_EVENT:
366	break;
367
368	/*
369	* Up a level, dump and debug.
370	*/
371	case VERR_TRPM_DONT_PANIC:
372	case VERR_TRPM_PANIC:
373	case VERR_VMM_RING0_ASSERTION:
374	case VINF_EM_TRIPLE_FAULT:
375	case VERR_VMM_HYPER_CR3_MISMATCH:
376	case VERR_VMM_RING3_CALL_DISABLED:
377	case VERR_IEM_INSTR_NOT_IMPLEMENTED:
378	case VERR_IEM_ASPECT_NOT_IMPLEMENTED:
379	case VERR_EM_GUEST_CPU_HANG:
380	break;
381
382	#ifdef EMHANDLERC_WITH_HM
383	/*
384	* Up a level, after Hm have done some release logging.
385	*/
386	case VERR_VMX_INVALID_VMCS_FIELD:
387	case VERR_VMX_INVALID_VMCS_PTR:
388	case VERR_VMX_INVALID_VMXON_PTR:
389	case VERR_VMX_UNEXPECTED_INTERRUPTION_EXIT_TYPE:
390	case VERR_VMX_UNEXPECTED_EXCEPTION:
391	case VERR_VMX_UNEXPECTED_EXIT:
392	case VERR_VMX_INVALID_GUEST_STATE:
393	case VERR_VMX_UNABLE_TO_START_VM:
394	case VERR_SVM_UNKNOWN_EXIT:
395	case VERR_SVM_UNEXPECTED_EXIT:
396	case VERR_SVM_UNEXPECTED_PATCH_TYPE:
397	case VERR_SVM_UNEXPECTED_XCPT_EXIT:
398	HMR3CheckError(pVM, rc);
399	break;
400
401	/* Up a level; fatal */
402	case VERR_VMX_IN_VMX_ROOT_MODE:
403	case VERR_SVM_IN_USE:
404	case VERR_SVM_UNABLE_TO_START_VM:
405	break;
406	#endif
407
408	/*
409	* These two should be handled via the force flag already, but just in
410	* case they end up here deal with it.
411	*/
412	case VINF_IOM_R3_IOPORT_COMMIT_WRITE:
413	case VINF_IOM_R3_MMIO_COMMIT_WRITE:
414	AssertFailed();
415	rc = VBOXSTRICTRC_TODO(IOMR3ProcessForceFlag(pVM, pVCpu, rc));
416	break;
417
418	/*
419	* Anything which is not known to us means an internal error
420	* and the termination of the VM!
421	*/
422	default:
423	AssertMsgFailed(("Unknown GC return code: %Rra\n", rc));
424	break;
425	}
426	return rc;
427	}
428
429	#endif
430

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source: vbox/trunk/src/VBox/VMM/include/EMHandleRCTmpl.h@ 61703

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