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source: vbox/trunk/src/VBox/VMM/include/EMHandleRCTmpl.h@ 69111

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1/* $Id: EMHandleRCTmpl.h 69111 2017-10-17 14:26:02Z vboxsync $ */
2/** @file
3 * EM - emR3[Raw|Hm]HandleRC template.
4 */
5
6/*
7 * Copyright (C) 2006-2017 Oracle Corporation
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 */
17
18#ifndef ___EMHandleRCTmpl_h
19#define ___EMHandleRCTmpl_h
20
21#if defined(EMHANDLERC_WITH_PATM) && defined(EMHANDLERC_WITH_HM)
22# error "Only one define"
23#endif
24
25
26/**
27 * Process a subset of the raw-mode and hm return codes.
28 *
29 * Since we have to share this with raw-mode single stepping, this inline
30 * function has been created to avoid code duplication.
31 *
32 * @returns VINF_SUCCESS if it's ok to continue raw mode.
33 * @returns VBox status code to return to the EM main loop.
34 *
35 * @param pVM The cross context VM structure.
36 * @param pVCpu The cross context virtual CPU structure.
37 * @param pCtx Pointer to the guest CPU context.
38 * @param rc The return code.
39 */
40#ifdef EMHANDLERC_WITH_PATM
41int emR3RawHandleRC(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx, int rc)
42#elif defined(EMHANDLERC_WITH_HM) || defined(DOXYGEN_RUNNING)
43int emR3HmHandleRC(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx, int rc)
44#endif
45{
46 switch (rc)
47 {
48 /*
49 * Common & simple ones.
50 */
51 case VINF_SUCCESS:
52 break;
53 case VINF_EM_RESCHEDULE_RAW:
54 case VINF_EM_RESCHEDULE_HM:
55 case VINF_EM_RAW_INTERRUPT:
56 case VINF_EM_RAW_TO_R3:
57 case VINF_EM_RAW_TIMER_PENDING:
58 case VINF_EM_PENDING_REQUEST:
59 rc = VINF_SUCCESS;
60 break;
61
62#ifdef EMHANDLERC_WITH_PATM
63 /*
64 * Privileged instruction.
65 */
66 case VINF_EM_RAW_EXCEPTION_PRIVILEGED:
67 case VINF_PATM_PATCH_TRAP_GP:
68 rc = emR3RawPrivileged(pVM, pVCpu);
69 break;
70
71 case VINF_EM_RAW_GUEST_TRAP:
72 /*
73 * Got a trap which needs dispatching.
74 */
75 if (PATMR3IsInsidePatchJump(pVM, pCtx->eip, NULL))
76 {
77 AssertReleaseMsgFailed(("FATAL ERROR: executing random instruction inside generated patch jump %08X\n", CPUMGetGuestEIP(pVCpu)));
78 rc = VERR_EM_RAW_PATCH_CONFLICT;
79 break;
80 }
81 rc = emR3RawGuestTrap(pVM, pVCpu);
82 break;
83
84 /*
85 * Trap in patch code.
86 */
87 case VINF_PATM_PATCH_TRAP_PF:
88 case VINF_PATM_PATCH_INT3:
89 rc = emR3RawPatchTrap(pVM, pVCpu, pCtx, rc);
90 break;
91
92 case VINF_PATM_DUPLICATE_FUNCTION:
93 Assert(PATMIsPatchGCAddr(pVM, pCtx->eip));
94 rc = PATMR3DuplicateFunctionRequest(pVM, pCtx);
95 AssertRC(rc);
96 rc = VINF_SUCCESS;
97 break;
98
99 case VINF_PATM_CHECK_PATCH_PAGE:
100 rc = PATMR3HandleMonitoredPage(pVM);
101 AssertRC(rc);
102 rc = VINF_SUCCESS;
103 break;
104
105 /*
106 * Patch manager.
107 */
108 case VERR_EM_RAW_PATCH_CONFLICT:
109 AssertReleaseMsgFailed(("%Rrc handling is not yet implemented\n", rc));
110 break;
111#endif /* EMHANDLERC_WITH_PATM */
112
113#ifdef EMHANDLERC_WITH_PATM
114 /*
115 * Memory mapped I/O access - attempt to patch the instruction
116 */
117 case VINF_PATM_HC_MMIO_PATCH_READ:
118 rc = PATMR3InstallPatch(pVM, SELMToFlat(pVM, DISSELREG_CS, CPUMCTX2CORE(pCtx), pCtx->eip),
119 PATMFL_MMIO_ACCESS
120 | (CPUMGetGuestCodeBits(pVCpu) == 32 ? PATMFL_CODE32 : 0));
121 if (RT_FAILURE(rc))
122 rc = emR3ExecuteInstruction(pVM, pVCpu, "MMIO");
123 break;
124
125 case VINF_PATM_HC_MMIO_PATCH_WRITE:
126 AssertFailed(); /* not yet implemented. */
127 rc = emR3ExecuteInstruction(pVM, pVCpu, "MMIO");
128 break;
129#endif /* EMHANDLERC_WITH_PATM */
130
131 /*
132 * Conflict or out of page tables.
133 *
134 * VM_FF_PGM_SYNC_CR3 is set by the hypervisor and all we need to
135 * do here is to execute the pending forced actions.
136 */
137 case VINF_PGM_SYNC_CR3:
138 AssertMsg(VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_PGM_SYNC_CR3 | VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL),
139 ("VINF_PGM_SYNC_CR3 and no VMCPU_FF_PGM_SYNC_CR3*!\n"));
140 rc = VINF_SUCCESS;
141 break;
142
143 /*
144 * PGM pool flush pending (guest SMP only).
145 */
146 /** @todo jumping back and forth between ring 0 and 3 can burn a lot of cycles
147 * if the EMT thread that's supposed to handle the flush is currently not active
148 * (e.g. waiting to be scheduled) -> fix this properly!
149 *
150 * bird: Since the clearing is global and done via a rendezvous any CPU can do
151 * it. They would have to choose who to call VMMR3EmtRendezvous and send
152 * the rest to VMMR3EmtRendezvousFF ... Hmm ... that's not going to work
153 * all that well since the latter will race the setup done by the
154 * first. Guess that means we need some new magic in that area for
155 * handling this case. :/
156 */
157 case VINF_PGM_POOL_FLUSH_PENDING:
158 rc = VINF_SUCCESS;
159 break;
160
161 /*
162 * Paging mode change.
163 */
164 case VINF_PGM_CHANGE_MODE:
165 rc = PGMChangeMode(pVCpu, pCtx->cr0, pCtx->cr4, pCtx->msrEFER);
166 if (rc == VINF_SUCCESS)
167 rc = VINF_EM_RESCHEDULE;
168 AssertMsg(RT_FAILURE(rc) || (rc >= VINF_EM_FIRST && rc <= VINF_EM_LAST), ("%Rrc\n", rc));
169 break;
170
171#ifdef EMHANDLERC_WITH_PATM
172 /*
173 * CSAM wants to perform a task in ring-3. It has set an FF action flag.
174 */
175 case VINF_CSAM_PENDING_ACTION:
176 rc = VINF_SUCCESS;
177 break;
178
179 /*
180 * Invoked Interrupt gate - must directly (!) go to the recompiler.
181 */
182 case VINF_EM_RAW_INTERRUPT_PENDING:
183 case VINF_EM_RAW_RING_SWITCH_INT:
184 Assert(TRPMHasTrap(pVCpu));
185 Assert(!PATMIsPatchGCAddr(pVM, pCtx->eip));
186
187 if (TRPMHasTrap(pVCpu))
188 {
189 /* If the guest gate is marked unpatched, then we will check again if we can patch it. */
190 uint8_t u8Interrupt = TRPMGetTrapNo(pVCpu);
191 if (TRPMR3GetGuestTrapHandler(pVM, u8Interrupt) == TRPM_INVALID_HANDLER)
192 {
193 CSAMR3CheckGates(pVM, u8Interrupt, 1);
194 Log(("emR3RawHandleRC: recheck gate %x -> valid=%d\n", u8Interrupt, TRPMR3GetGuestTrapHandler(pVM, u8Interrupt) != TRPM_INVALID_HANDLER));
195 /* Note: If it was successful, then we could go back to raw mode, but let's keep things simple for now. */
196 }
197 }
198 rc = VINF_EM_RESCHEDULE_REM;
199 break;
200
201 /*
202 * Other ring switch types.
203 */
204 case VINF_EM_RAW_RING_SWITCH:
205 rc = emR3RawRingSwitch(pVM, pVCpu);
206 break;
207#endif /* EMHANDLERC_WITH_PATM */
208
209 /*
210 * I/O Port access - emulate the instruction.
211 */
212 case VINF_IOM_R3_IOPORT_READ:
213 case VINF_IOM_R3_IOPORT_WRITE:
214 rc = emR3ExecuteIOInstruction(pVM, pVCpu);
215 break;
216
217 /*
218 * Memory mapped I/O access - emulate the instruction.
219 */
220 case VINF_IOM_R3_MMIO_READ:
221 case VINF_IOM_R3_MMIO_WRITE:
222 case VINF_IOM_R3_MMIO_READ_WRITE:
223 rc = emR3ExecuteInstruction(pVM, pVCpu, "MMIO");
224 break;
225
226 /*
227 * Machine specific register access - emulate the instruction.
228 */
229 case VINF_CPUM_R3_MSR_READ:
230 case VINF_CPUM_R3_MSR_WRITE:
231 rc = emR3ExecuteInstruction(pVM, pVCpu, "MSR");
232 break;
233
234 /*
235 * GIM hypercall.
236 */
237 case VINF_GIM_R3_HYPERCALL:
238 {
239 /* Currently hypercall instruction (vmcall/vmmcall) emulation is compiled
240 only when Nested Hw. virt feature is enabled in IEM (for easier IEM backports). */
241#ifdef VBOX_WITH_NESTED_HWVIRT
242 rc = emR3ExecuteInstruction(pVM, pVCpu, "Hypercall");
243 break;
244#else
245 /** @todo IEM/REM need to handle VMCALL/VMMCALL, see
246 * @bugref{7270#c168}. */
247 uint8_t cbInstr = 0;
248 VBOXSTRICTRC rcStrict = GIMExecHypercallInstr(pVCpu, pCtx, &cbInstr);
249 if (rcStrict == VINF_SUCCESS)
250 {
251 Assert(cbInstr);
252 pCtx->rip += cbInstr;
253 /* Update interrupt inhibition. */
254 if ( VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS)
255 && pCtx->rip != EMGetInhibitInterruptsPC(pVCpu))
256 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS);
257 rc = VINF_SUCCESS;
258 }
259 else if (rcStrict == VINF_GIM_HYPERCALL_CONTINUING)
260 rc = VINF_SUCCESS;
261 else
262 {
263 Assert(rcStrict != VINF_GIM_R3_HYPERCALL);
264 rc = VBOXSTRICTRC_VAL(rcStrict);
265 }
266 break;
267#endif
268 }
269
270#ifdef EMHANDLERC_WITH_HM
271 /*
272 * (MM)IO intensive code block detected; fall back to the recompiler for better performance
273 */
274 case VINF_EM_RAW_EMULATE_IO_BLOCK:
275 rc = HMR3EmulateIoBlock(pVM, pCtx);
276 break;
277
278 case VINF_EM_HM_PATCH_TPR_INSTR:
279 rc = HMR3PatchTprInstr(pVM, pVCpu, pCtx);
280 break;
281#endif
282
283#ifdef EMHANDLERC_WITH_PATM
284 /*
285 * Execute instruction.
286 */
287 case VINF_EM_RAW_EMULATE_INSTR_LDT_FAULT:
288 rc = emR3ExecuteInstruction(pVM, pVCpu, "LDT FAULT: ");
289 break;
290 case VINF_EM_RAW_EMULATE_INSTR_GDT_FAULT:
291 rc = emR3ExecuteInstruction(pVM, pVCpu, "GDT FAULT: ");
292 break;
293 case VINF_EM_RAW_EMULATE_INSTR_IDT_FAULT:
294 rc = emR3ExecuteInstruction(pVM, pVCpu, "IDT FAULT: ");
295 break;
296 case VINF_EM_RAW_EMULATE_INSTR_TSS_FAULT:
297 rc = emR3ExecuteInstruction(pVM, pVCpu, "TSS FAULT: ");
298 break;
299#endif
300
301#ifdef EMHANDLERC_WITH_PATM
302 case VINF_PATM_PENDING_IRQ_AFTER_IRET:
303 rc = emR3ExecuteInstruction(pVM, pVCpu, "EMUL: ", VINF_PATM_PENDING_IRQ_AFTER_IRET);
304 break;
305
306 case VINF_PATCH_EMULATE_INSTR:
307#else
308 case VINF_EM_RAW_GUEST_TRAP:
309#endif
310 case VINF_EM_RAW_EMULATE_INSTR:
311 rc = emR3ExecuteInstruction(pVM, pVCpu, "EMUL: ");
312 break;
313
314 case VINF_EM_RAW_INJECT_TRPM_EVENT:
315 rc = VBOXSTRICTRC_VAL(IEMInjectTrpmEvent(pVCpu));
316 /* The following condition should be removed when IEM_IMPLEMENTS_TASKSWITCH becomes true. */
317 if (rc == VERR_IEM_ASPECT_NOT_IMPLEMENTED)
318 rc = emR3ExecuteInstruction(pVM, pVCpu, "EVENT: ");
319 break;
320
321
322#ifdef EMHANDLERC_WITH_PATM
323 /*
324 * Stale selector and iret traps => REM.
325 */
326 case VINF_EM_RAW_STALE_SELECTOR:
327 case VINF_EM_RAW_IRET_TRAP:
328 /* We will not go to the recompiler if EIP points to patch code. */
329 if (PATMIsPatchGCAddr(pVM, pCtx->eip))
330 {
331 pCtx->eip = PATMR3PatchToGCPtr(pVM, (RTGCPTR)pCtx->eip, 0);
332 }
333 LogFlow(("emR3RawHandleRC: %Rrc -> %Rrc\n", rc, VINF_EM_RESCHEDULE_REM));
334 rc = VINF_EM_RESCHEDULE_REM;
335 break;
336
337 /*
338 * Conflict in GDT, resync and continue.
339 */
340 case VINF_SELM_SYNC_GDT:
341 AssertMsg(VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_SELM_SYNC_GDT | VMCPU_FF_SELM_SYNC_LDT | VMCPU_FF_SELM_SYNC_TSS),
342 ("VINF_SELM_SYNC_GDT without VMCPU_FF_SELM_SYNC_GDT/LDT/TSS!\n"));
343 rc = VINF_SUCCESS;
344 break;
345#endif
346
347 /*
348 * Up a level.
349 */
350 case VINF_EM_TERMINATE:
351 case VINF_EM_OFF:
352 case VINF_EM_RESET:
353 case VINF_EM_SUSPEND:
354 case VINF_EM_HALT:
355 case VINF_EM_RESUME:
356 case VINF_EM_NO_MEMORY:
357 case VINF_EM_RESCHEDULE:
358 case VINF_EM_RESCHEDULE_REM:
359 case VINF_EM_WAIT_SIPI:
360 break;
361
362 /*
363 * Up a level and invoke the debugger.
364 */
365 case VINF_EM_DBG_STEPPED:
366 case VINF_EM_DBG_BREAKPOINT:
367 case VINF_EM_DBG_STEP:
368 case VINF_EM_DBG_HYPER_BREAKPOINT:
369 case VINF_EM_DBG_HYPER_STEPPED:
370 case VINF_EM_DBG_HYPER_ASSERTION:
371 case VINF_EM_DBG_STOP:
372 case VINF_EM_DBG_EVENT:
373 break;
374
375 /*
376 * Up a level, dump and debug.
377 */
378 case VERR_TRPM_DONT_PANIC:
379 case VERR_TRPM_PANIC:
380 case VERR_VMM_RING0_ASSERTION:
381 case VINF_EM_TRIPLE_FAULT:
382 case VERR_VMM_HYPER_CR3_MISMATCH:
383 case VERR_VMM_RING3_CALL_DISABLED:
384 case VERR_IEM_INSTR_NOT_IMPLEMENTED:
385 case VERR_IEM_ASPECT_NOT_IMPLEMENTED:
386 case VERR_EM_GUEST_CPU_HANG:
387 break;
388
389#ifdef EMHANDLERC_WITH_HM
390 /*
391 * Up a level, after Hm have done some release logging.
392 */
393 case VERR_VMX_INVALID_VMCS_FIELD:
394 case VERR_VMX_INVALID_VMCS_PTR:
395 case VERR_VMX_INVALID_VMXON_PTR:
396 case VERR_VMX_UNEXPECTED_INTERRUPTION_EXIT_TYPE:
397 case VERR_VMX_UNEXPECTED_EXCEPTION:
398 case VERR_VMX_UNEXPECTED_EXIT:
399 case VERR_VMX_INVALID_GUEST_STATE:
400 case VERR_VMX_UNABLE_TO_START_VM:
401 case VERR_SVM_UNKNOWN_EXIT:
402 case VERR_SVM_UNEXPECTED_EXIT:
403 case VERR_SVM_UNEXPECTED_PATCH_TYPE:
404 case VERR_SVM_UNEXPECTED_XCPT_EXIT:
405 HMR3CheckError(pVM, rc);
406 break;
407
408 /* Up a level; fatal */
409 case VERR_VMX_IN_VMX_ROOT_MODE:
410 case VERR_SVM_IN_USE:
411 case VERR_SVM_UNABLE_TO_START_VM:
412 break;
413#endif
414
415 /*
416 * These two should be handled via the force flag already, but just in
417 * case they end up here deal with it.
418 */
419 case VINF_IOM_R3_IOPORT_COMMIT_WRITE:
420 case VINF_IOM_R3_MMIO_COMMIT_WRITE:
421 AssertFailed();
422 rc = VBOXSTRICTRC_TODO(IOMR3ProcessForceFlag(pVM, pVCpu, rc));
423 break;
424
425 /*
426 * Anything which is not known to us means an internal error
427 * and the termination of the VM!
428 */
429 default:
430 AssertMsgFailed(("Unknown GC return code: %Rra\n", rc));
431 break;
432 }
433 return rc;
434}
435
436#endif
437
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