EMHandleRCTmpl.h@ 72492

Last change on this file since 72492 was 72492, checked in by vboxsync, 6 years ago
EM: build fix. bugref:9044
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1	/* $Id: EMHandleRCTmpl.h 72492 2018-06-09 15:16:55Z vboxsync $ */
2	/** @file
3	* EM - emR3[Raw\|Hm\|Nem]HandleRC template.
4	*/
5
6	/*
7	* Copyright (C) 2006-2018 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*/
17
18	#ifndef ___EMHandleRCTmpl_h
19	#define ___EMHandleRCTmpl_h
20
21	#if defined(EMHANDLERC_WITH_PATM) + defined(EMHANDLERC_WITH_HM) + defined(EMHANDLERC_WITH_NEM) != 1
22	# error "Exactly one of these must be defined: EMHANDLERC_WITH_PATM, EMHANDLERC_WITH_HM, EMHANDLERC_WITH_NEM"
23	#endif
24
25
26	/**
27	* Process a subset of the raw-mode and hm return codes.
28	*
29	* Since we have to share this with raw-mode single stepping, this inline
30	* function has been created to avoid code duplication.
31	*
32	* @returns VINF_SUCCESS if it's ok to continue raw mode.
33	* @returns VBox status code to return to the EM main loop.
34	*
35	* @param pVM The cross context VM structure.
36	* @param pVCpu The cross context virtual CPU structure.
37	* @param pCtx Pointer to the guest CPU context.
38	* @param rc The return code.
39	*/
40	#ifdef EMHANDLERC_WITH_PATM
41	int emR3RawHandleRC(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx, int rc)
42	#elif defined(EMHANDLERC_WITH_HM) \|\| defined(DOXYGEN_RUNNING)
43	int emR3HmHandleRC(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx, int rc)
44	#elif defined(EMHANDLERC_WITH_NEM)
45	int emR3NemHandleRC(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx, int rc)
46	#endif
47	{
48	NOREF(pCtx);
49
50	switch (rc)
51	{
52	/*
53	* Common & simple ones.
54	*/
55	case VINF_SUCCESS:
56	break;
57	case VINF_EM_RESCHEDULE_RAW:
58	case VINF_EM_RESCHEDULE_HM:
59	case VINF_EM_RAW_INTERRUPT:
60	case VINF_EM_RAW_TO_R3:
61	case VINF_EM_RAW_TIMER_PENDING:
62	case VINF_EM_PENDING_REQUEST:
63	rc = VINF_SUCCESS;
64	break;
65
66	#ifdef EMHANDLERC_WITH_PATM
67	/*
68	* Privileged instruction.
69	*/
70	case VINF_EM_RAW_EXCEPTION_PRIVILEGED:
71	case VINF_PATM_PATCH_TRAP_GP:
72	rc = emR3RawPrivileged(pVM, pVCpu);
73	break;
74
75	case VINF_EM_RAW_GUEST_TRAP:
76	/*
77	* Got a trap which needs dispatching.
78	*/
79	if (PATMR3IsInsidePatchJump(pVM, pCtx->eip, NULL))
80	{
81	AssertReleaseMsgFailed(("FATAL ERROR: executing random instruction inside generated patch jump %08X\n", CPUMGetGuestEIP(pVCpu)));
82	rc = VERR_EM_RAW_PATCH_CONFLICT;
83	break;
84	}
85	rc = emR3RawGuestTrap(pVM, pVCpu);
86	break;
87
88	/*
89	* Trap in patch code.
90	*/
91	case VINF_PATM_PATCH_TRAP_PF:
92	case VINF_PATM_PATCH_INT3:
93	rc = emR3RawPatchTrap(pVM, pVCpu, pCtx, rc);
94	break;
95
96	case VINF_PATM_DUPLICATE_FUNCTION:
97	Assert(PATMIsPatchGCAddr(pVM, pCtx->eip));
98	rc = PATMR3DuplicateFunctionRequest(pVM, pCtx);
99	AssertRC(rc);
100	rc = VINF_SUCCESS;
101	break;
102
103	case VINF_PATM_CHECK_PATCH_PAGE:
104	rc = PATMR3HandleMonitoredPage(pVM);
105	AssertRC(rc);
106	rc = VINF_SUCCESS;
107	break;
108
109	/*
110	* Patch manager.
111	*/
112	case VERR_EM_RAW_PATCH_CONFLICT:
113	AssertReleaseMsgFailed(("%Rrc handling is not yet implemented\n", rc));
114	break;
115
116	/*
117	* Memory mapped I/O access - attempt to patch the instruction
118	*/
119	case VINF_PATM_HC_MMIO_PATCH_READ:
120	rc = PATMR3InstallPatch(pVM, SELMToFlat(pVM, DISSELREG_CS, CPUMCTX2CORE(pCtx), pCtx->eip),
121	PATMFL_MMIO_ACCESS
122	\| (CPUMGetGuestCodeBits(pVCpu) == 32 ? PATMFL_CODE32 : 0));
123	if (RT_FAILURE(rc))
124	rc = emR3ExecuteInstruction(pVM, pVCpu, "MMIO");
125	break;
126
127	case VINF_PATM_HC_MMIO_PATCH_WRITE:
128	AssertFailed(); /* not yet implemented. */
129	rc = emR3ExecuteInstruction(pVM, pVCpu, "MMIO");
130	break;
131	#endif /* EMHANDLERC_WITH_PATM */
132
133	#ifndef EMHANDLERC_WITH_NEM
134	/*
135	* Conflict or out of page tables.
136	*
137	* VM_FF_PGM_SYNC_CR3 is set by the hypervisor and all we need to
138	* do here is to execute the pending forced actions.
139	*/
140	case VINF_PGM_SYNC_CR3:
141	AssertMsg(VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_PGM_SYNC_CR3 \| VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL),
142	("VINF_PGM_SYNC_CR3 and no VMCPU_FF_PGM_SYNC_CR3*!\n"));
143	rc = VINF_SUCCESS;
144	break;
145
146	/*
147	* PGM pool flush pending (guest SMP only).
148	*/
149	/** @todo jumping back and forth between ring 0 and 3 can burn a lot of cycles
150	* if the EMT thread that's supposed to handle the flush is currently not active
151	* (e.g. waiting to be scheduled) -> fix this properly!
152	*
153	* bird: Since the clearing is global and done via a rendezvous any CPU can do
154	* it. They would have to choose who to call VMMR3EmtRendezvous and send
155	* the rest to VMMR3EmtRendezvousFF ... Hmm ... that's not going to work
156	* all that well since the latter will race the setup done by the
157	* first. Guess that means we need some new magic in that area for
158	* handling this case. :/
159	*/
160	case VINF_PGM_POOL_FLUSH_PENDING:
161	rc = VINF_SUCCESS;
162	break;
163
164	/*
165	* Paging mode change.
166	*/
167	case VINF_PGM_CHANGE_MODE:
168	CPUM_ASSERT_NOT_EXTRN(pVCpu, CPUMCTX_EXTRN_CR0 \| CPUMCTX_EXTRN_CR3 \| CPUMCTX_EXTRN_CR4 \| CPUMCTX_EXTRN_EFER);
169	rc = PGMChangeMode(pVCpu, pCtx->cr0, pCtx->cr4, pCtx->msrEFER);
170	if (rc == VINF_SUCCESS)
171	rc = VINF_EM_RESCHEDULE;
172	AssertMsg(RT_FAILURE(rc) \|\| (rc >= VINF_EM_FIRST && rc <= VINF_EM_LAST), ("%Rrc\n", rc));
173	break;
174	#endif /* !EMHANDLERC_WITH_NEM */
175
176	#ifdef EMHANDLERC_WITH_PATM
177	/*
178	* CSAM wants to perform a task in ring-3. It has set an FF action flag.
179	*/
180	case VINF_CSAM_PENDING_ACTION:
181	rc = VINF_SUCCESS;
182	break;
183
184	/*
185	* Invoked Interrupt gate - must directly (!) go to the recompiler.
186	*/
187	case VINF_EM_RAW_INTERRUPT_PENDING:
188	case VINF_EM_RAW_RING_SWITCH_INT:
189	Assert(TRPMHasTrap(pVCpu));
190	Assert(!PATMIsPatchGCAddr(pVM, pCtx->eip));
191
192	if (TRPMHasTrap(pVCpu))
193	{
194	/* If the guest gate is marked unpatched, then we will check again if we can patch it. */
195	uint8_t u8Interrupt = TRPMGetTrapNo(pVCpu);
196	if (TRPMR3GetGuestTrapHandler(pVM, u8Interrupt) == TRPM_INVALID_HANDLER)
197	{
198	CSAMR3CheckGates(pVM, u8Interrupt, 1);
199	Log(("emR3RawHandleRC: recheck gate %x -> valid=%d\n", u8Interrupt, TRPMR3GetGuestTrapHandler(pVM, u8Interrupt) != TRPM_INVALID_HANDLER));
200	/* Note: If it was successful, then we could go back to raw mode, but let's keep things simple for now. */
201	}
202	}
203	rc = VINF_EM_RESCHEDULE_REM;
204	break;
205
206	/*
207	* Other ring switch types.
208	*/
209	case VINF_EM_RAW_RING_SWITCH:
210	rc = emR3RawRingSwitch(pVM, pVCpu);
211	break;
212	#endif /* EMHANDLERC_WITH_PATM */
213
214	/*
215	* I/O Port access - emulate the instruction.
216	*/
217	case VINF_IOM_R3_IOPORT_READ:
218	case VINF_IOM_R3_IOPORT_WRITE:
219	rc = emR3ExecuteIOInstruction(pVM, pVCpu);
220	break;
221
222	/*
223	* Execute pending I/O Port access.
224	*/
225	case VINF_EM_PENDING_R3_IOPORT_WRITE:
226	rc = VBOXSTRICTRC_TODO(emR3ExecutePendingIoPortWrite(pVM, pVCpu));
227	break;
228	case VINF_EM_PENDING_R3_IOPORT_READ:
229	rc = VBOXSTRICTRC_TODO(emR3ExecutePendingIoPortRead(pVM, pVCpu));
230	break;
231
232	/*
233	* Memory mapped I/O access - emulate the instruction.
234	*/
235	case VINF_IOM_R3_MMIO_READ:
236	case VINF_IOM_R3_MMIO_WRITE:
237	case VINF_IOM_R3_MMIO_READ_WRITE:
238	rc = emR3ExecuteInstruction(pVM, pVCpu, "MMIO");
239	break;
240
241	/*
242	* Machine specific register access - emulate the instruction.
243	*/
244	case VINF_CPUM_R3_MSR_READ:
245	case VINF_CPUM_R3_MSR_WRITE:
246	rc = emR3ExecuteInstruction(pVM, pVCpu, "MSR");
247	break;
248
249	/*
250	* GIM hypercall.
251	*/
252	case VINF_GIM_R3_HYPERCALL:
253	rc = emR3ExecuteInstruction(pVM, pVCpu, "Hypercall");
254	break;
255
256	#ifdef EMHANDLERC_WITH_HM
257	/*
258	* (MM)IO intensive code block detected; fall back to the recompiler for better performance
259	*/
260	case VINF_EM_RAW_EMULATE_IO_BLOCK:
261	rc = HMR3EmulateIoBlock(pVM, pCtx);
262	break;
263
264	case VINF_EM_HM_PATCH_TPR_INSTR:
265	rc = HMR3PatchTprInstr(pVM, pVCpu, pCtx);
266	break;
267	#endif
268
269	#ifdef EMHANDLERC_WITH_PATM
270	/*
271	* Execute instruction.
272	*/
273	case VINF_EM_RAW_EMULATE_INSTR_LDT_FAULT:
274	rc = emR3ExecuteInstruction(pVM, pVCpu, "LDT FAULT: ");
275	break;
276	case VINF_EM_RAW_EMULATE_INSTR_GDT_FAULT:
277	rc = emR3ExecuteInstruction(pVM, pVCpu, "GDT FAULT: ");
278	break;
279	case VINF_EM_RAW_EMULATE_INSTR_IDT_FAULT:
280	rc = emR3ExecuteInstruction(pVM, pVCpu, "IDT FAULT: ");
281	break;
282	case VINF_EM_RAW_EMULATE_INSTR_TSS_FAULT:
283	rc = emR3ExecuteInstruction(pVM, pVCpu, "TSS FAULT: ");
284	break;
285
286	case VINF_PATM_PENDING_IRQ_AFTER_IRET:
287	rc = emR3ExecuteInstruction(pVM, pVCpu, "EMUL: ", VINF_PATM_PENDING_IRQ_AFTER_IRET);
288	break;
289
290	case VINF_PATCH_EMULATE_INSTR:
291	#else
292	case VINF_EM_RAW_GUEST_TRAP:
293	#endif
294	case VINF_EM_RAW_EMULATE_INSTR:
295	rc = emR3ExecuteInstruction(pVM, pVCpu, "EMUL: ");
296	break;
297
298	case VINF_EM_RAW_INJECT_TRPM_EVENT:
299	CPUM_IMPORT_EXTRN_RET(pVCpu, IEM_CPUMCTX_EXTRN_XCPT_MASK);
300	rc = VBOXSTRICTRC_VAL(IEMInjectTrpmEvent(pVCpu));
301	/* The following condition should be removed when IEM_IMPLEMENTS_TASKSWITCH becomes true. */
302	if (rc == VERR_IEM_ASPECT_NOT_IMPLEMENTED)
303	rc = emR3ExecuteInstruction(pVM, pVCpu, "EVENT: ");
304	break;
305
306
307	#ifdef EMHANDLERC_WITH_PATM
308	/*
309	* Stale selector and iret traps => REM.
310	*/
311	case VINF_EM_RAW_STALE_SELECTOR:
312	case VINF_EM_RAW_IRET_TRAP:
313	/* We will not go to the recompiler if EIP points to patch code. */
314	if (PATMIsPatchGCAddr(pVM, pCtx->eip))
315	{
316	pCtx->eip = PATMR3PatchToGCPtr(pVM, (RTGCPTR)pCtx->eip, 0);
317	}
318	LogFlow(("emR3RawHandleRC: %Rrc -> %Rrc\n", rc, VINF_EM_RESCHEDULE_REM));
319	rc = VINF_EM_RESCHEDULE_REM;
320	break;
321
322	/*
323	* Conflict in GDT, resync and continue.
324	*/
325	case VINF_SELM_SYNC_GDT:
326	AssertMsg(VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_SELM_SYNC_GDT \| VMCPU_FF_SELM_SYNC_LDT \| VMCPU_FF_SELM_SYNC_TSS),
327	("VINF_SELM_SYNC_GDT without VMCPU_FF_SELM_SYNC_GDT/LDT/TSS!\n"));
328	rc = VINF_SUCCESS;
329	break;
330	#endif
331
332	/*
333	* Up a level.
334	*/
335	case VINF_EM_TERMINATE:
336	case VINF_EM_OFF:
337	case VINF_EM_RESET:
338	case VINF_EM_SUSPEND:
339	case VINF_EM_HALT:
340	case VINF_EM_RESUME:
341	case VINF_EM_NO_MEMORY:
342	case VINF_EM_RESCHEDULE:
343	case VINF_EM_RESCHEDULE_REM:
344	case VINF_EM_WAIT_SIPI:
345	break;
346
347	/*
348	* Up a level and invoke the debugger.
349	*/
350	case VINF_EM_DBG_STEPPED:
351	case VINF_EM_DBG_BREAKPOINT:
352	case VINF_EM_DBG_STEP:
353	case VINF_EM_DBG_HYPER_BREAKPOINT:
354	case VINF_EM_DBG_HYPER_STEPPED:
355	case VINF_EM_DBG_HYPER_ASSERTION:
356	case VINF_EM_DBG_STOP:
357	case VINF_EM_DBG_EVENT:
358	break;
359
360	/*
361	* Up a level, dump and debug.
362	*/
363	case VERR_TRPM_DONT_PANIC:
364	case VERR_TRPM_PANIC:
365	case VERR_VMM_RING0_ASSERTION:
366	case VINF_EM_TRIPLE_FAULT:
367	case VERR_VMM_HYPER_CR3_MISMATCH:
368	case VERR_VMM_RING3_CALL_DISABLED:
369	case VERR_IEM_INSTR_NOT_IMPLEMENTED:
370	case VERR_IEM_ASPECT_NOT_IMPLEMENTED:
371	case VERR_EM_GUEST_CPU_HANG:
372	break;
373
374	#ifdef EMHANDLERC_WITH_HM
375	/*
376	* Up a level, after Hm have done some release logging.
377	*/
378	case VERR_VMX_INVALID_VMCS_FIELD:
379	case VERR_VMX_INVALID_VMCS_PTR:
380	case VERR_VMX_INVALID_VMXON_PTR:
381	case VERR_VMX_UNEXPECTED_INTERRUPTION_EXIT_TYPE:
382	case VERR_VMX_UNEXPECTED_EXCEPTION:
383	case VERR_VMX_UNEXPECTED_EXIT:
384	case VERR_VMX_INVALID_GUEST_STATE:
385	case VERR_VMX_UNABLE_TO_START_VM:
386	case VERR_SVM_UNKNOWN_EXIT:
387	case VERR_SVM_UNEXPECTED_EXIT:
388	case VERR_SVM_UNEXPECTED_PATCH_TYPE:
389	case VERR_SVM_UNEXPECTED_XCPT_EXIT:
390	HMR3CheckError(pVM, rc);
391	break;
392
393	/* Up a level; fatal */
394	case VERR_VMX_IN_VMX_ROOT_MODE:
395	case VERR_SVM_IN_USE:
396	case VERR_SVM_UNABLE_TO_START_VM:
397	break;
398	#endif
399
400	/*
401	* These two should be handled via the force flag already, but just in
402	* case they end up here deal with it.
403	*/
404	case VINF_IOM_R3_IOPORT_COMMIT_WRITE:
405	case VINF_IOM_R3_MMIO_COMMIT_WRITE:
406	AssertFailed();
407	rc = VBOXSTRICTRC_TODO(IOMR3ProcessForceFlag(pVM, pVCpu, rc));
408	break;
409
410	/*
411	* Anything which is not known to us means an internal error
412	* and the termination of the VM!
413	*/
414	default:
415	AssertMsgFailed(("Unknown GC return code: %Rra\n", rc));
416	break;
417	}
418	return rc;
419	}
420
421	#endif
422

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source: vbox/trunk/src/VBox/VMM/include/EMHandleRCTmpl.h@ 72492

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