EMHandleRCTmpl.h@ 73770

Last change on this file since 73770 was 73203, checked in by vboxsync, 6 years ago
VMM, Devices: bugref:9193 Remove unused code after using EMRZSetPendingIoPort[Read\|Write].
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File size: 14.1 KB

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1	/* $Id: EMHandleRCTmpl.h 73203 2018-07-18 13:00:43Z vboxsync $ */
2	/** @file
3	* EM - emR3[Raw\|Hm\|Nem]HandleRC template.
4	*/
5
6	/*
7	* Copyright (C) 2006-2018 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*/
17
18	#ifndef ___EMHandleRCTmpl_h
19	#define ___EMHandleRCTmpl_h
20
21	#if defined(EMHANDLERC_WITH_PATM) + defined(EMHANDLERC_WITH_HM) + defined(EMHANDLERC_WITH_NEM) != 1
22	# error "Exactly one of these must be defined: EMHANDLERC_WITH_PATM, EMHANDLERC_WITH_HM, EMHANDLERC_WITH_NEM"
23	#endif
24
25
26	/**
27	* Process a subset of the raw-mode, HM and NEM return codes.
28	*
29	* Since we have to share this with raw-mode single stepping, this inline
30	* function has been created to avoid code duplication.
31	*
32	* @returns VINF_SUCCESS if it's ok to continue raw mode.
33	* @returns VBox status code to return to the EM main loop.
34	*
35	* @param pVM The cross context VM structure.
36	* @param pVCpu The cross context virtual CPU structure.
37	* @param rc The return code.
38	*/
39	#ifdef EMHANDLERC_WITH_PATM
40	int emR3RawHandleRC(PVM pVM, PVMCPU pVCpu, int rc)
41	#elif defined(EMHANDLERC_WITH_HM) \|\| defined(DOXYGEN_RUNNING)
42	int emR3HmHandleRC(PVM pVM, PVMCPU pVCpu, int rc)
43	#elif defined(EMHANDLERC_WITH_NEM)
44	int emR3NemHandleRC(PVM pVM, PVMCPU pVCpu, int rc)
45	#endif
46	{
47	switch (rc)
48	{
49	/*
50	* Common & simple ones.
51	*/
52	case VINF_SUCCESS:
53	break;
54	case VINF_EM_RESCHEDULE_RAW:
55	case VINF_EM_RESCHEDULE_HM:
56	case VINF_EM_RAW_INTERRUPT:
57	case VINF_EM_RAW_TO_R3:
58	case VINF_EM_RAW_TIMER_PENDING:
59	case VINF_EM_PENDING_REQUEST:
60	rc = VINF_SUCCESS;
61	break;
62
63	#ifdef EMHANDLERC_WITH_PATM
64	/*
65	* Privileged instruction.
66	*/
67	case VINF_EM_RAW_EXCEPTION_PRIVILEGED:
68	case VINF_PATM_PATCH_TRAP_GP:
69	rc = emR3RawPrivileged(pVM, pVCpu);
70	break;
71
72	case VINF_EM_RAW_GUEST_TRAP:
73	/*
74	* Got a trap which needs dispatching.
75	*/
76	if (PATMR3IsInsidePatchJump(pVM, pVCpu->cpum.GstCtx.eip, NULL))
77	{
78	AssertReleaseMsgFailed(("FATAL ERROR: executing random instruction inside generated patch jump %08X\n", CPUMGetGuestEIP(pVCpu)));
79	rc = VERR_EM_RAW_PATCH_CONFLICT;
80	break;
81	}
82	rc = emR3RawGuestTrap(pVM, pVCpu);
83	break;
84
85	/*
86	* Trap in patch code.
87	*/
88	case VINF_PATM_PATCH_TRAP_PF:
89	case VINF_PATM_PATCH_INT3:
90	rc = emR3RawPatchTrap(pVM, pVCpu, rc);
91	break;
92
93	case VINF_PATM_DUPLICATE_FUNCTION:
94	Assert(PATMIsPatchGCAddr(pVM, pVCpu->cpum.GstCtx.eip));
95	rc = PATMR3DuplicateFunctionRequest(pVM, &pVCpu->cpum.GstCtx);
96	AssertRC(rc);
97	rc = VINF_SUCCESS;
98	break;
99
100	case VINF_PATM_CHECK_PATCH_PAGE:
101	rc = PATMR3HandleMonitoredPage(pVM);
102	AssertRC(rc);
103	rc = VINF_SUCCESS;
104	break;
105
106	/*
107	* Patch manager.
108	*/
109	case VERR_EM_RAW_PATCH_CONFLICT:
110	AssertReleaseMsgFailed(("%Rrc handling is not yet implemented\n", rc));
111	break;
112
113	/*
114	* Memory mapped I/O access - attempt to patch the instruction
115	*/
116	case VINF_PATM_HC_MMIO_PATCH_READ:
117	rc = PATMR3InstallPatch(pVM, SELMToFlat(pVM, DISSELREG_CS, CPUMCTX2CORE(&pVCpu->cpum.GstCtx), pVCpu->cpum.GstCtx.eip),
118	PATMFL_MMIO_ACCESS
119	\| (CPUMGetGuestCodeBits(pVCpu) == 32 ? PATMFL_CODE32 : 0));
120	if (RT_FAILURE(rc))
121	rc = emR3ExecuteInstruction(pVM, pVCpu, "MMIO");
122	break;
123
124	case VINF_PATM_HC_MMIO_PATCH_WRITE:
125	AssertFailed(); /* not yet implemented. */
126	rc = emR3ExecuteInstruction(pVM, pVCpu, "MMIO");
127	break;
128	#endif /* EMHANDLERC_WITH_PATM */
129
130	#ifndef EMHANDLERC_WITH_NEM
131	/*
132	* Conflict or out of page tables.
133	*
134	* VM_FF_PGM_SYNC_CR3 is set by the hypervisor and all we need to
135	* do here is to execute the pending forced actions.
136	*/
137	case VINF_PGM_SYNC_CR3:
138	AssertMsg(VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_PGM_SYNC_CR3 \| VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL),
139	("VINF_PGM_SYNC_CR3 and no VMCPU_FF_PGM_SYNC_CR3*!\n"));
140	rc = VINF_SUCCESS;
141	break;
142
143	/*
144	* PGM pool flush pending (guest SMP only).
145	*/
146	/** @todo jumping back and forth between ring 0 and 3 can burn a lot of cycles
147	* if the EMT thread that's supposed to handle the flush is currently not active
148	* (e.g. waiting to be scheduled) -> fix this properly!
149	*
150	* bird: Since the clearing is global and done via a rendezvous any CPU can do
151	* it. They would have to choose who to call VMMR3EmtRendezvous and send
152	* the rest to VMMR3EmtRendezvousFF ... Hmm ... that's not going to work
153	* all that well since the latter will race the setup done by the
154	* first. Guess that means we need some new magic in that area for
155	* handling this case. :/
156	*/
157	case VINF_PGM_POOL_FLUSH_PENDING:
158	rc = VINF_SUCCESS;
159	break;
160
161	/*
162	* Paging mode change.
163	*/
164	case VINF_PGM_CHANGE_MODE:
165	CPUM_ASSERT_NOT_EXTRN(pVCpu, CPUMCTX_EXTRN_CR0 \| CPUMCTX_EXTRN_CR3 \| CPUMCTX_EXTRN_CR4 \| CPUMCTX_EXTRN_EFER);
166	rc = PGMChangeMode(pVCpu, pVCpu->cpum.GstCtx.cr0, pVCpu->cpum.GstCtx.cr4, pVCpu->cpum.GstCtx.msrEFER);
167	if (rc == VINF_SUCCESS)
168	rc = VINF_EM_RESCHEDULE;
169	AssertMsg(RT_FAILURE(rc) \|\| (rc >= VINF_EM_FIRST && rc <= VINF_EM_LAST), ("%Rrc\n", rc));
170	break;
171	#endif /* !EMHANDLERC_WITH_NEM */
172
173	#ifdef EMHANDLERC_WITH_PATM
174	/*
175	* CSAM wants to perform a task in ring-3. It has set an FF action flag.
176	*/
177	case VINF_CSAM_PENDING_ACTION:
178	rc = VINF_SUCCESS;
179	break;
180
181	/*
182	* Invoked Interrupt gate - must directly (!) go to the recompiler.
183	*/
184	case VINF_EM_RAW_INTERRUPT_PENDING:
185	case VINF_EM_RAW_RING_SWITCH_INT:
186	Assert(TRPMHasTrap(pVCpu));
187	Assert(!PATMIsPatchGCAddr(pVM, pVCpu->cpum.GstCtx.eip));
188
189	if (TRPMHasTrap(pVCpu))
190	{
191	/* If the guest gate is marked unpatched, then we will check again if we can patch it. */
192	uint8_t u8Interrupt = TRPMGetTrapNo(pVCpu);
193	if (TRPMR3GetGuestTrapHandler(pVM, u8Interrupt) == TRPM_INVALID_HANDLER)
194	{
195	CSAMR3CheckGates(pVM, u8Interrupt, 1);
196	Log(("emR3RawHandleRC: recheck gate %x -> valid=%d\n", u8Interrupt, TRPMR3GetGuestTrapHandler(pVM, u8Interrupt) != TRPM_INVALID_HANDLER));
197	/* Note: If it was successful, then we could go back to raw mode, but let's keep things simple for now. */
198	}
199	}
200	rc = VINF_EM_RESCHEDULE_REM;
201	break;
202
203	/*
204	* Other ring switch types.
205	*/
206	case VINF_EM_RAW_RING_SWITCH:
207	rc = emR3RawRingSwitch(pVM, pVCpu);
208	break;
209	#endif /* EMHANDLERC_WITH_PATM */
210
211	/*
212	* I/O Port access - emulate the instruction.
213	*/
214	case VINF_IOM_R3_IOPORT_READ:
215	case VINF_IOM_R3_IOPORT_WRITE:
216	case VINF_EM_RESUME_R3_HISTORY_EXEC: /* Resume EMHistoryExec after VMCPU_FF_IOM. */
217	rc = emR3ExecuteIOInstruction(pVM, pVCpu);
218	break;
219
220	/*
221	* Execute pending I/O Port access.
222	*/
223	case VINF_EM_PENDING_R3_IOPORT_WRITE:
224	rc = VBOXSTRICTRC_TODO(emR3ExecutePendingIoPortWrite(pVM, pVCpu));
225	break;
226	case VINF_EM_PENDING_R3_IOPORT_READ:
227	rc = VBOXSTRICTRC_TODO(emR3ExecutePendingIoPortRead(pVM, pVCpu));
228	break;
229
230	/*
231	* Memory mapped I/O access - emulate the instruction.
232	*/
233	case VINF_IOM_R3_MMIO_READ:
234	case VINF_IOM_R3_MMIO_WRITE:
235	case VINF_IOM_R3_MMIO_READ_WRITE:
236	rc = emR3ExecuteInstruction(pVM, pVCpu, "MMIO");
237	break;
238
239	/*
240	* Machine specific register access - emulate the instruction.
241	*/
242	case VINF_CPUM_R3_MSR_READ:
243	case VINF_CPUM_R3_MSR_WRITE:
244	rc = emR3ExecuteInstruction(pVM, pVCpu, "MSR");
245	break;
246
247	/*
248	* GIM hypercall.
249	*/
250	case VINF_GIM_R3_HYPERCALL:
251	rc = emR3ExecuteInstruction(pVM, pVCpu, "Hypercall");
252	break;
253
254	#ifdef EMHANDLERC_WITH_HM
255	case VINF_EM_HM_PATCH_TPR_INSTR:
256	rc = HMR3PatchTprInstr(pVM, pVCpu);
257	break;
258	#endif
259
260	#ifdef EMHANDLERC_WITH_PATM
261	/*
262	* Execute instruction.
263	*/
264	case VINF_EM_RAW_EMULATE_INSTR_LDT_FAULT:
265	rc = emR3ExecuteInstruction(pVM, pVCpu, "LDT FAULT: ");
266	break;
267	case VINF_EM_RAW_EMULATE_INSTR_GDT_FAULT:
268	rc = emR3ExecuteInstruction(pVM, pVCpu, "GDT FAULT: ");
269	break;
270	case VINF_EM_RAW_EMULATE_INSTR_IDT_FAULT:
271	rc = emR3ExecuteInstruction(pVM, pVCpu, "IDT FAULT: ");
272	break;
273	case VINF_EM_RAW_EMULATE_INSTR_TSS_FAULT:
274	rc = emR3ExecuteInstruction(pVM, pVCpu, "TSS FAULT: ");
275	break;
276
277	case VINF_PATM_PENDING_IRQ_AFTER_IRET:
278	rc = emR3ExecuteInstruction(pVM, pVCpu, "EMUL: ", VINF_PATM_PENDING_IRQ_AFTER_IRET);
279	break;
280
281	case VINF_PATCH_EMULATE_INSTR:
282	#else
283	case VINF_EM_RAW_GUEST_TRAP:
284	#endif
285	case VINF_EM_RAW_EMULATE_INSTR:
286	rc = emR3ExecuteInstruction(pVM, pVCpu, "EMUL: ");
287	break;
288
289	case VINF_EM_RAW_INJECT_TRPM_EVENT:
290	CPUM_IMPORT_EXTRN_RET(pVCpu, IEM_CPUMCTX_EXTRN_XCPT_MASK);
291	rc = VBOXSTRICTRC_VAL(IEMInjectTrpmEvent(pVCpu));
292	/* The following condition should be removed when IEM_IMPLEMENTS_TASKSWITCH becomes true. */
293	if (rc == VERR_IEM_ASPECT_NOT_IMPLEMENTED)
294	rc = emR3ExecuteInstruction(pVM, pVCpu, "EVENT: ");
295	break;
296
297
298	#ifdef EMHANDLERC_WITH_PATM
299	/*
300	* Stale selector and iret traps => REM.
301	*/
302	case VINF_EM_RAW_STALE_SELECTOR:
303	case VINF_EM_RAW_IRET_TRAP:
304	/* We will not go to the recompiler if EIP points to patch code. */
305	if (PATMIsPatchGCAddr(pVM, pVCpu->cpum.GstCtx.eip))
306	{
307	pVCpu->cpum.GstCtx.eip = PATMR3PatchToGCPtr(pVM, (RTGCPTR)pVCpu->cpum.GstCtx.eip, 0);
308	}
309	LogFlow(("emR3RawHandleRC: %Rrc -> %Rrc\n", rc, VINF_EM_RESCHEDULE_REM));
310	rc = VINF_EM_RESCHEDULE_REM;
311	break;
312
313	/*
314	* Conflict in GDT, resync and continue.
315	*/
316	case VINF_SELM_SYNC_GDT:
317	AssertMsg(VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_SELM_SYNC_GDT \| VMCPU_FF_SELM_SYNC_LDT \| VMCPU_FF_SELM_SYNC_TSS),
318	("VINF_SELM_SYNC_GDT without VMCPU_FF_SELM_SYNC_GDT/LDT/TSS!\n"));
319	rc = VINF_SUCCESS;
320	break;
321	#endif
322
323	/*
324	* Up a level.
325	*/
326	case VINF_EM_TERMINATE:
327	case VINF_EM_OFF:
328	case VINF_EM_RESET:
329	case VINF_EM_SUSPEND:
330	case VINF_EM_HALT:
331	case VINF_EM_RESUME:
332	case VINF_EM_NO_MEMORY:
333	case VINF_EM_RESCHEDULE:
334	case VINF_EM_RESCHEDULE_REM:
335	case VINF_EM_WAIT_SIPI:
336	break;
337
338	/*
339	* Up a level and invoke the debugger.
340	*/
341	case VINF_EM_DBG_STEPPED:
342	case VINF_EM_DBG_BREAKPOINT:
343	case VINF_EM_DBG_STEP:
344	case VINF_EM_DBG_HYPER_BREAKPOINT:
345	case VINF_EM_DBG_HYPER_STEPPED:
346	case VINF_EM_DBG_HYPER_ASSERTION:
347	case VINF_EM_DBG_STOP:
348	case VINF_EM_DBG_EVENT:
349	break;
350
351	/*
352	* Up a level, dump and debug.
353	*/
354	case VERR_TRPM_DONT_PANIC:
355	case VERR_TRPM_PANIC:
356	case VERR_VMM_RING0_ASSERTION:
357	case VINF_EM_TRIPLE_FAULT:
358	case VERR_VMM_HYPER_CR3_MISMATCH:
359	case VERR_VMM_RING3_CALL_DISABLED:
360	case VERR_IEM_INSTR_NOT_IMPLEMENTED:
361	case VERR_IEM_ASPECT_NOT_IMPLEMENTED:
362	case VERR_EM_GUEST_CPU_HANG:
363	break;
364
365	#ifdef EMHANDLERC_WITH_HM
366	/*
367	* Up a level, after Hm have done some release logging.
368	*/
369	case VERR_VMX_INVALID_VMCS_FIELD:
370	case VERR_VMX_INVALID_VMCS_PTR:
371	case VERR_VMX_INVALID_VMXON_PTR:
372	case VERR_VMX_UNEXPECTED_INTERRUPTION_EXIT_TYPE:
373	case VERR_VMX_UNEXPECTED_EXCEPTION:
374	case VERR_VMX_UNEXPECTED_EXIT:
375	case VERR_VMX_INVALID_GUEST_STATE:
376	case VERR_VMX_UNABLE_TO_START_VM:
377	case VERR_SVM_UNKNOWN_EXIT:
378	case VERR_SVM_UNEXPECTED_EXIT:
379	case VERR_SVM_UNEXPECTED_PATCH_TYPE:
380	case VERR_SVM_UNEXPECTED_XCPT_EXIT:
381	HMR3CheckError(pVM, rc);
382	break;
383
384	/* Up a level; fatal */
385	case VERR_VMX_IN_VMX_ROOT_MODE:
386	case VERR_SVM_IN_USE:
387	case VERR_SVM_UNABLE_TO_START_VM:
388	break;
389	#endif
390
391	/*
392	* These two should be handled via the force flag already, but just in
393	* case they end up here deal with it.
394	*/
395	case VINF_IOM_R3_IOPORT_COMMIT_WRITE:
396	case VINF_IOM_R3_MMIO_COMMIT_WRITE:
397	AssertFailed();
398	rc = VBOXSTRICTRC_TODO(IOMR3ProcessForceFlag(pVM, pVCpu, rc));
399	break;
400
401	/*
402	* Anything which is not known to us means an internal error
403	* and the termination of the VM!
404	*/
405	default:
406	AssertMsgFailed(("Unknown GC return code: %Rra\n", rc));
407	break;
408	}
409	return rc;
410	}
411
412	#endif
413

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source: vbox/trunk/src/VBox/VMM/include/EMHandleRCTmpl.h@ 73770

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