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source: vbox/trunk/src/VBox/VMM/include/EMHandleRCTmpl.h@ 91263

Last change on this file since 91263 was 89993, checked in by vboxsync, 3 years ago

VMM/HMVMX/EM: Do a rendezvous when a split-lock #AC is emulated. Currently doing this for single-cpu VMs too, will change that after some testing. bugref:10052
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File size: 8.9 KB
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1/* $Id: EMHandleRCTmpl.h 89993 2021-07-02 09:21:45Z vboxsync $ */
2/** @file
3 * EM - emR3[Raw|Hm|Nem]HandleRC template.
4 */
5
6/*
7 * Copyright (C) 2006-2020 Oracle Corporation
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 */
17
18#ifndef VMM_INCLUDED_SRC_include_EMHandleRCTmpl_h
19#define VMM_INCLUDED_SRC_include_EMHandleRCTmpl_h
20#ifndef RT_WITHOUT_PRAGMA_ONCE
21# pragma once
22#endif
23
24#if defined(EMHANDLERC_WITH_PATM) + defined(EMHANDLERC_WITH_HM) + defined(EMHANDLERC_WITH_NEM) != 1
25# error "Exactly one of these must be defined: EMHANDLERC_WITH_PATM, EMHANDLERC_WITH_HM, EMHANDLERC_WITH_NEM"
26#endif
27
28
29/**
30 * Process a subset of the raw-mode, HM and NEM return codes.
31 *
32 * Since we have to share this with raw-mode single stepping, this inline
33 * function has been created to avoid code duplication.
34 *
35 * @returns VINF_SUCCESS if it's ok to continue raw mode.
36 * @returns VBox status code to return to the EM main loop.
37 *
38 * @param pVM The cross context VM structure.
39 * @param pVCpu The cross context virtual CPU structure.
40 * @param rc The return code.
41 */
42#if defined(EMHANDLERC_WITH_HM) || defined(DOXYGEN_RUNNING)
43int emR3HmHandleRC(PVM pVM, PVMCPU pVCpu, int rc)
44#elif defined(EMHANDLERC_WITH_NEM)
45int emR3NemHandleRC(PVM pVM, PVMCPU pVCpu, int rc)
46#endif
47{
48 switch (rc)
49 {
50 /*
51 * Common & simple ones.
52 */
53 case VINF_SUCCESS:
54 break;
55 case VINF_EM_RESCHEDULE_RAW:
56 case VINF_EM_RESCHEDULE_HM:
57 case VINF_EM_RAW_INTERRUPT:
58 case VINF_EM_RAW_TO_R3:
59 case VINF_EM_RAW_TIMER_PENDING:
60 case VINF_EM_PENDING_REQUEST:
61 rc = VINF_SUCCESS;
62 break;
63
64#ifndef EMHANDLERC_WITH_NEM
65 /*
66 * Conflict or out of page tables.
67 *
68 * VM_FF_PGM_SYNC_CR3 is set by the hypervisor and all we need to
69 * do here is to execute the pending forced actions.
70 */
71 case VINF_PGM_SYNC_CR3:
72 AssertMsg(VMCPU_FF_IS_ANY_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3 | VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL),
73 ("VINF_PGM_SYNC_CR3 and no VMCPU_FF_PGM_SYNC_CR3*!\n"));
74 rc = VINF_SUCCESS;
75 break;
76
77 /*
78 * PGM pool flush pending (guest SMP only).
79 */
80 /** @todo jumping back and forth between ring 0 and 3 can burn a lot of cycles
81 * if the EMT thread that's supposed to handle the flush is currently not active
82 * (e.g. waiting to be scheduled) -> fix this properly!
83 *
84 * bird: Since the clearing is global and done via a rendezvous any CPU can do
85 * it. They would have to choose who to call VMMR3EmtRendezvous and send
86 * the rest to VMMR3EmtRendezvousFF ... Hmm ... that's not going to work
87 * all that well since the latter will race the setup done by the
88 * first. Guess that means we need some new magic in that area for
89 * handling this case. :/
90 */
91 case VINF_PGM_POOL_FLUSH_PENDING:
92 rc = VINF_SUCCESS;
93 break;
94
95 /*
96 * Paging mode change.
97 */
98 case VINF_PGM_CHANGE_MODE:
99 CPUM_ASSERT_NOT_EXTRN(pVCpu, CPUMCTX_EXTRN_CR0 | CPUMCTX_EXTRN_CR3 | CPUMCTX_EXTRN_CR4 | CPUMCTX_EXTRN_EFER);
100 rc = PGMChangeMode(pVCpu, pVCpu->cpum.GstCtx.cr0, pVCpu->cpum.GstCtx.cr4, pVCpu->cpum.GstCtx.msrEFER);
101 if (rc == VINF_SUCCESS)
102 rc = VINF_EM_RESCHEDULE;
103 AssertMsg(RT_FAILURE(rc) || (rc >= VINF_EM_FIRST && rc <= VINF_EM_LAST), ("%Rrc\n", rc));
104 break;
105#endif /* !EMHANDLERC_WITH_NEM */
106
107 /*
108 * I/O Port access - emulate the instruction.
109 */
110 case VINF_IOM_R3_IOPORT_READ:
111 case VINF_IOM_R3_IOPORT_WRITE:
112 case VINF_EM_RESUME_R3_HISTORY_EXEC: /* Resume EMHistoryExec after VMCPU_FF_IOM. */
113 rc = emR3ExecuteIOInstruction(pVM, pVCpu);
114 break;
115
116 /*
117 * Execute pending I/O Port access.
118 */
119 case VINF_EM_PENDING_R3_IOPORT_WRITE:
120 rc = VBOXSTRICTRC_TODO(emR3ExecutePendingIoPortWrite(pVM, pVCpu));
121 break;
122 case VINF_EM_PENDING_R3_IOPORT_READ:
123 rc = VBOXSTRICTRC_TODO(emR3ExecutePendingIoPortRead(pVM, pVCpu));
124 break;
125
126 /*
127 * Memory mapped I/O access - emulate the instruction.
128 */
129 case VINF_IOM_R3_MMIO_READ:
130 case VINF_IOM_R3_MMIO_WRITE:
131 case VINF_IOM_R3_MMIO_READ_WRITE:
132 rc = emR3ExecuteInstruction(pVM, pVCpu, "MMIO");
133 break;
134
135 /*
136 * Machine specific register access - emulate the instruction.
137 */
138 case VINF_CPUM_R3_MSR_READ:
139 case VINF_CPUM_R3_MSR_WRITE:
140 rc = emR3ExecuteInstruction(pVM, pVCpu, "MSR");
141 break;
142
143 /*
144 * GIM hypercall.
145 */
146 case VINF_GIM_R3_HYPERCALL:
147 rc = emR3ExecuteInstruction(pVM, pVCpu, "Hypercall");
148 break;
149
150#ifdef EMHANDLERC_WITH_HM
151 case VINF_EM_HM_PATCH_TPR_INSTR:
152 rc = HMR3PatchTprInstr(pVM, pVCpu);
153 break;
154#endif
155
156 case VINF_EM_RAW_GUEST_TRAP:
157 case VINF_EM_RAW_EMULATE_INSTR:
158 Assert(!TRPMHasTrap(pVCpu)); /* We're directly executing instructions below without respecting any pending traps! */
159 rc = emR3ExecuteInstruction(pVM, pVCpu, "EMUL: ");
160 break;
161
162 case VINF_EM_RAW_INJECT_TRPM_EVENT:
163 CPUM_IMPORT_EXTRN_RET(pVCpu, IEM_CPUMCTX_EXTRN_XCPT_MASK);
164 rc = VBOXSTRICTRC_VAL(IEMInjectTrpmEvent(pVCpu));
165 /* The following condition should be removed when IEM_IMPLEMENTS_TASKSWITCH becomes true. */
166 if (rc == VERR_IEM_ASPECT_NOT_IMPLEMENTED)
167 rc = emR3ExecuteInstruction(pVM, pVCpu, "EVENT: ");
168 break;
169
170 case VINF_EM_EMULATE_SPLIT_LOCK:
171 rc = VBOXSTRICTRC_TODO(emR3ExecuteSplitLockInstruction(pVM, pVCpu));
172 break;
173
174
175 /*
176 * Up a level.
177 */
178 case VINF_EM_TERMINATE:
179 case VINF_EM_OFF:
180 case VINF_EM_RESET:
181 case VINF_EM_SUSPEND:
182 case VINF_EM_HALT:
183 case VINF_EM_RESUME:
184 case VINF_EM_NO_MEMORY:
185 case VINF_EM_RESCHEDULE:
186 case VINF_EM_RESCHEDULE_REM:
187 case VINF_EM_WAIT_SIPI:
188 break;
189
190 /*
191 * Up a level and invoke the debugger.
192 */
193 case VINF_EM_DBG_STEPPED:
194 case VINF_EM_DBG_BREAKPOINT:
195 case VINF_EM_DBG_STEP:
196 case VINF_EM_DBG_HYPER_BREAKPOINT:
197 case VINF_EM_DBG_HYPER_STEPPED:
198 case VINF_EM_DBG_HYPER_ASSERTION:
199 case VINF_EM_DBG_STOP:
200 case VINF_EM_DBG_EVENT:
201 break;
202
203 /*
204 * Up a level, dump and debug.
205 */
206 case VERR_TRPM_DONT_PANIC:
207 case VERR_TRPM_PANIC:
208 case VERR_VMM_RING0_ASSERTION:
209 case VINF_EM_TRIPLE_FAULT:
210 case VERR_VMM_HYPER_CR3_MISMATCH:
211 case VERR_VMM_RING3_CALL_DISABLED:
212 case VERR_IEM_INSTR_NOT_IMPLEMENTED:
213 case VERR_IEM_ASPECT_NOT_IMPLEMENTED:
214 case VERR_EM_GUEST_CPU_HANG:
215 break;
216
217#ifdef EMHANDLERC_WITH_HM
218 /*
219 * Up a level, after Hm have done some release logging.
220 */
221 case VERR_VMX_INVALID_VMCS_FIELD:
222 case VERR_VMX_INVALID_VMCS_PTR:
223 case VERR_VMX_INVALID_VMXON_PTR:
224 case VERR_VMX_UNEXPECTED_INTERRUPTION_EXIT_TYPE:
225 case VERR_VMX_UNEXPECTED_EXCEPTION:
226 case VERR_VMX_UNEXPECTED_EXIT:
227 case VERR_VMX_INVALID_GUEST_STATE:
228 case VERR_VMX_UNABLE_TO_START_VM:
229 case VERR_SVM_UNKNOWN_EXIT:
230 case VERR_SVM_UNEXPECTED_EXIT:
231 case VERR_SVM_UNEXPECTED_PATCH_TYPE:
232 case VERR_SVM_UNEXPECTED_XCPT_EXIT:
233 HMR3CheckError(pVM, rc);
234 break;
235
236 /* Up a level; fatal */
237 case VERR_VMX_IN_VMX_ROOT_MODE:
238 case VERR_SVM_IN_USE:
239 case VERR_SVM_UNABLE_TO_START_VM:
240 break;
241#endif
242
243 /*
244 * These two should be handled via the force flag already, but just in
245 * case they end up here deal with it.
246 */
247 case VINF_IOM_R3_IOPORT_COMMIT_WRITE:
248 case VINF_IOM_R3_MMIO_COMMIT_WRITE:
249 AssertFailed();
250 rc = VBOXSTRICTRC_TODO(IOMR3ProcessForceFlag(pVM, pVCpu, rc));
251 break;
252
253 /*
254 * Anything which is not known to us means an internal error
255 * and the termination of the VM!
256 */
257 default:
258 AssertMsgFailed(("Unknown GC return code: %Rra\n", rc));
259 break;
260 }
261 return rc;
262}
263
264#endif /* !VMM_INCLUDED_SRC_include_EMHandleRCTmpl_h */
265
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