VirtualBox

source: vbox/trunk/src/VBox/VMM/include/EMInternal.h@ 72576

Last change on this file since 72576 was 72576, checked in by vboxsync, 6 years ago

EM: build fix. bugref:9044
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1/* $Id: EMInternal.h 72576 2018-06-15 21:27:49Z vboxsync $ */
2/** @file
3 * EM - Internal header file.
4 */
5
6/*
7 * Copyright (C) 2006-2017 Oracle Corporation
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 */
17
18#ifndef ___EMInternal_h
19#define ___EMInternal_h
20
21#include <VBox/cdefs.h>
22#include <VBox/types.h>
23#include <VBox/vmm/em.h>
24#include <VBox/vmm/stam.h>
25#include <VBox/vmm/patm.h>
26#include <VBox/dis.h>
27#include <VBox/vmm/pdmcritsect.h>
28#include <iprt/avl.h>
29#include <setjmp.h>
30
31RT_C_DECLS_BEGIN
32
33
34/** @defgroup grp_em_int Internal
35 * @ingroup grp_em
36 * @internal
37 * @{
38 */
39
40/** The saved state version. */
41#define EM_SAVED_STATE_VERSION 5
42#define EM_SAVED_STATE_VERSION_PRE_IEM 4
43#define EM_SAVED_STATE_VERSION_PRE_MWAIT 3
44#define EM_SAVED_STATE_VERSION_PRE_SMP 2
45
46
47/** @name MWait state flags.
48 * @{
49 */
50/** MWait activated. */
51#define EMMWAIT_FLAG_ACTIVE RT_BIT(0)
52/** MWait will continue when an interrupt is pending even when IF=0. */
53#define EMMWAIT_FLAG_BREAKIRQIF0 RT_BIT(1)
54/** Monitor instruction was executed previously. */
55#define EMMWAIT_FLAG_MONITOR_ACTIVE RT_BIT(2)
56/** @} */
57
58/** EM time slice in ms; used for capping execution time. */
59#define EM_TIME_SLICE 100
60
61/**
62 * Cli node structure
63 */
64typedef struct CLISTAT
65{
66 /** The key is the cli address. */
67 AVLGCPTRNODECORE Core;
68#if HC_ARCH_BITS == 32 && !defined(RT_OS_WINDOWS)
69 /** Padding. */
70 uint32_t u32Padding;
71#endif
72 /** Occurrences. */
73 STAMCOUNTER Counter;
74} CLISTAT, *PCLISTAT;
75#ifdef IN_RING3
76AssertCompileMemberAlignment(CLISTAT, Counter, 8);
77#endif
78
79
80/**
81 * Excessive EM statistics.
82 */
83typedef struct EMSTATS
84{
85 /** GC: Profiling of EMInterpretInstruction(). */
86 STAMPROFILE StatRZEmulate;
87 /** HC: Profiling of EMInterpretInstruction(). */
88 STAMPROFILE StatR3Emulate;
89
90 /** @name Interpreter Instruction statistics.
91 * @{
92 */
93 STAMCOUNTER StatRZInterpretSucceeded;
94 STAMCOUNTER StatR3InterpretSucceeded;
95
96 STAMCOUNTER StatRZAnd;
97 STAMCOUNTER StatR3And;
98 STAMCOUNTER StatRZCpuId;
99 STAMCOUNTER StatR3CpuId;
100 STAMCOUNTER StatRZDec;
101 STAMCOUNTER StatR3Dec;
102 STAMCOUNTER StatRZHlt;
103 STAMCOUNTER StatR3Hlt;
104 STAMCOUNTER StatRZInc;
105 STAMCOUNTER StatR3Inc;
106 STAMCOUNTER StatRZInvlPg;
107 STAMCOUNTER StatR3InvlPg;
108 STAMCOUNTER StatRZIret;
109 STAMCOUNTER StatR3Iret;
110 STAMCOUNTER StatRZLLdt;
111 STAMCOUNTER StatR3LLdt;
112 STAMCOUNTER StatRZLIdt;
113 STAMCOUNTER StatR3LIdt;
114 STAMCOUNTER StatRZLGdt;
115 STAMCOUNTER StatR3LGdt;
116 STAMCOUNTER StatRZMov;
117 STAMCOUNTER StatR3Mov;
118 STAMCOUNTER StatRZMovCRx;
119 STAMCOUNTER StatR3MovCRx;
120 STAMCOUNTER StatRZMovDRx;
121 STAMCOUNTER StatR3MovDRx;
122 STAMCOUNTER StatRZOr;
123 STAMCOUNTER StatR3Or;
124 STAMCOUNTER StatRZPop;
125 STAMCOUNTER StatR3Pop;
126 STAMCOUNTER StatRZSti;
127 STAMCOUNTER StatR3Sti;
128 STAMCOUNTER StatRZXchg;
129 STAMCOUNTER StatR3Xchg;
130 STAMCOUNTER StatRZXor;
131 STAMCOUNTER StatR3Xor;
132 STAMCOUNTER StatRZMonitor;
133 STAMCOUNTER StatR3Monitor;
134 STAMCOUNTER StatRZMWait;
135 STAMCOUNTER StatR3MWait;
136 STAMCOUNTER StatRZAdd;
137 STAMCOUNTER StatR3Add;
138 STAMCOUNTER StatRZSub;
139 STAMCOUNTER StatR3Sub;
140 STAMCOUNTER StatRZAdc;
141 STAMCOUNTER StatR3Adc;
142 STAMCOUNTER StatRZRdtsc;
143 STAMCOUNTER StatR3Rdtsc;
144 STAMCOUNTER StatRZRdpmc;
145 STAMCOUNTER StatR3Rdpmc;
146 STAMCOUNTER StatRZBtr;
147 STAMCOUNTER StatR3Btr;
148 STAMCOUNTER StatRZBts;
149 STAMCOUNTER StatR3Bts;
150 STAMCOUNTER StatRZBtc;
151 STAMCOUNTER StatR3Btc;
152 STAMCOUNTER StatRZCmpXchg;
153 STAMCOUNTER StatR3CmpXchg;
154 STAMCOUNTER StatRZCmpXchg8b;
155 STAMCOUNTER StatR3CmpXchg8b;
156 STAMCOUNTER StatRZXAdd;
157 STAMCOUNTER StatR3XAdd;
158 STAMCOUNTER StatRZClts;
159 STAMCOUNTER StatR3Clts;
160 STAMCOUNTER StatRZStosWD;
161 STAMCOUNTER StatR3StosWD;
162 STAMCOUNTER StatR3Rdmsr;
163 STAMCOUNTER StatR3Wrmsr;
164 STAMCOUNTER StatRZRdmsr;
165 STAMCOUNTER StatRZWrmsr;
166 STAMCOUNTER StatRZWbInvd;
167 STAMCOUNTER StatR3WbInvd;
168 STAMCOUNTER StatRZLmsw;
169 STAMCOUNTER StatR3Lmsw;
170 STAMCOUNTER StatRZSmsw;
171 STAMCOUNTER StatR3Smsw;
172
173 STAMCOUNTER StatRZInterpretFailed;
174 STAMCOUNTER StatR3InterpretFailed;
175
176 STAMCOUNTER StatRZFailedAnd;
177 STAMCOUNTER StatR3FailedAnd;
178 STAMCOUNTER StatRZFailedCpuId;
179 STAMCOUNTER StatR3FailedCpuId;
180 STAMCOUNTER StatRZFailedDec;
181 STAMCOUNTER StatR3FailedDec;
182 STAMCOUNTER StatRZFailedHlt;
183 STAMCOUNTER StatR3FailedHlt;
184 STAMCOUNTER StatRZFailedInc;
185 STAMCOUNTER StatR3FailedInc;
186 STAMCOUNTER StatRZFailedInvlPg;
187 STAMCOUNTER StatR3FailedInvlPg;
188 STAMCOUNTER StatRZFailedIret;
189 STAMCOUNTER StatR3FailedIret;
190 STAMCOUNTER StatRZFailedLLdt;
191 STAMCOUNTER StatR3FailedLLdt;
192 STAMCOUNTER StatRZFailedLGdt;
193 STAMCOUNTER StatR3FailedLGdt;
194 STAMCOUNTER StatRZFailedLIdt;
195 STAMCOUNTER StatR3FailedLIdt;
196 STAMCOUNTER StatRZFailedMisc;
197 STAMCOUNTER StatR3FailedMisc;
198 STAMCOUNTER StatRZFailedMov;
199 STAMCOUNTER StatR3FailedMov;
200 STAMCOUNTER StatRZFailedMovCRx;
201 STAMCOUNTER StatR3FailedMovCRx;
202 STAMCOUNTER StatRZFailedMovDRx;
203 STAMCOUNTER StatR3FailedMovDRx;
204 STAMCOUNTER StatRZFailedOr;
205 STAMCOUNTER StatR3FailedOr;
206 STAMCOUNTER StatRZFailedPop;
207 STAMCOUNTER StatR3FailedPop;
208 STAMCOUNTER StatRZFailedSti;
209 STAMCOUNTER StatR3FailedSti;
210 STAMCOUNTER StatRZFailedXchg;
211 STAMCOUNTER StatR3FailedXchg;
212 STAMCOUNTER StatRZFailedXor;
213 STAMCOUNTER StatR3FailedXor;
214 STAMCOUNTER StatRZFailedMonitor;
215 STAMCOUNTER StatR3FailedMonitor;
216 STAMCOUNTER StatRZFailedMWait;
217 STAMCOUNTER StatR3FailedMWait;
218 STAMCOUNTER StatR3FailedRdmsr;
219 STAMCOUNTER StatR3FailedWrmsr;
220 STAMCOUNTER StatRZFailedRdmsr;
221 STAMCOUNTER StatRZFailedWrmsr;
222 STAMCOUNTER StatRZFailedLmsw;
223 STAMCOUNTER StatR3FailedLmsw;
224 STAMCOUNTER StatRZFailedSmsw;
225 STAMCOUNTER StatR3FailedSmsw;
226
227 STAMCOUNTER StatRZFailedAdd;
228 STAMCOUNTER StatR3FailedAdd;
229 STAMCOUNTER StatRZFailedAdc;
230 STAMCOUNTER StatR3FailedAdc;
231 STAMCOUNTER StatRZFailedBtr;
232 STAMCOUNTER StatR3FailedBtr;
233 STAMCOUNTER StatRZFailedBts;
234 STAMCOUNTER StatR3FailedBts;
235 STAMCOUNTER StatRZFailedBtc;
236 STAMCOUNTER StatR3FailedBtc;
237 STAMCOUNTER StatRZFailedCli;
238 STAMCOUNTER StatR3FailedCli;
239 STAMCOUNTER StatRZFailedCmpXchg;
240 STAMCOUNTER StatR3FailedCmpXchg;
241 STAMCOUNTER StatRZFailedCmpXchg8b;
242 STAMCOUNTER StatR3FailedCmpXchg8b;
243 STAMCOUNTER StatRZFailedXAdd;
244 STAMCOUNTER StatR3FailedXAdd;
245 STAMCOUNTER StatR3FailedMovNTPS;
246 STAMCOUNTER StatRZFailedMovNTPS;
247 STAMCOUNTER StatRZFailedStosWD;
248 STAMCOUNTER StatR3FailedStosWD;
249 STAMCOUNTER StatRZFailedSub;
250 STAMCOUNTER StatR3FailedSub;
251 STAMCOUNTER StatRZFailedWbInvd;
252 STAMCOUNTER StatR3FailedWbInvd;
253 STAMCOUNTER StatRZFailedRdtsc;
254 STAMCOUNTER StatR3FailedRdtsc;
255 STAMCOUNTER StatRZFailedRdpmc;
256 STAMCOUNTER StatR3FailedRdpmc;
257 STAMCOUNTER StatRZFailedClts;
258 STAMCOUNTER StatR3FailedClts;
259
260 STAMCOUNTER StatRZFailedUserMode;
261 STAMCOUNTER StatR3FailedUserMode;
262 STAMCOUNTER StatRZFailedPrefix;
263 STAMCOUNTER StatR3FailedPrefix;
264 /** @} */
265
266 /** @name Privileged Instructions Ending Up In HC.
267 * @{ */
268 STAMCOUNTER StatIoRestarted;
269 STAMCOUNTER StatIoIem;
270 STAMCOUNTER StatCli;
271 STAMCOUNTER StatSti;
272 STAMCOUNTER StatInvlpg;
273 STAMCOUNTER StatHlt;
274 STAMCOUNTER StatMovReadCR[DISCREG_CR4 + 1];
275 STAMCOUNTER StatMovWriteCR[DISCREG_CR4 + 1];
276 STAMCOUNTER StatMovDRx;
277 STAMCOUNTER StatIret;
278 STAMCOUNTER StatMovLgdt;
279 STAMCOUNTER StatMovLldt;
280 STAMCOUNTER StatMovLidt;
281 STAMCOUNTER StatMisc;
282 STAMCOUNTER StatSysEnter;
283 STAMCOUNTER StatSysExit;
284 STAMCOUNTER StatSysCall;
285 STAMCOUNTER StatSysRet;
286 /** @} */
287
288} EMSTATS;
289/** Pointer to the excessive EM statistics. */
290typedef EMSTATS *PEMSTATS;
291
292
293/**
294 * Exit history entry.
295 *
296 * @remarks We could perhaps trim this down a little bit by assuming uFlatPC
297 * only needs 48 bits (currently true but will change) and stuffing
298 * the flags+type in the available 16 bits made available. The
299 * timestamp could likewise be shortened to accomodate the index, or
300 * we might skip the index entirely. However, since we will have to
301 * deal with 56-bit wide PC address before long, there's not point.
302 *
303 * On the upside, there are unused bits in both uFlagsAndType and the
304 * idxSlot fields if needed for anything.
305 */
306typedef struct EMEXITENTRY
307{
308 /** The flat PC (CS:EIP/RIP) address of the exit.
309 * UINT64_MAX if not available. */
310 uint64_t uFlatPC;
311 /** The EMEXIT_MAKE_FLAGS_AND_TYPE */
312 uint32_t uFlagsAndType;
313 /** The index into the exit slot hash table.
314 * UINT32_MAX if too many collisions and not entered into it. */
315 uint32_t idxSlot;
316 /** The TSC timestamp of the exit.
317 * This is 0 if not timestamped. */
318 uint64_t uTimestamp;
319} EMEXITENTRY;
320/** Pointer to an exit history entry. */
321typedef EMEXITENTRY *PEMEXITENTRY;
322/** Pointer to a const exit history entry. */
323typedef EMEXITENTRY const *PCEMEXITENTRY;
324
325
326/**
327 * Converts a EM pointer into a VM pointer.
328 * @returns Pointer to the VM structure the EM is part of.
329 * @param pEM Pointer to EM instance data.
330 */
331#define EM2VM(pEM) ( (PVM)((char*)pEM - pEM->offVM) )
332
333/**
334 * EM VM Instance data.
335 * Changes to this must checked against the padding of the cfgm union in VM!
336 */
337typedef struct EM
338{
339 /** Offset to the VM structure.
340 * See EM2VM(). */
341 RTUINT offVM;
342
343 /** Whether IEM executes everything. */
344 bool fIemExecutesAll;
345 /** Whether a triple fault triggers a guru. */
346 bool fGuruOnTripleFault;
347 /** Alignment padding. */
348 bool afPadding[6];
349
350 /** Id of the VCPU that last executed code in the recompiler. */
351 VMCPUID idLastRemCpu;
352
353#ifdef VBOX_WITH_REM
354 /** REM critical section.
355 * This protects recompiler usage
356 */
357 PDMCRITSECT CritSectREM;
358#endif
359} EM;
360/** Pointer to EM VM instance data. */
361typedef EM *PEM;
362
363
364/**
365 * EM VMCPU Instance data.
366 */
367typedef struct EMCPU
368{
369 /** Execution Manager State. */
370 EMSTATE volatile enmState;
371
372 /** The state prior to the suspending of the VM. */
373 EMSTATE enmPrevState;
374
375 /** Force raw-mode execution.
376 * This is used to prevent REM from trying to execute patch code.
377 * The flag is cleared upon entering emR3RawExecute() and updated in certain return paths. */
378 bool fForceRAW;
379
380 /** Set if hypercall instruction VMMCALL (AMD) & VMCALL (Intel) are enabled.
381 * GIM sets this and the execution managers queries it. Not saved, as GIM
382 * takes care of that bit too. */
383 bool fHypercallEnabled;
384
385 /** Explicit padding. */
386 uint8_t abPadding[2];
387
388 /** The number of instructions we've executed in IEM since switching to the
389 * EMSTATE_IEM_THEN_REM state. */
390 uint32_t cIemThenRemInstructions;
391
392 /** Inhibit interrupts for this instruction. Valid only when VM_FF_INHIBIT_INTERRUPTS is set. */
393 RTGCUINTPTR GCPtrInhibitInterrupts;
394
395#ifdef VBOX_WITH_RAW_MODE
396 /** Pointer to the PATM status structure. (R3 Ptr) */
397 R3PTRTYPE(PPATMGCSTATE) pPatmGCState;
398#else
399 RTR3PTR R3PtrPaddingNoRaw;
400#endif
401
402 /** Pointer to the guest CPUM state. (R3 Ptr) */
403 R3PTRTYPE(PCPUMCTX) pCtx;
404
405#if GC_ARCH_BITS == 64
406 RTGCPTR aPadding1;
407#endif
408
409 /** Start of the current time slice in ms. */
410 uint64_t u64TimeSliceStart;
411 /** Start of the current time slice in thread execution time (ms). */
412 uint64_t u64TimeSliceStartExec;
413 /** Current time slice value. */
414 uint64_t u64TimeSliceExec;
415
416 /** Pending ring-3 I/O port access (VINF_EM_PENDING_R3_IOPORT_READ / VINF_EM_PENDING_R3_IOPORT_WRITE). */
417 struct
418 {
419 RTIOPORT uPort; /**< The I/O port number.*/
420 uint8_t cbValue; /**< The value size in bytes. Zero when not pending. */
421 uint8_t cbInstr; /**< The instruction length. */
422 uint32_t uValue; /**< The value to write. */
423 } PendingIoPortAccess;
424
425 /** MWait halt state. */
426 struct
427 {
428 uint32_t fWait; /**< Type of mwait; see EMMWAIT_FLAG_*. */
429 uint32_t u32Padding;
430 RTGCPTR uMWaitRAX; /**< MWAIT hints. */
431 RTGCPTR uMWaitRCX; /**< MWAIT extensions. */
432 RTGCPTR uMonitorRAX; /**< Monitored address. */
433 RTGCPTR uMonitorRCX; /**< Monitor extension. */
434 RTGCPTR uMonitorRDX; /**< Monitor hint. */
435 } MWait;
436
437 union
438 {
439 /** Padding used in the other rings.
440 * This must be larger than jmp_buf on any supported platform. */
441 char achPaddingFatalLongJump[HC_ARCH_BITS == 32 ? 176 : 256];
442#ifdef IN_RING3
443 /** Long buffer jump for fatal VM errors.
444 * It will jump to before the outer EM loop is entered. */
445 jmp_buf FatalLongJump;
446#endif
447 } u;
448
449 /** For saving stack space, the disassembler state is allocated here instead of
450 * on the stack. */
451 DISCPUSTATE DisState;
452
453 /** @name Execution profiling.
454 * @{ */
455 STAMPROFILE StatForcedActions;
456 STAMPROFILE StatHalted;
457 STAMPROFILEADV StatCapped;
458 STAMPROFILEADV StatHMEntry;
459 STAMPROFILE StatHMExec;
460 STAMPROFILE StatIEMEmu;
461 STAMPROFILE StatIEMThenREM;
462 STAMPROFILEADV StatNEMEntry;
463 STAMPROFILE StatNEMExec;
464 STAMPROFILE StatREMEmu;
465 STAMPROFILE StatREMExec;
466 STAMPROFILE StatREMSync;
467 STAMPROFILEADV StatREMTotal;
468 STAMPROFILE StatRAWExec;
469 STAMPROFILEADV StatRAWEntry;
470 STAMPROFILEADV StatRAWTail;
471 STAMPROFILEADV StatRAWTotal;
472 STAMPROFILEADV StatTotal;
473 /** @} */
474
475 /** R3: Profiling of emR3RawExecuteIOInstruction. */
476 STAMPROFILE StatIOEmu;
477 /** R3: Profiling of emR3RawPrivileged. */
478 STAMPROFILE StatPrivEmu;
479 /** R3: Number of times emR3HmExecute is called. */
480 STAMCOUNTER StatHMExecuteCalled;
481 /** R3: Number of times emR3NEMExecute is called. */
482 STAMCOUNTER StatNEMExecuteCalled;
483
484 /** More statistics (R3). */
485 R3PTRTYPE(PEMSTATS) pStatsR3;
486 /** More statistics (R0). */
487 R0PTRTYPE(PEMSTATS) pStatsR0;
488 /** More statistics (RC). */
489 RCPTRTYPE(PEMSTATS) pStatsRC;
490#if HC_ARCH_BITS == 64
491 RTRCPTR padding0;
492#endif
493
494 /** Tree for keeping track of cli occurrences (debug only). */
495 R3PTRTYPE(PAVLGCPTRNODECORE) pCliStatTree;
496 STAMCOUNTER StatTotalClis;
497#if HC_ARCH_BITS == 32
498 uint64_t padding1;
499#endif
500
501 /** Where to store the next exit history entry.
502 * Since aExitHistory is 256 items longs, we'll just increment this and
503 * mask it when using it. That help the readers detect whether we've
504 * wrapped around or not. */
505 uint64_t iNextExit;
506 /** Exit history table (6KB). */
507 EMEXITENTRY aExitHistory[256];
508 /** Number of exit records in use. */
509 uint32_t cExitRecordUsed;
510 /** Number of exit records collisions. */
511 uint32_t cExitRecordCollisions;
512 /** Exit records (32KB). (Aligned on 32 byte boundrary.) */
513 EMEXITREC aExitRecords[1024];
514} EMCPU;
515/** Pointer to EM VM instance data. */
516typedef EMCPU *PEMCPU;
517
518/** @} */
519
520int emR3InitDbg(PVM pVM);
521
522int emR3HmExecute(PVM pVM, PVMCPU pVCpu, bool *pfFFDone);
523VBOXSTRICTRC emR3NemExecute(PVM pVM, PVMCPU pVCpu, bool *pfFFDone);
524int emR3RawExecute(PVM pVM, PVMCPU pVCpu, bool *pfFFDone);
525
526int emR3RawHandleRC(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx, int rc);
527int emR3HmHandleRC(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx, int rc);
528int emR3NemHandleRC(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx, int rc);
529
530EMSTATE emR3Reschedule(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx);
531int emR3ForcedActions(PVM pVM, PVMCPU pVCpu, int rc);
532VBOXSTRICTRC emR3HighPriorityPostForcedActions(PVM pVM, PVMCPU pVCpu, VBOXSTRICTRC rc);
533
534int emR3RawUpdateForceFlag(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx, int rc);
535int emR3RawResumeHyper(PVM pVM, PVMCPU pVCpu);
536int emR3RawStep(PVM pVM, PVMCPU pVCpu);
537
538VBOXSTRICTRC emR3NemSingleInstruction(PVM pVM, PVMCPU pVCpu, uint32_t fFlags);
539
540int emR3SingleStepExecRem(PVM pVM, PVMCPU pVCpu, uint32_t cIterations);
541
542bool emR3IsExecutionAllowed(PVM pVM, PVMCPU pVCpu);
543
544VBOXSTRICTRC emR3ExecutePendingIoPortWrite(PVM pVM, PVMCPU pVCpu);
545VBOXSTRICTRC emR3ExecutePendingIoPortRead(PVM pVM, PVMCPU pVCpu);
546
547RT_C_DECLS_END
548
549#endif
550
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