| 1 | /* $Id: GICInternal.h 107984 2025-01-30 06:43:18Z vboxsync $ */
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| 2 | /** @file
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| 3 | * GIC - Generic Interrupt Controller Architecture (GIC).
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| 4 | */
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| 5 |
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| 6 | /*
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| 7 | * Copyright (C) 2023-2024 Oracle and/or its affiliates.
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| 8 | *
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| 9 | * This file is part of VirtualBox base platform packages, as
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| 10 | * available from https://www.virtualbox.org.
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| 11 | *
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| 12 | * This program is free software; you can redistribute it and/or
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| 13 | * modify it under the terms of the GNU General Public License
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| 14 | * as published by the Free Software Foundation, in version 3 of the
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| 15 | * License.
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| 16 | *
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| 17 | * This program is distributed in the hope that it will be useful, but
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| 18 | * WITHOUT ANY WARRANTY; without even the implied warranty of
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| 19 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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| 20 | * General Public License for more details.
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| 21 | *
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| 22 | * You should have received a copy of the GNU General Public License
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| 23 | * along with this program; if not, see <https://www.gnu.org/licenses>.
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| 24 | *
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| 25 | * SPDX-License-Identifier: GPL-3.0-only
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| 26 | */
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| 27 |
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| 28 | #ifndef VMM_INCLUDED_SRC_include_GICInternal_h
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| 29 | #define VMM_INCLUDED_SRC_include_GICInternal_h
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| 30 | #ifndef RT_WITHOUT_PRAGMA_ONCE
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| 31 | # pragma once
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| 32 | #endif
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| 33 |
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| 34 | #include <VBox/gic.h>
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| 35 | #include <VBox/vmm/pdmdev.h>
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| 36 | #include <VBox/vmm/pdmgic.h>
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| 37 | #include <VBox/vmm/stam.h>
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| 38 |
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| 39 |
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| 40 | /** @defgroup grp_gic_int Internal
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| 41 | * @ingroup grp_gic
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| 42 | * @internal
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| 43 | * @{
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| 44 | */
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| 45 |
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| 46 | #ifdef VBOX_INCLUDED_vmm_pdmgic_h
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| 47 | /** The VirtualBox GIC backend. */
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| 48 | extern const PDMGICBACKEND g_GicBackend;
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| 49 | # ifdef RT_OS_DARWIN
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| 50 | /** The Hypervisor.Framework GIC backend. */
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| 51 | extern const PDMGICBACKEND g_GicHvfBackend;
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| 52 | # elif defined(RT_OS_WINDOWS)
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| 53 | /** The Hyper-V GIC backend. */
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| 54 | extern const PDMGICBACKEND g_GicHvBackend;
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| 55 | # endif
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| 56 | #endif
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| 57 |
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| 58 | #define VMCPU_TO_GICCPU(a_pVCpu) (&(a_pVCpu)->gic.s)
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| 59 | #define VM_TO_GIC(a_pVM) (&(a_pVM)->gic.s)
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| 60 | #define VM_TO_GICDEV(a_pVM) CTX_SUFF(VM_TO_GIC(a_pVM)->pGicDev)
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| 61 | #ifdef IN_RING3
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| 62 | # define VMCPU_TO_DEVINS(a_pVCpu) ((a_pVCpu)->pVMR3->gic.s.pDevInsR3)
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| 63 | #elif defined(IN_RING0)
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| 64 | # error "Not implemented!"
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| 65 | #endif
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| 66 |
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| 67 | /** Maximum number of SPI interrupts. */
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| 68 | #define GIC_SPI_MAX 32
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| 69 |
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| 70 | /**
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| 71 | * GIC PDM instance data (per-VM).
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| 72 | */
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| 73 | typedef struct GICDEV
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| 74 | {
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| 75 | /** The distributor MMIO handle. */
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| 76 | IOMMMIOHANDLE hMmioDist;
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| 77 | /** The redistributor MMIO handle. */
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| 78 | IOMMMIOHANDLE hMmioReDist;
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| 79 |
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| 80 | /** @name SPI distributor register state.
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| 81 | * @{ */
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| 82 | /** Interrupt Group 0 Register. */
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| 83 | volatile uint32_t u32RegIGrp0;
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| 84 | /** Interrupt Configuration Register 0. */
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| 85 | volatile uint32_t u32RegICfg0;
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| 86 | /** Interrupt Configuration Register 1. */
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| 87 | volatile uint32_t u32RegICfg1;
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| 88 | /** Interrupt enabled bitmap. */
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| 89 | volatile uint32_t bmIntEnabled;
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| 90 | /** Current interrupt pending state. */
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| 91 | volatile uint32_t bmIntPending;
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| 92 | /** The current interrupt active state. */
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| 93 | volatile uint32_t bmIntActive;
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| 94 | /** The interrupt priority for each of the SGI/PPIs */
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| 95 | volatile uint8_t abIntPriority[GIC_SPI_MAX];
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| 96 | /** The interrupt routing information. */
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| 97 | volatile uint32_t au32IntRouting[GIC_SPI_MAX];
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| 98 |
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| 99 | /** Flag whether group 0 interrupts are currently enabled. */
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| 100 | volatile bool fIrqGrp0Enabled;
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| 101 | /** Flag whether group 1 interrupts are currently enabled. */
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| 102 | volatile bool fIrqGrp1Enabled;
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| 103 | /** @} */
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| 104 |
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| 105 | /** @name Configurables.
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| 106 | * @{ */
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| 107 | /** The GIC architecture (GICD_PIDR2.ArchRev and GICR_PIDR2.ArchRev). */
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| 108 | uint8_t uArchRev;
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| 109 | /** Extended PPIs supported (GICR_TYPER.PpiNum). */
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| 110 | uint8_t fPpiNum;
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| 111 | /** Whether extended SPIs are supported (GICD_TYPER.ESPI). */
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| 112 | bool fExtSpi;
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| 113 | /** Whether NMIs are supported (GICD_TYPER.NMI). */
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| 114 | bool fNmi;
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| 115 | /** The maximum SPI supported (GICD_TYPER.ItsLinesNumber). */
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| 116 | uint16_t uMaxSpi;
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| 117 | /** Maximum extended SPI supported (GICR_TYPER.ESPI_range). */
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| 118 | uint16_t uMaxExtSpi;
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| 119 | /** @} */
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| 120 | } GICDEV;
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| 121 | /** Pointer to a GIC device. */
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| 122 | typedef GICDEV *PGICDEV;
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| 123 | /** Pointer to a const GIC device. */
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| 124 | typedef GICDEV const *PCGICDEV;
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| 125 |
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| 126 |
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| 127 | /**
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| 128 | * GIC VM Instance data.
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| 129 | */
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| 130 | typedef struct GIC
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| 131 | {
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| 132 | /** The ring-3 device instance. */
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| 133 | PPDMDEVINSR3 pDevInsR3;
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| 134 | } GIC;
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| 135 | /** Pointer to GIC VM instance data. */
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| 136 | typedef GIC *PGIC;
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| 137 | /** Pointer to const GIC VM instance data. */
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| 138 | typedef GIC const *PCGIC;
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| 139 | AssertCompileSizeAlignment(GIC, 8);
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| 140 |
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| 141 | /**
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| 142 | * GIC VMCPU Instance data.
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| 143 | */
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| 144 | typedef struct GICCPU
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| 145 | {
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| 146 | /** @name The per vCPU redistributor data is kept here.
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| 147 | * @{ */
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| 148 | /** @} */
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| 149 |
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| 150 | /** @name Physical LPI register state.
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| 151 | * @{ */
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| 152 | /** @} */
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| 153 |
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| 154 | /** @name SGI and PPI redistributor register state.
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| 155 | * @{ */
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| 156 | /** Interrupt Group 0 Register. */
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| 157 | volatile uint32_t u32RegIGrp0;
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| 158 | /** Interrupt Configuration Register 0. */
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| 159 | volatile uint32_t u32RegICfg0;
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| 160 | /** Interrupt Configuration Register 1. */
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| 161 | volatile uint32_t u32RegICfg1;
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| 162 | /** Interrupt enabled bitmap. */
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| 163 | volatile uint32_t bmIntEnabled;
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| 164 | /** Current interrupt pending state. */
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| 165 | volatile uint32_t bmIntPending;
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| 166 | /** The current interrupt active state. */
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| 167 | volatile uint32_t bmIntActive;
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| 168 | /** The interrupt priority for each of the SGI/PPIs */
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| 169 | volatile uint8_t abIntPriority[GIC_INTID_RANGE_PPI_LAST + 1];
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| 170 | /** @} */
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| 171 |
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| 172 | /** @name ICC system register state.
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| 173 | * @{ */
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| 174 | /** Flag whether group 0 interrupts are currently enabled. */
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| 175 | volatile bool fIrqGrp0Enabled;
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| 176 | /** Flag whether group 1 interrupts are currently enabled. */
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| 177 | volatile bool fIrqGrp1Enabled;
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| 178 | /** The current interrupt priority, only interrupts with a higher priority get signalled. */
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| 179 | volatile uint8_t bInterruptPriority;
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| 180 | /** The interrupt controller Binary Point Register for Group 0 interrupts. */
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| 181 | uint8_t bBinaryPointGrp0;
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| 182 | /** The interrupt controller Binary Point Register for Group 1 interrupts. */
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| 183 | uint8_t bBinaryPointGrp1;
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| 184 | /** The running priorities caused by preemption. */
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| 185 | volatile uint8_t abRunningPriorities[256];
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| 186 | /** The index to the current running priority. */
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| 187 | volatile uint8_t idxRunningPriority;
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| 188 | /** @} */
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| 189 |
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| 190 | /** @name Log Max counters
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| 191 | * @{ */
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| 192 | uint32_t cLogMaxAccessError;
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| 193 | uint32_t cLogMaxSetApicBaseAddr;
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| 194 | uint32_t cLogMaxGetApicBaseAddr;
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| 195 | uint32_t uAlignment4;
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| 196 | /** @} */
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| 197 |
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| 198 | /** @name APIC statistics.
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| 199 | * @{ */
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| 200 | #ifdef VBOX_WITH_STATISTICS
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| 201 | /** Number of MMIO reads in R3. */
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| 202 | STAMCOUNTER StatMmioReadR3;
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| 203 | /** Number of MMIO writes in R3. */
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| 204 | STAMCOUNTER StatMmioWriteR3;
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| 205 | /** Number of MSR reads in R3. */
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| 206 | STAMCOUNTER StatSysRegReadR3;
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| 207 | /** Number of MSR writes in R3. */
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| 208 | STAMCOUNTER StatSysRegWriteR3;
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| 209 |
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| 210 | # if 0 /* No R0 for now. */
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| 211 | /** Number of MMIO reads in RZ. */
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| 212 | STAMCOUNTER StatMmioReadRZ;
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| 213 | /** Number of MMIO writes in RZ. */
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| 214 | STAMCOUNTER StatMmioWriteRZ;
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| 215 | /** Number of MSR reads in RZ. */
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| 216 | STAMCOUNTER StatSysRegReadRZ;
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| 217 | /** Number of MSR writes in RZ. */
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| 218 | STAMCOUNTER StatSysRegWriteRZ;
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| 219 | # endif
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| 220 | #endif
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| 221 | /** @} */
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| 222 | } GICCPU;
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| 223 | /** Pointer to GIC VMCPU instance data. */
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| 224 | typedef GICCPU *PGICCPU;
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| 225 | /** Pointer to a const GIC VMCPU instance data. */
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| 226 | typedef GICCPU const *PCGICCPU;
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| 227 |
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| 228 | DECL_HIDDEN_CALLBACK(VBOXSTRICTRC) gicDistMmioRead(PPDMDEVINS pDevIns, void *pvUser, RTGCPHYS off, void *pv, unsigned cb);
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| 229 | DECL_HIDDEN_CALLBACK(VBOXSTRICTRC) gicDistMmioWrite(PPDMDEVINS pDevIns, void *pvUser, RTGCPHYS off, void const *pv, unsigned cb);
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| 230 |
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| 231 | DECL_HIDDEN_CALLBACK(VBOXSTRICTRC) gicReDistMmioRead(PPDMDEVINS pDevIns, void *pvUser, RTGCPHYS off, void *pv, unsigned cb);
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| 232 | DECL_HIDDEN_CALLBACK(VBOXSTRICTRC) gicReDistMmioWrite(PPDMDEVINS pDevIns, void *pvUser, RTGCPHYS off, void const *pv, unsigned cb);
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| 233 |
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| 234 | DECLHIDDEN(void) gicResetCpu(PVMCPUCC pVCpu);
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| 235 |
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| 236 | DECLCALLBACK(int) gicR3Construct(PPDMDEVINS pDevIns, int iInstance, PCFGMNODE pCfg);
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| 237 | DECLCALLBACK(int) gicR3Destruct(PPDMDEVINS pDevIns);
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| 238 | DECLCALLBACK(void) gicR3Relocate(PPDMDEVINS pDevIns, RTGCINTPTR offDelta);
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| 239 | DECLCALLBACK(void) gicR3Reset(PPDMDEVINS pDevIns);
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| 240 |
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| 241 | /** @} */
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| 242 |
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| 243 | #endif /* !VMM_INCLUDED_SRC_include_GICInternal_h */
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| 244 |
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