VirtualBox

source: vbox/trunk/src/VBox/VMM/include/GICInternal.h@ 108483

Last change on this file since 108483 was 108483, checked in by vboxsync, 2 months ago

VMM/GIC: bugref:10404 CFGM leaf validation nits and rename.
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1/* $Id: GICInternal.h 108483 2025-03-10 07:00:57Z vboxsync $ */
2/** @file
3 * GIC - Generic Interrupt Controller Architecture (GIC).
4 */
5
6/*
7 * Copyright (C) 2023-2024 Oracle and/or its affiliates.
8 *
9 * This file is part of VirtualBox base platform packages, as
10 * available from https://www.virtualbox.org.
11 *
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License
14 * as published by the Free Software Foundation, in version 3 of the
15 * License.
16 *
17 * This program is distributed in the hope that it will be useful, but
18 * WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
20 * General Public License for more details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, see <https://www.gnu.org/licenses>.
24 *
25 * SPDX-License-Identifier: GPL-3.0-only
26 */
27
28#ifndef VMM_INCLUDED_SRC_include_GICInternal_h
29#define VMM_INCLUDED_SRC_include_GICInternal_h
30#ifndef RT_WITHOUT_PRAGMA_ONCE
31# pragma once
32#endif
33
34#include <VBox/gic.h>
35#include <VBox/vmm/pdmdev.h>
36#include <VBox/vmm/pdmgic.h>
37#include <VBox/vmm/stam.h>
38
39
40/** @defgroup grp_gic_int Internal
41 * @ingroup grp_gic
42 * @internal
43 * @{
44 */
45
46#ifdef VBOX_INCLUDED_vmm_pdmgic_h
47/** The VirtualBox GIC backend. */
48extern const PDMGICBACKEND g_GicBackend;
49# ifdef RT_OS_DARWIN
50/** The Hypervisor.Framework GIC backend. */
51extern const PDMGICBACKEND g_GicHvfBackend;
52# elif defined(RT_OS_WINDOWS)
53/** The Hyper-V GIC backend. */
54extern const PDMGICBACKEND g_GicHvBackend;
55# elif defined(RT_OS_LINUX)
56/** The KVM GIC backend. */
57extern const PDMGICBACKEND g_GicKvmBackend;
58# endif
59#endif
60
61#define VMCPU_TO_GICCPU(a_pVCpu) (&(a_pVCpu)->gic.s)
62#define VM_TO_GIC(a_pVM) (&(a_pVM)->gic.s)
63#define VM_TO_GICDEV(a_pVM) CTX_SUFF(VM_TO_GIC(a_pVM)->pGicDev)
64#ifdef IN_RING3
65# define VMCPU_TO_DEVINS(a_pVCpu) ((a_pVCpu)->pVMR3->gic.s.pDevInsR3)
66#elif defined(IN_RING0)
67# error "Not implemented!"
68#endif
69
70#if 0
71/** Maximum number of SPI interrupts. */
72#define GIC_SPI_MAX 32
73#endif
74
75#if 0
76/** @def GIC_CACHE_LINE_SIZE
77 * Padding (in bytes) for aligning data in different cache lines. The ARMv8 cache
78 * line size is 64 bytes.
79 *
80 * See ARM spec "Cache Size ID Register, CCSIDR_EL1".
81 */
82#define GIC_CACHE_LINE_SIZE 64
83
84/**
85 * GIC Interrupt-Delivery Bitmap (IDB).
86 */
87typedef struct GICIDB
88{
89 uint64_t volatile au64IntIdBitmap[33];
90 uint32_t volatile fOutstandingNotification;
91 uint8_t abAlignment[52];
92} GICIDB;
93AssertCompileMemberOffset(GICIDB, fOutstandingNotification, 264);
94AssertCompileSizeAlignment(GICIDB, GIC_CACHE_LINE_SIZE);
95/** Pointer to a pending-interrupt bitmap. */
96typedef GICIDB *PGICIDB;
97/** Pointer to a const pending-interrupt bitmap. */
98typedef const GICIDB *PCGICIDB;
99#endif
100
101/**
102 * GIC PDM instance data (per-VM).
103 */
104typedef struct GICDEV
105{
106 /** The distributor MMIO handle. */
107 IOMMMIOHANDLE hMmioDist;
108 /** The redistributor MMIO handle. */
109 IOMMMIOHANDLE hMmioReDist;
110
111 /** @name Distributor register state.
112 * @{
113 */
114#if 1
115 /** Interrupt group bitmap. */
116 uint32_t bmIntrGroup[64];
117 /** Interrupt config bitmap (edge-triggered vs level-sensitive). */
118 uint32_t bmIntrConfig[128];
119 /** Interrupt enabled bitmap. */
120 uint32_t bmIntrEnabled[64];
121 /** Interrupt pending bitmap. */
122 uint32_t bmIntrPending[64];
123 /** Interrupt active bitmap. */
124 uint32_t bmIntrActive[64];
125 /** Interrupt priorities. */
126 uint8_t abIntrPriority[2048];
127 /** Interrupt routing info. */
128 uint32_t au32IntrRouting[2048];
129 /** Interrupt routine mode bitmap. */
130 uint32_t bmIntrRoutingMode[64];
131
132 /** Flag whether group 0 interrupts are enabled. */
133 bool fIntrGroup0Enabled;
134 /** Flag whether group 1 interrupts are enabled. */
135 bool fIntrGroup1Enabled;
136 /** Flag whether affinity routing is enabled. */
137 bool fAffRoutingEnabled;
138 /** Alignment. */
139 bool fAlignment0;
140 /** @} */
141#else
142 /** @name SPI distributor register state.
143 * @{ */
144 /** Interrupt Group 0 Register. */
145 volatile uint32_t u32RegIGrp0;
146 /** Interrupt Configuration Register 0. */
147 volatile uint32_t u32RegICfg0;
148 /** Interrupt Configuration Register 1. */
149 volatile uint32_t u32RegICfg1;
150 /** Interrupt enabled bitmap. */
151 volatile uint32_t bmIntEnabled;
152 /** Current interrupt pending state. */
153 volatile uint32_t bmIntPending;
154 /** The current interrupt active state. */
155 volatile uint32_t bmIntActive;
156 /** The interrupt priority for each of the SGI/PPIs */
157 volatile uint8_t abIntPriority[GIC_SPI_MAX];
158 /** The interrupt routing information. */
159 volatile uint32_t au32IntRouting[GIC_SPI_MAX];
160
161 /** Flag whether group 0 interrupts are currently enabled. */
162 volatile bool fIrqGrp0Enabled;
163 /** Flag whether group 1 interrupts are currently enabled. */
164 volatile bool fIrqGrp1Enabled;
165 /** @} */
166#endif
167
168 /** @name Configurables.
169 * @{ */
170 /** The GIC architecture (GICD_PIDR2.ArchRev and GICR_PIDR2.ArchRev). */
171 uint8_t uArchRev;
172 /** The maximum SPI supported (GICD_TYPER.ItLinesNumber). */
173 uint8_t uMaxSpi;
174 /** Whether extended SPIs are supported (GICD_ESPI). */
175 bool fExtSpi;
176 /** The maximum extended SPI supported (GICD_TYPER.ESPI_range). */
177 uint8_t uMaxExtSpi;
178 /** Whether extended PPIs are supported. */
179 bool fExtPpi;
180 /** The maximum extended PPI supported (GICR_TYPER.PPInum). */
181 uint8_t uMaxExtPpi;
182 /** Whether range-selector is supported (GICD_TYPER.RSS and ICC_CTLR_EL1.RSS). */
183 bool fRangeSel;
184 /** Whether NMIs are supported (GICD_TYPER.NMI). */
185 bool fNmi;
186 /** Whether message-based interrupts are supported (GICD_TYPER.MBIS). */
187 bool fMbi;
188 /** Alignment. */
189 bool afPadding[3];
190 /** @} */
191} GICDEV;
192/** Pointer to a GIC device. */
193typedef GICDEV *PGICDEV;
194/** Pointer to a const GIC device. */
195typedef GICDEV const *PCGICDEV;
196
197/**
198 * GIC VM Instance data.
199 */
200typedef struct GIC
201{
202 /** The ring-3 device instance. */
203 PPDMDEVINSR3 pDevInsR3;
204} GIC;
205/** Pointer to GIC VM instance data. */
206typedef GIC *PGIC;
207/** Pointer to const GIC VM instance data. */
208typedef GIC const *PCGIC;
209AssertCompileSizeAlignment(GIC, 8);
210
211/**
212 * GIC VMCPU Instance data.
213 */
214typedef struct GICCPU
215{
216 /** @name Redistributor register state.
217 * @{ */
218#if 1
219 /** Interrupt group bitmap. */
220 uint32_t bmIntrGroup[3];
221 /** Interrupt config bitmap (edge-triggered vs level-sensitive). */
222 uint32_t bmIntrConfig[6];
223 /** Interrupt enabled bitmap. */
224 uint32_t bmIntrEnabled[3];
225 /** Interrupt pending bitmap. */
226 uint32_t bmIntrPending[3];
227 /** Interrupt active bitmap. */
228 uint32_t bmIntrActive[3];
229 /** Interrupt priorities. */
230 uint8_t abIntrPriority[96];
231#else
232 /** Interrupt Group 0 Register. */
233 volatile uint32_t u32RegIGrp0;
234 /** Interrupt Configuration Register 0. */
235 volatile uint32_t u32RegICfg0;
236 /** Interrupt Configuration Register 1. */
237 volatile uint32_t u32RegICfg1;
238 /** Interrupt enabled bitmap. */
239 volatile uint32_t bmIntEnabled;
240 /** Current interrupt pending state. */
241 volatile uint32_t bmIntPending;
242 /** The current interrupt active state. */
243 volatile uint32_t bmIntActive;
244 /** The interrupt priority for each of the SGI/PPIs */
245 volatile uint8_t abIntPriority[GIC_INTID_RANGE_PPI_LAST + 1];
246#endif
247 /** @} */
248
249 /** @name ICC system register state.
250 * @{ */
251 /** The control register (ICC_CTLR_EL1). */
252 uint64_t uIccCtlr;
253 /** The interrupt priority mask of the CPU interface (ICC_PMR_EL1). */
254 uint8_t bIntrPriorityMask;
255 /** The index to the current running priority. */
256 uint8_t idxRunningPriority;
257 /** The running priorities caused by preemption. */
258 uint8_t abRunningPriorities[256];
259 /** The active priorities group 0 bitmap. */
260 uint32_t bmActivePriorityGroup0[4];
261 /** The active priorities group 0 bitmap. */
262 uint32_t bmActivePriorityGroup1[4];
263 /** The binary point register for group 0 interrupts. */
264 uint8_t bBinaryPtGroup0;
265 /** The binary point register for group 1 interrupts. */
266 uint8_t bBinaryPtGroup1;
267 /** Flag whether group 0 interrupts are enabled. */
268 bool fIntrGroup0Enabled;
269 /** Flag whether group 1 interrupts are enabled. */
270 bool fIntrGroup1Enabled;
271 /** @} */
272
273 /** @name Log Max counters
274 * @{ */
275 uint32_t cLogMaxAccessError;
276 uint32_t cLogMaxSetApicBaseAddr;
277 uint32_t cLogMaxGetApicBaseAddr;
278 uint32_t uAlignment4;
279 /** @} */
280
281 /** @name APIC statistics.
282 * @{ */
283#ifdef VBOX_WITH_STATISTICS
284 /** Number of MMIO reads in R3. */
285 STAMCOUNTER StatMmioReadR3;
286 /** Number of MMIO writes in R3. */
287 STAMCOUNTER StatMmioWriteR3;
288 /** Number of MSR reads in R3. */
289 STAMCOUNTER StatSysRegReadR3;
290 /** Number of MSR writes in R3. */
291 STAMCOUNTER StatSysRegWriteR3;
292 /** Number of set SPI callbacks. */
293 STAMCOUNTER StatSetSpiR3;
294 /** Number of set PPI callbacks. */
295 STAMCOUNTER StatSetPpiR3;
296
297# if 0 /* No R0 for now. */
298 /** Number of MMIO reads in RZ. */
299 STAMCOUNTER StatMmioReadRZ;
300 /** Number of MMIO writes in RZ. */
301 STAMCOUNTER StatMmioWriteRZ;
302 /** Number of MSR reads in RZ. */
303 STAMCOUNTER StatSysRegReadRZ;
304 /** Number of MSR writes in RZ. */
305 STAMCOUNTER StatSysRegWriteRZ;
306# endif
307#endif
308 /** @} */
309} GICCPU;
310/** Pointer to GIC VMCPU instance data. */
311typedef GICCPU *PGICCPU;
312/** Pointer to a const GIC VMCPU instance data. */
313typedef GICCPU const *PCGICCPU;
314
315DECL_HIDDEN_CALLBACK(VBOXSTRICTRC) gicDistMmioRead(PPDMDEVINS pDevIns, void *pvUser, RTGCPHYS off, void *pv, unsigned cb);
316DECL_HIDDEN_CALLBACK(VBOXSTRICTRC) gicDistMmioWrite(PPDMDEVINS pDevIns, void *pvUser, RTGCPHYS off, void const *pv, unsigned cb);
317DECL_HIDDEN_CALLBACK(VBOXSTRICTRC) gicReDistMmioRead(PPDMDEVINS pDevIns, void *pvUser, RTGCPHYS off, void *pv, unsigned cb);
318DECL_HIDDEN_CALLBACK(VBOXSTRICTRC) gicReDistMmioWrite(PPDMDEVINS pDevIns, void *pvUser, RTGCPHYS off, void const *pv, unsigned cb);
319
320DECLHIDDEN(void) gicResetCpu(PPDMDEVINS pDevIns, PVMCPUCC pVCpu);
321DECLHIDDEN(void) gicReset(PPDMDEVINS pDevIns);
322DECLHIDDEN(uint16_t) gicReDistGetIntIdFromIndex(uint16_t idxIntr);
323DECLHIDDEN(uint16_t) gicDistGetIntIdFromIndex(uint16_t idxIntr);
324
325DECLCALLBACK(int) gicR3Construct(PPDMDEVINS pDevIns, int iInstance, PCFGMNODE pCfg);
326DECLCALLBACK(int) gicR3Destruct(PPDMDEVINS pDevIns);
327DECLCALLBACK(void) gicR3Relocate(PPDMDEVINS pDevIns, RTGCINTPTR offDelta);
328DECLCALLBACK(void) gicR3Reset(PPDMDEVINS pDevIns);
329
330/** @} */
331
332#endif /* !VMM_INCLUDED_SRC_include_GICInternal_h */
333
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