| 1 | /* $Id: GICInternal.h 108833 2025-04-03 08:16:02Z vboxsync $ */
|
|---|
| 2 | /** @file
|
|---|
| 3 | * GIC - Generic Interrupt Controller Architecture (GIC).
|
|---|
| 4 | */
|
|---|
| 5 |
|
|---|
| 6 | /*
|
|---|
| 7 | * Copyright (C) 2023-2024 Oracle and/or its affiliates.
|
|---|
| 8 | *
|
|---|
| 9 | * This file is part of VirtualBox base platform packages, as
|
|---|
| 10 | * available from https://www.virtualbox.org.
|
|---|
| 11 | *
|
|---|
| 12 | * This program is free software; you can redistribute it and/or
|
|---|
| 13 | * modify it under the terms of the GNU General Public License
|
|---|
| 14 | * as published by the Free Software Foundation, in version 3 of the
|
|---|
| 15 | * License.
|
|---|
| 16 | *
|
|---|
| 17 | * This program is distributed in the hope that it will be useful, but
|
|---|
| 18 | * WITHOUT ANY WARRANTY; without even the implied warranty of
|
|---|
| 19 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
|
|---|
| 20 | * General Public License for more details.
|
|---|
| 21 | *
|
|---|
| 22 | * You should have received a copy of the GNU General Public License
|
|---|
| 23 | * along with this program; if not, see <https://www.gnu.org/licenses>.
|
|---|
| 24 | *
|
|---|
| 25 | * SPDX-License-Identifier: GPL-3.0-only
|
|---|
| 26 | */
|
|---|
| 27 |
|
|---|
| 28 | #ifndef VMM_INCLUDED_SRC_include_GICInternal_h
|
|---|
| 29 | #define VMM_INCLUDED_SRC_include_GICInternal_h
|
|---|
| 30 | #ifndef RT_WITHOUT_PRAGMA_ONCE
|
|---|
| 31 | # pragma once
|
|---|
| 32 | #endif
|
|---|
| 33 |
|
|---|
| 34 | #include <VBox/gic.h>
|
|---|
| 35 | #include <VBox/vmm/pdmdev.h>
|
|---|
| 36 | #include <VBox/vmm/pdmthread.h>
|
|---|
| 37 | #include <VBox/vmm/pdmgic.h>
|
|---|
| 38 | #include <VBox/vmm/stam.h>
|
|---|
| 39 |
|
|---|
| 40 | #include "GITSInternal.h"
|
|---|
| 41 |
|
|---|
| 42 | /** @defgroup grp_gic_int Internal
|
|---|
| 43 | * @ingroup grp_gic
|
|---|
| 44 | * @internal
|
|---|
| 45 | * @{
|
|---|
| 46 | */
|
|---|
| 47 |
|
|---|
| 48 | #ifdef VBOX_INCLUDED_vmm_pdmgic_h
|
|---|
| 49 | /** The VirtualBox GIC backend. */
|
|---|
| 50 | extern const PDMGICBACKEND g_GicBackend;
|
|---|
| 51 | # ifdef RT_OS_DARWIN
|
|---|
| 52 | /** The Hypervisor.Framework GIC backend. */
|
|---|
| 53 | extern const PDMGICBACKEND g_GicHvfBackend;
|
|---|
| 54 | # elif defined(RT_OS_WINDOWS)
|
|---|
| 55 | /** The Hyper-V GIC backend. */
|
|---|
| 56 | extern const PDMGICBACKEND g_GicHvBackend;
|
|---|
| 57 | # elif defined(RT_OS_LINUX)
|
|---|
| 58 | /** The KVM GIC backend. */
|
|---|
| 59 | extern const PDMGICBACKEND g_GicKvmBackend;
|
|---|
| 60 | # endif
|
|---|
| 61 | #endif
|
|---|
| 62 |
|
|---|
| 63 | #define VMCPU_TO_GICCPU(a_pVCpu) (&(a_pVCpu)->gic.s)
|
|---|
| 64 | #define VM_TO_GIC(a_pVM) (&(a_pVM)->gic.s)
|
|---|
| 65 | #define VM_TO_GICDEV(a_pVM) CTX_SUFF(VM_TO_GIC(a_pVM)->pGicDev)
|
|---|
| 66 | #define GICDEV_TO_GITSDEV(a_GicDev) (&(a_GicDev)->Gits)
|
|---|
| 67 | #ifdef IN_RING3
|
|---|
| 68 | # define VMCPU_TO_DEVINS(a_pVCpu) ((a_pVCpu)->pVMR3->gic.s.pDevInsR3)
|
|---|
| 69 | #elif defined(IN_RING0)
|
|---|
| 70 | # error "Not implemented!"
|
|---|
| 71 | #endif
|
|---|
| 72 |
|
|---|
| 73 | /**
|
|---|
| 74 | * GIC PDM instance data (per-VM).
|
|---|
| 75 | */
|
|---|
| 76 | typedef struct GICDEV
|
|---|
| 77 | {
|
|---|
| 78 | /** @name Distributor register state.
|
|---|
| 79 | * @{
|
|---|
| 80 | */
|
|---|
| 81 | /** Interrupt group bitmap. */
|
|---|
| 82 | uint32_t bmIntrGroup[64];
|
|---|
| 83 | /** Interrupt config bitmap (edge-triggered vs level-sensitive). */
|
|---|
| 84 | uint32_t bmIntrConfig[128];
|
|---|
| 85 | /** Interrupt enabled bitmap. */
|
|---|
| 86 | uint32_t bmIntrEnabled[64];
|
|---|
| 87 | /** Interrupt pending bitmap. */
|
|---|
| 88 | uint32_t bmIntrPending[64];
|
|---|
| 89 | /** Interrupt active bitmap. */
|
|---|
| 90 | uint32_t bmIntrActive[64];
|
|---|
| 91 | /** Interrupt priorities. */
|
|---|
| 92 | uint8_t abIntrPriority[2048];
|
|---|
| 93 | /** Interrupt routing info. */
|
|---|
| 94 | uint32_t au32IntrRouting[2048];
|
|---|
| 95 | /** Interrupt routine mode bitmap. */
|
|---|
| 96 | uint32_t bmIntrRoutingMode[64];
|
|---|
| 97 | /** Flag whether group 0 interrupts are enabled. */
|
|---|
| 98 | bool fIntrGroup0Enabled;
|
|---|
| 99 | /** Flag whether group 1 interrupts are enabled. */
|
|---|
| 100 | bool fIntrGroup1Enabled;
|
|---|
| 101 | /** Flag whether affinity routing is enabled. */
|
|---|
| 102 | bool fAffRoutingEnabled;
|
|---|
| 103 | /** Alignment. */
|
|---|
| 104 | bool fPadding0;
|
|---|
| 105 | /** @} */
|
|---|
| 106 |
|
|---|
| 107 | /** @name Configurables.
|
|---|
| 108 | * @{ */
|
|---|
| 109 | /** The GIC architecture revision (GICD_PIDR2.ArchRev and GICR_PIDR2.ArchRev). */
|
|---|
| 110 | uint8_t uArchRev;
|
|---|
| 111 | /** The GIC architecture minor revision (currently 1 as we only support GICv3.1). */
|
|---|
| 112 | uint8_t uArchRevMinor;
|
|---|
| 113 | /** The maximum SPI supported (GICD_TYPER.ItLinesNumber). */
|
|---|
| 114 | uint8_t uMaxSpi;
|
|---|
| 115 | /** Whether extended SPIs are supported (GICD_ESPI). */
|
|---|
| 116 | bool fExtSpi;
|
|---|
| 117 | /** The maximum extended SPI supported (GICD_TYPER.ESPI_range). */
|
|---|
| 118 | uint8_t uMaxExtSpi;
|
|---|
| 119 | /** Whether extended PPIs are supported. */
|
|---|
| 120 | bool fExtPpi;
|
|---|
| 121 | /** The maximum extended PPI supported (GICR_TYPER.PPInum). */
|
|---|
| 122 | uint8_t uMaxExtPpi;
|
|---|
| 123 | /** Whether range-selector is supported (GICD_TYPER.RSS and ICC_CTLR_EL1.RSS). */
|
|---|
| 124 | bool fRangeSel;
|
|---|
| 125 | /** Whether NMIs are supported (GICD_TYPER.NMI). */
|
|---|
| 126 | bool fNmi;
|
|---|
| 127 | /** Whether message-based interrupts are supported (GICD_TYPER.MBIS). */
|
|---|
| 128 | bool fMbi;
|
|---|
| 129 | /** Whether non-zero affinity 3 levels are supported (GICD_TYPER.A3V) and
|
|---|
| 130 | * (ICC_CTLR.A3V). */
|
|---|
| 131 | bool fAff3Levels;
|
|---|
| 132 | /** Whether LPIs are supported (GICD_TYPER.PLPIS). */
|
|---|
| 133 | bool fLpi;
|
|---|
| 134 | /** The maximum LPI supported (GICD_TYPER.num_LPI). */
|
|---|
| 135 | uint8_t uMaxLpi;
|
|---|
| 136 | /** Padding. */
|
|---|
| 137 | bool afPadding0[3];
|
|---|
| 138 | /** @} */
|
|---|
| 139 |
|
|---|
| 140 | /** @name GITS device data and LPIs.
|
|---|
| 141 | * @{ */
|
|---|
| 142 | /** ITS device state. */
|
|---|
| 143 | GITSDEV Gits;
|
|---|
| 144 | /** LPI config table. */
|
|---|
| 145 | uint8_t abLpiConfig[2048];
|
|---|
| 146 | /** LPI pending bitmap. */
|
|---|
| 147 | uint32_t bmLpiPending[64];
|
|---|
| 148 | /** The LPI config table base register (GICR_PROPBASER). */
|
|---|
| 149 | RTUINT64U uLpiConfigBaseReg;
|
|---|
| 150 | /** The LPI pending table base register (GICR_PENDBASER). */
|
|---|
| 151 | RTUINT64U uLpiPendingBaseReg;
|
|---|
| 152 | /** Whether LPIs are enabled (GICR_CTLR.EnableLpis of all redistributors). */
|
|---|
| 153 | bool fEnableLpis;
|
|---|
| 154 | /** Padding. */
|
|---|
| 155 | bool afPadding1[7];
|
|---|
| 156 | /** The command-queue thread. */
|
|---|
| 157 | R3PTRTYPE(PPDMTHREAD) pCmdQueueThread;
|
|---|
| 158 | /** The event semaphore the command-queue thread waits on. */
|
|---|
| 159 | SUPSEMEVENT hEvtCmdQueue;
|
|---|
| 160 | /** @} */
|
|---|
| 161 |
|
|---|
| 162 | /** @name MMIO data.
|
|---|
| 163 | * @{ */
|
|---|
| 164 | /** The distributor MMIO handle. */
|
|---|
| 165 | IOMMMIOHANDLE hMmioDist;
|
|---|
| 166 | /** The redistributor MMIO handle. */
|
|---|
| 167 | IOMMMIOHANDLE hMmioReDist;
|
|---|
| 168 | /** The interrupt translation service MMIO handle. */
|
|---|
| 169 | IOMMMIOHANDLE hMmioGits;
|
|---|
| 170 | /** @} */
|
|---|
| 171 | } GICDEV;
|
|---|
| 172 | /** Pointer to a GIC device. */
|
|---|
| 173 | typedef GICDEV *PGICDEV;
|
|---|
| 174 | /** Pointer to a const GIC device. */
|
|---|
| 175 | typedef GICDEV const *PCGICDEV;
|
|---|
| 176 | AssertCompileMemberSizeAlignment(GICDEV, Gits, 8);
|
|---|
| 177 |
|
|---|
| 178 | /**
|
|---|
| 179 | * GIC VM Instance data.
|
|---|
| 180 | */
|
|---|
| 181 | typedef struct GIC
|
|---|
| 182 | {
|
|---|
| 183 | /** The ring-3 device instance. */
|
|---|
| 184 | PPDMDEVINSR3 pDevInsR3;
|
|---|
| 185 | } GIC;
|
|---|
| 186 | /** Pointer to GIC VM instance data. */
|
|---|
| 187 | typedef GIC *PGIC;
|
|---|
| 188 | /** Pointer to const GIC VM instance data. */
|
|---|
| 189 | typedef GIC const *PCGIC;
|
|---|
| 190 | AssertCompileSizeAlignment(GIC, 8);
|
|---|
| 191 |
|
|---|
| 192 | /**
|
|---|
| 193 | * GIC VMCPU Instance data.
|
|---|
| 194 | */
|
|---|
| 195 | typedef struct GICCPU
|
|---|
| 196 | {
|
|---|
| 197 | /** @name Redistributor register state.
|
|---|
| 198 | * @{ */
|
|---|
| 199 | /** Interrupt group bitmap. */
|
|---|
| 200 | uint32_t bmIntrGroup[3];
|
|---|
| 201 | /** Interrupt config bitmap (edge-triggered vs level-sensitive). */
|
|---|
| 202 | uint32_t bmIntrConfig[6];
|
|---|
| 203 | /** Interrupt enabled bitmap. */
|
|---|
| 204 | uint32_t bmIntrEnabled[3];
|
|---|
| 205 | /** Interrupt pending bitmap. */
|
|---|
| 206 | uint32_t bmIntrPending[3];
|
|---|
| 207 | /** Interrupt active bitmap. */
|
|---|
| 208 | uint32_t bmIntrActive[3];
|
|---|
| 209 | /** Interrupt priorities. */
|
|---|
| 210 | uint8_t abIntrPriority[96];
|
|---|
| 211 | /** @} */
|
|---|
| 212 |
|
|---|
| 213 | /** @name ICC system register state.
|
|---|
| 214 | * @{ */
|
|---|
| 215 | /** The control register (ICC_CTLR_EL1). */
|
|---|
| 216 | uint64_t uIccCtlr;
|
|---|
| 217 | /** The interrupt priority mask of the CPU interface (ICC_PMR_EL1). */
|
|---|
| 218 | uint8_t bIntrPriorityMask;
|
|---|
| 219 | /** The index to the current running priority. */
|
|---|
| 220 | uint8_t idxRunningPriority;
|
|---|
| 221 | /** The running priorities caused by preemption. */
|
|---|
| 222 | uint8_t abRunningPriorities[256];
|
|---|
| 223 | /** The active priorities group 0 bitmap. */
|
|---|
| 224 | uint32_t bmActivePriorityGroup0[4];
|
|---|
| 225 | /** The active priorities group 0 bitmap. */
|
|---|
| 226 | uint32_t bmActivePriorityGroup1[4];
|
|---|
| 227 | /** The binary point register for group 0 interrupts. */
|
|---|
| 228 | uint8_t bBinaryPtGroup0;
|
|---|
| 229 | /** The binary point register for group 1 interrupts. */
|
|---|
| 230 | uint8_t bBinaryPtGroup1;
|
|---|
| 231 | /** Flag whether group 0 interrupts are enabled. */
|
|---|
| 232 | bool fIntrGroup0Enabled;
|
|---|
| 233 | /** Flag whether group 1 interrupts are enabled. */
|
|---|
| 234 | bool fIntrGroup1Enabled;
|
|---|
| 235 | /** @} */
|
|---|
| 236 |
|
|---|
| 237 | /** @name Statistics.
|
|---|
| 238 | * @{ */
|
|---|
| 239 | #ifdef VBOX_WITH_STATISTICS
|
|---|
| 240 | /** Number of MMIO reads in R3. */
|
|---|
| 241 | STAMCOUNTER StatMmioReadR3;
|
|---|
| 242 | /** Number of MMIO writes in R3. */
|
|---|
| 243 | STAMCOUNTER StatMmioWriteR3;
|
|---|
| 244 | /** Number of MSR reads in R3. */
|
|---|
| 245 | STAMCOUNTER StatSysRegReadR3;
|
|---|
| 246 | /** Number of MSR writes in R3. */
|
|---|
| 247 | STAMCOUNTER StatSysRegWriteR3;
|
|---|
| 248 | /** Number of set SPI callbacks. */
|
|---|
| 249 | STAMCOUNTER StatSetSpiR3;
|
|---|
| 250 | /** Number of set PPI callbacks. */
|
|---|
| 251 | STAMCOUNTER StatSetPpiR3;
|
|---|
| 252 | /** Number of SGIs generated. */
|
|---|
| 253 | STAMCOUNTER StatSetSgiR3;
|
|---|
| 254 |
|
|---|
| 255 | /** Profiling of interrupt acknowledge (IAR). */
|
|---|
| 256 | STAMPROFILE StatProfIntrAckR3;
|
|---|
| 257 | /** Profiling of set SPI callback. */
|
|---|
| 258 | STAMPROFILE StatProfSetSpiR3;
|
|---|
| 259 | /** Profiling of set PPI callback. */
|
|---|
| 260 | STAMPROFILE StatProfSetPpiR3;
|
|---|
| 261 | /** Profiling of set SGI function. */
|
|---|
| 262 | STAMPROFILE StatProfSetSgiR3;
|
|---|
| 263 | #endif
|
|---|
| 264 | /** @} */
|
|---|
| 265 | } GICCPU;
|
|---|
| 266 | /** Pointer to GIC VMCPU instance data. */
|
|---|
| 267 | typedef GICCPU *PGICCPU;
|
|---|
| 268 | /** Pointer to a const GIC VMCPU instance data. */
|
|---|
| 269 | typedef GICCPU const *PCGICCPU;
|
|---|
| 270 |
|
|---|
| 271 | DECL_HIDDEN_CALLBACK(VBOXSTRICTRC) gicDistMmioRead(PPDMDEVINS pDevIns, void *pvUser, RTGCPHYS off, void *pv, unsigned cb);
|
|---|
| 272 | DECL_HIDDEN_CALLBACK(VBOXSTRICTRC) gicDistMmioWrite(PPDMDEVINS pDevIns, void *pvUser, RTGCPHYS off, void const *pv, unsigned cb);
|
|---|
| 273 | DECL_HIDDEN_CALLBACK(VBOXSTRICTRC) gicReDistMmioRead(PPDMDEVINS pDevIns, void *pvUser, RTGCPHYS off, void *pv, unsigned cb);
|
|---|
| 274 | DECL_HIDDEN_CALLBACK(VBOXSTRICTRC) gicReDistMmioWrite(PPDMDEVINS pDevIns, void *pvUser, RTGCPHYS off, void const *pv, unsigned cb);
|
|---|
| 275 | DECL_HIDDEN_CALLBACK(VBOXSTRICTRC) gicItsMmioWrite(PPDMDEVINS pDevIns, void *pvUser, RTGCPHYS off, void const *pv, unsigned cb);
|
|---|
| 276 | DECL_HIDDEN_CALLBACK(VBOXSTRICTRC) gicItsMmioRead(PPDMDEVINS pDevIns, void *pvUser, RTGCPHYS off, void *pv, unsigned cb);
|
|---|
| 277 |
|
|---|
| 278 | DECLHIDDEN(void) gicResetCpu(PPDMDEVINS pDevIns, PVMCPUCC pVCpu);
|
|---|
| 279 | DECLHIDDEN(void) gicReset(PPDMDEVINS pDevIns);
|
|---|
| 280 | DECLHIDDEN(uint16_t) gicReDistGetIntIdFromIndex(uint16_t idxIntr);
|
|---|
| 281 | DECLHIDDEN(uint16_t) gicDistGetIntIdFromIndex(uint16_t idxIntr);
|
|---|
| 282 |
|
|---|
| 283 | DECLCALLBACK(int) gicR3Construct(PPDMDEVINS pDevIns, int iInstance, PCFGMNODE pCfg);
|
|---|
| 284 | DECLCALLBACK(int) gicR3Destruct(PPDMDEVINS pDevIns);
|
|---|
| 285 | DECLCALLBACK(void) gicR3Relocate(PPDMDEVINS pDevIns, RTGCINTPTR offDelta);
|
|---|
| 286 | DECLCALLBACK(void) gicR3Reset(PPDMDEVINS pDevIns);
|
|---|
| 287 |
|
|---|
| 288 | /** @} */
|
|---|
| 289 |
|
|---|
| 290 | #endif /* !VMM_INCLUDED_SRC_include_GICInternal_h */
|
|---|
| 291 |
|
|---|
