GIMHvInternal.h@ 52343

Last change on this file since 52343 was 52010, checked in by vboxsync, 11 years ago
VMM/GIM: Add Hyper-V SSM version to the saved-state.
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1	/* $Id: GIMHvInternal.h 52010 2014-07-14 06:00:30Z vboxsync $ */
2	/** @file
3	* GIM - Hyper-V, Internal header file.
4	*/
5
6	/*
7	* Copyright (C) 2014 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*/
17
18	#ifndef ___GIMHvInternal_h
19	#define ___GIMHvInternal_h
20
21	#include <VBox/vmm/gim.h>
22	#include <VBox/vmm/cpum.h>
23
24	/**
25	* GIM Hyper-V saved-state version.
26	*/
27	#define GIM_HV_SSM_VERSION UINT32_C(1)
28
29	/** @name Hyper-V base feature identification.
30	* Features based on current partition privileges (per-VM).
31	* @{
32	*/
33	/** Virtual processor runtime MSR available. */
34	#define GIM_HV_BASE_FEAT_VP_RUNTIME_MSR RT_BIT(0)
35	/** Partition reference counter MSR available. */
36	#define GIM_HV_BASE_FEAT_PART_TIME_REF_COUNT_MSR RT_BIT(1)
37	/** Basic Synthetic Interrupt Controller MSRs available. */
38	#define GIM_HV_BASE_FEAT_BASIC_SYNTH_IC RT_BIT(2)
39	/** Synthetic Timer MSRs available. */
40	#define GIM_HV_BASE_FEAT_SYNTH_TIMER_MSRS RT_BIT(3)
41	/** APIC access MSRs (EOI, ICR, TPR) available. */
42	#define GIM_HV_BASE_FEAT_APIC_ACCESS_MSRS RT_BIT(4)
43	/** Hypercall MSRs available. */
44	#define GIM_HV_BASE_FEAT_HYPERCALL_MSRS RT_BIT(5)
45	/** Access to VCPU index MSR available. */
46	#define GIM_HV_BASE_FEAT_VP_ID_MSR RT_BIT(6)
47	/** Virtual system reset MSR available. */
48	#define GIM_HV_BASE_FEAT_VIRT_SYS_RESET_MSR RT_BIT(7)
49	/** Statistic pages MSRs available. */
50	#define GIM_HV_BASE_FEAT_STAT_PAGES_MSR RT_BIT(8)
51	/** Paritition reference TSC MSR available. */
52	#define GIM_HV_BASE_FEAT_PART_REF_TSC_MSR RT_BIT(9)
53	/** Virtual guest idle state MSR available. */
54	#define GIM_HV_BASE_FEAT_GUEST_IDLE_STATE_MSR RT_BIT(10)
55	/** Timer frequency MSRs (TSC and APIC) available. */
56	#define GIM_HV_BASE_FEAT_TIMER_FREQ_MSRS RT_BIT(11)
57	/** Debug MSRs available. */
58	#define GIM_HV_BASE_FEAT_DEBUG_MSRS RT_BIT(12)
59	/** @} */
60
61	/** @name Hyper-V partition-creation feature identification.
62	* Indicates flags specified during partition creation.
63	* @{
64	*/
65	/** Create partitions. */
66	#define GIM_HV_PART_FLAGS_CREATE_PART RT_BIT(0)
67	/** Access partition Id. */
68	#define GIM_HV_PART_FLAGS_ACCESS_PART_ID RT_BIT(1)
69	/** Access memory pool. */
70	#define GIM_HV_PART_FLAGS_ACCESS_MEMORY_POOL RT_BIT(2)
71	/** Adjust message buffers. */
72	#define GIM_HV_PART_FLAGS_ADJUST_MSG_BUFFERS RT_BIT(3)
73	/** Post messages. */
74	#define GIM_HV_PART_FLAGS_POST_MSGS RT_BIT(4)
75	/** Signal events. */
76	#define GIM_HV_PART_FLAGS_SIGNAL_EVENTS RT_BIT(5)
77	/** Create port. */
78	#define GIM_HV_PART_FLAGS_CREATE_PORT RT_BIT(6)
79	/** Connect port. */
80	#define GIM_HV_PART_FLAGS_CONNECT_PORT RT_BIT(7)
81	/** Access statistics. */
82	#define GIM_HV_PART_FLAGS_ACCESS_STATS RT_BIT(8)
83	/** Debugging.*/
84	#define GIM_HV_PART_FLAGS_DEBUGGING RT_BIT(11)
85	/** CPU management. */
86	#define GIM_HV_PART_FLAGS_CPU_MGMT RT_BIT(12)
87	/** CPU profiler. */
88	#define GIM_HV_PART_FLAGS_CPU_PROFILER RT_BIT(13)
89	/** Enable expanded stack walking. */
90	#define GIM_HV_PART_FLAGS_EXPANDED_STACK_WALK RT_BIT(14)
91	/** @} */
92
93	/** @name Hyper-V power management feature identification.
94	* @{
95	*/
96	/** Maximum CPU power state C0. */
97	#define GIM_HV_PM_MAX_CPU_POWER_STATE_C0 RT_BIT(0)
98	/** Maximum CPU power state C1. */
99	#define GIM_HV_PM_MAX_CPU_POWER_STATE_C1 RT_BIT(1)
100	/** Maximum CPU power state C2. */
101	#define GIM_HV_PM_MAX_CPU_POWER_STATE_C2 RT_BIT(2)
102	/** Maximum CPU power state C3. */
103	#define GIM_HV_PM_MAX_CPU_POWER_STATE_C3 RT_BIT(3)
104	/** HPET is required to enter C3 power state. */
105	#define GIM_HV_PM_HPET_REQD_FOR_C3 RT_BIT(4)
106	/** @} */
107
108	/** @name Hyper-V miscellaneous feature identification.
109	* Miscellaneous features available for the current partition.
110	* @{
111	*/
112	/** MWAIT instruction available. */
113	#define GIM_HV_MISC_FEAT_MWAIT RT_BIT(0)
114	/** Guest debugging support available. */
115	#define GIM_HV_MISC_FEAT_GUEST_DEBUGGING RT_BIT(1)
116	/** Performance monitor support is available. */
117	#define GIM_HV_MISC_FEAT_PERF_MON RT_BIT(2)
118	/** Support for physical CPU dynamic partitioning events. */
119	#define GIM_HV_MISC_FEAT_PCPU_DYN_PART_EVENT RT_BIT(3)
120	/** Support for passing hypercall input parameter block via XMM registers. */
121	#define GIM_HV_MISC_FEAT_XMM_HYPERCALL_INPUT RT_BIT(4)
122	/** Support for virtual guest idle state. */
123	#define GIM_HV_MISC_FEAT_GUEST_IDLE_STATE RT_BIT(5)
124	/** Support for hypervisor sleep state. */
125	#define GIM_HV_MISC_FEAT_HYPERVISOR_SLEEP_STATE RT_BIT(6)
126	/** Support for querying NUMA distances. */
127	#define GIM_HV_MISC_FEAT_QUERY_NUMA_DISTANCE RT_BIT(7)
128	/** Support for determining timer frequencies. */
129	#define GIM_HV_MISC_FEAT_TIMER_FREQ RT_BIT(8)
130	/** Support for injecting synthetic machine checks. */
131	#define GIM_HV_MISC_FEAT_INJECT_SYNTH_MC_XCPT RT_BIT(9)
132	/** Support for guest crash MSRs. */
133	#define GIM_HV_MISC_FEAT_GUEST_CRASH_MSRS RT_BIT(10)
134	/** Support for debug MSRs. */
135	#define GIM_HV_MISC_FEAT_DEBUG_MSRS RT_BIT(11)
136	/** Npiep1 Available / /* @todo What the heck is this? */
137	#define GIM_HV_MISC_FEAT_NPIEP1 RT_BIT(12)
138	/** Disable hypervisor available. */
139	#define GIM_HV_MISC_FEAT_DISABLE_HYPERVISOR RT_BIT(13)
140	/** @} */
141
142	/** @name Hyper-V implementation recommendations.
143	* Recommendations from the hypervisor for the guest for optimal performance.
144	* @{
145	*/
146	/** Use hypercall for address space switches rather than MOV CR3. */
147	#define GIM_HV_HINT_HYPERCALL_FOR_PROCESS_SWITCH RT_BIT(0)
148	/** Use hypercall for local TLB flushes rather than INVLPG/MOV CR3. */
149	#define GIM_HV_HINT_HYPERCALL_FOR_TLB_FLUSH RT_BIT(1)
150	/** Use hypercall for inter-CPU TLB flushes rather than IPIs. */
151	#define GIM_HV_HINT_HYPERCALL_FOR_TLB_SHOOTDOWN RT_BIT(2)
152	/** Use MSRs for APIC access (EOI, ICR, TPR) rather than MMIO. */
153	#define GIM_HV_HINT_MSR_FOR_APIC_ACCESS RT_BIT(3)
154	/** Use hypervisor provided MSR for a system reset. */
155	#define GIM_HV_HINT_MSR_FOR_SYS_RESET RT_BIT(4)
156	/** Relax timer-related checks (watchdogs/deadman timeouts) that rely on
157	* timely deliver of external interrupts. */
158	#define GIM_HV_HINT_RELAX_TIME_CHECKS RT_BIT(5)
159	/** Use DMA remapping. */
160	#define GIM_HV_HINT_DMA_REMAPPING RT_BIT(6)
161	/** Use interrupt remapping. */
162	#define GIM_HV_HINT_INTERRUPT_REMAPPING RT_BIT(7)
163	/** Use X2APIC MSRs rather than MMIO. */
164	#define GIM_HV_HINT_X2APIC_MSRS RT_BIT(8)
165	/** Deprecate Auto EOI (end of interrupt). */
166	#define GIM_HV_HINT_DEPRECATE_AUTO_EOI RT_BIT(9)
167	/** @} */
168
169
170	/** @name Hyper-V implementation hardware features.
171	* Which hardware features are in use by the hypervisor.
172	* @{
173	*/
174	/** APIC overlay is used. */
175	#define GIM_HV_HOST_FEAT_AVIC RT_BIT(0)
176	/** MSR bitmaps is used. */
177	#define GIM_HV_HOST_FEAT_MSR_BITMAP RT_BIT(1)
178	/** Architectural performance counter supported. */
179	#define GIM_HV_HOST_FEAT_PERF_COUNTER RT_BIT(2)
180	/** Nested paging is used. */
181	#define GIM_HV_HOST_FEAT_NESTED_PAGING RT_BIT(3)
182	/** DMA remapping is used. */
183	#define GIM_HV_HOST_FEAT_DMA_REMAPPING RT_BIT(4)
184	/** Interrupt remapping is used. */
185	#define GIM_HV_HOST_FEAT_INTERRUPT_REMAPPING RT_BIT(5)
186	/** Memory patrol scrubber is present. */
187	#define GIM_HV_HOST_FEAT_MEM_PATROL_SCRUBBER RT_BIT(6)
188	/** @} */
189
190
191	/** @name Hyper-V MSRs.
192	* @{
193	*/
194	/** Start of range 0. */
195	#define MSR_GIM_HV_RANGE0_START UINT32_C(0x40000000)
196	/** Guest OS identification (R/W) */
197	#define MSR_GIM_HV_GUEST_OS_ID UINT32_C(0x40000000)
198	/** Enable hypercall interface (R/W) */
199	#define MSR_GIM_HV_HYPERCALL UINT32_C(0x40000001)
200	/** Virtual processor's (VCPU) index (R) */
201	#define MSR_GIM_HV_VP_INDEX UINT32_C(0x40000002)
202	/** Reset operation (R/W) */
203	#define MSR_GIM_HV_RESET UINT32_C(0x40000003)
204	/** End of range 0. */
205	#define MSR_GIM_HV_RANGE0_END MSR_GIM_HV_RESET
206
207	/** Start of range 1. */
208	#define MSR_GIM_HV_RANGE1_START UINT32_C(0x40000010)
209	/** Virtual processor's (VCPU) runtime (R) */
210	#define MSR_GIM_HV_VP_RUNTIME UINT32_C(0x40000010)
211	/** End of range 1. */
212	#define MSR_GIM_HV_RANGE1_END MSR_GIM_HV_VP_RUNTIME
213
214	/** Start of range 2. */
215	#define MSR_GIM_HV_RANGE2_START UINT32_C(0x40000020)
216	/** Per-VM reference counter (R) */
217	#define MSR_GIM_HV_TIME_REF_COUNT UINT32_C(0x40000020)
218	/** Per-VM TSC page (R/W) */
219	#define MSR_GIM_HV_REF_TSC UINT32_C(0x40000021)
220	/** Frequency of TSC in Hz as reported by the hypervisor (R) */
221	#define MSR_GIM_HV_TSC_FREQ UINT32_C(0x40000022)
222	/** Frequency of LAPIC in Hz as reported by the hypervisor (R) */
223	#define MSR_GIM_HV_APIC_FREQ UINT32_C(0x40000023)
224	/** End of range 2. */
225	#define MSR_GIM_HV_RANGE2_END MSR_GIM_HV_APIC_FREQ
226
227	/** Start of range 3. */
228	#define MSR_GIM_HV_RANGE3_START UINT32_C(0x40000070)
229	/** Access to APIC EOI (End-Of-Interrupt) register (W) */
230	#define MSR_GIM_HV_EOI UINT32_C(0x40000070)
231	/** Access to APIC ICR (Interrupt Command) register (R/W) */
232	#define MSR_GIM_HV_ICR UINT32_C(0x40000071)
233	/** Access to APIC TPR (Task Priority) register (R/W) */
234	#define MSR_GIM_HV_TPR UINT32_C(0x40000072)
235	/** Enables lazy EOI processing (R/W) */
236	#define MSR_GIM_HV_APIC_ASSIST_PAGE UINT32_C(0x40000073)
237	/** End of range 3. */
238	#define MSR_GIM_HV_RANGE3_END MSR_GIM_HV_APIC_ASSIST_PAGE
239
240	/** Start of range 4. */
241	#define MSR_GIM_HV_RANGE4_START UINT32_C(0x40000080)
242	/** Control behaviour of synthetic interrupt controller (R/W) */
243	#define MSR_GIM_HV_SCONTROL UINT32_C(0x40000080)
244	/** Synthetic interrupt controller version (R) */
245	#define MSR_GIM_HV_SVERSION UINT32_C(0x40000081)
246	/** Base address of synthetic interrupt event flag (R/W) */
247	#define MSR_GIM_HV_SIEFP UINT32_C(0x40000082)
248	/** Base address of synthetic interrupt parameter page (R/W) */
249	#define MSR_GIM_HV_SIMP UINT32_C(0x40000083)
250	/** End-Of-Message in synthetic interrupt parameter page (W) */
251	#define MSR_GIM_HV_EOM UINT32_C(0x40000084)
252	/** End of range 4. */
253	#define MSR_GIM_HV_RANGE4_END MSR_GIM_HV_EOM
254
255	/** Start of range 5. */
256	#define MSR_GIM_HV_RANGE5_START UINT32_C(0x40000090)
257	/** Configures synthetic interrupt source 0 (R/W) */
258	#define MSR_GIM_HV_SINT0 UINT32_C(0x40000090)
259	/** Configures synthetic interrupt source 1 (R/W) */
260	#define MSR_GIM_HV_SINT1 UINT32_C(0x40000091)
261	/** Configures synthetic interrupt source 2 (R/W) */
262	#define MSR_GIM_HV_SINT2 UINT32_C(0x40000092)
263	/** Configures synthetic interrupt source 3 (R/W) */
264	#define MSR_GIM_HV_SINT3 UINT32_C(0x40000093)
265	/** Configures synthetic interrupt source 4 (R/W) */
266	#define MSR_GIM_HV_SINT4 UINT32_C(0x40000094)
267	/** Configures synthetic interrupt source 5 (R/W) */
268	#define MSR_GIM_HV_SINT5 UINT32_C(0x40000095)
269	/** Configures synthetic interrupt source 6 (R/W) */
270	#define MSR_GIM_HV_SINT6 UINT32_C(0x40000096)
271	/** Configures synthetic interrupt source 7 (R/W) */
272	#define MSR_GIM_HV_SINT7 UINT32_C(0x40000097)
273	/** Configures synthetic interrupt source 8 (R/W) */
274	#define MSR_GIM_HV_SINT8 UINT32_C(0x40000098)
275	/** Configures synthetic interrupt source 9 (R/W) */
276	#define MSR_GIM_HV_SINT9 UINT32_C(0x40000099)
277	/** Configures synthetic interrupt source 10 (R/W) */
278	#define MSR_GIM_HV_SINT10 UINT32_C(0x4000009A)
279	/** Configures synthetic interrupt source 11 (R/W) */
280	#define MSR_GIM_HV_SINT11 UINT32_C(0x4000009B)
281	/** Configures synthetic interrupt source 12 (R/W) */
282	#define MSR_GIM_HV_SINT12 UINT32_C(0x4000009C)
283	/** Configures synthetic interrupt source 13 (R/W) */
284	#define MSR_GIM_HV_SINT13 UINT32_C(0x4000009D)
285	/** Configures synthetic interrupt source 14 (R/W) */
286	#define MSR_GIM_HV_SINT14 UINT32_C(0x4000009E)
287	/** Configures synthetic interrupt source 15 (R/W) */
288	#define MSR_GIM_HV_SINT15 UINT32_C(0x4000009F)
289	/** End of range 5. */
290	#define MSR_GIM_HV_RANGE5_END MSR_GIM_HV_SINT15
291
292	/** Start of range 6. */
293	#define MSR_GIM_HV_RANGE6_START UINT32_C(0x400000B0)
294	/** Configures register for synthetic timer 0 (R/W) */
295	#define MSR_GIM_HV_STIMER0_CONFIG UINT32_C(0x400000B0)
296	/** Expiration time or period for synthetic timer 0 (R/W) */
297	#define MSR_GIM_HV_STIMER0_COUNT UINT32_C(0x400000B1)
298	/** Configures register for synthetic timer 1 (R/W) */
299	#define MSR_GIM_HV_STIMER1_CONFIG UINT32_C(0x400000B2)
300	/** Expiration time or period for synthetic timer 1 (R/W) */
301	#define MSR_GIM_HV_STIMER1_COUNT UINT32_C(0x400000B3)
302	/** Configures register for synthetic timer 2 (R/W) */
303	#define MSR_GIM_HV_STIMER2_CONFIG UINT32_C(0x400000B4)
304	/** Expiration time or period for synthetic timer 2 (R/W) */
305	#define MSR_GIM_HV_STIMER2_COUNT UINT32_C(0x400000B5)
306	/** Configures register for synthetic timer 3 (R/W) */
307	#define MSR_GIM_HV_STIMER3_CONFIG UINT32_C(0x400000B6)
308	/** Expiration time or period for synthetic timer 3 (R/W) */
309	#define MSR_GIM_HV_STIMER3_COUNT UINT32_C(0x400000B7)
310	/** End of range 6. */
311	#define MSR_GIM_HV_RANGE6_END MSR_GIM_HV_STIMER3_COUNT
312
313	/** Start of range 7. */
314	#define MSR_GIM_HV_RANGE7_START UINT32_C(0x400000C1)
315	/** Trigger to transition to power state C1 (R) */
316	#define MSR_GIM_HV_POWER_STATE_TRIGGER_C1 UINT32_C(0x400000C1)
317	/** Trigger to transition to power state C2 (R) */
318	#define MSR_GIM_HV_POWER_STATE_TRIGGER_C2 UINT32_C(0x400000C2)
319	/** Trigger to transition to power state C3 (R) */
320	#define MSR_GIM_HV_POWER_STATE_TRIGGER_C3 UINT32_C(0x400000C3)
321	/** End of range 7. */
322	#define MSR_GIM_HV_RANGE7_END MSR_GIM_HV_POWER_STATE_TRIGGER_C3
323
324	/** Start of range 8. */
325	#define MSR_GIM_HV_RANGE8_START UINT32_C(0x400000D1)
326	/** Configure the recipe for power state transitions to C1 (R/W) */
327	#define MSR_GIM_HV_POWER_STATE_CONFIG_C1 UINT32_C(0x400000D1)
328	/** Configure the recipe for power state transitions to C2 (R/W) */
329	#define MSR_GIM_HV_POWER_STATE_CONFIG_C2 UINT32_C(0x400000D2)
330	/** Configure the recipe for power state transitions to C3 (R/W) */
331	#define MSR_GIM_HV_POWER_STATE_CONFIG_C3 UINT32_C(0x400000D3)
332	/** End of range 8. */
333	#define MSR_GIM_HV_RANGE8_END MSR_GIM_HV_POWER_STATE_CONFIG_C3
334
335	/** Start of range 9. */
336	#define MSR_GIM_HV_RANGE9_START UINT32_C(0x400000E0)
337	/** Map the guest's retail partition stats page (R/W) */
338	#define MSR_GIM_HV_STATS_PART_RETAIL_PAGE UINT32_C(0x400000E0)
339	/** Map the guest's internal partition stats page (R/W) */
340	#define MSR_GIM_HV_STATS_PART_INTERNAL_PAGE UINT32_C(0x400000E1)
341	/** Map the guest's retail VP stats page (R/W) */
342	#define MSR_GIM_HV_STATS_VP_RETAIL_PAGE UINT32_C(0x400000E2)
343	/** Map the guest's internal VP stats page (R/W) */
344	#define MSR_GIM_HV_STATS_VP_INTERNAL_PAGE UINT32_C(0x400000E3)
345	/** End of range 9. */
346	#define MSR_GIM_HV_RANGE9_END MSR_GIM_HV_STATS_VP_INTERNAL_PAGE
347
348	/** Start of range 10. */
349	#define MSR_GIM_HV_RANGE10_START UINT32_C(0x400000F0)
350	/** Trigger the guest's transition to idle power state (R) */
351	#define MSR_GIM_HV_GUEST_IDLE UINT32_C(0x400000F0)
352	/** Synthetic debug control. */
353	#define MSR_GIM_HV_SYNTH_DEBUG_CONTROL UINT32_C(0x400000F1)
354	/** Synthetic debug status. */
355	#define MSR_GIM_HV_SYNTH_DEBUG_STATUS UINT32_C(0x400000F2)
356	/** Synthetic debug send buffer. */
357	#define MSR_GIM_HV_SYNTH_DEBUG_SEND_BUFFER UINT32_C(0x400000F3)
358	/** Synthetic debug receive buffer. */
359	#define MSR_GIM_HV_SYNTH_DEBUG_RECEIVE_BUFFER UINT32_C(0x400000F4)
360	/** Synthetic debug pending buffer. */
361	#define MSR_GIM_HV_SYNTH_DEBUG_PENDING_BUFFER UINT32_C(0x400000F5)
362	/** End of range 10. */
363	#define MSR_GIM_HV_RANGE10_END MSR_GIM_HV_SYNTH_DEBUG_PENDING_BUFFER
364
365	/** Start of range 11. */
366	#define MSR_GIM_HV_RANGE11_START UINT32_C(0x40000100)
367	/** Guest crash MSR 0. */
368	#define MSR_GIM_HV_CRASH_P0 UINT32_C(0x40000100)
369	/** Guest crash MSR 1. */
370	#define MSR_GIM_HV_CRASH_P1 UINT32_C(0x40000101)
371	/** Guest crash MSR 2. */
372	#define MSR_GIM_HV_CRASH_P2 UINT32_C(0x40000102)
373	/** Guest crash MSR 3. */
374	#define MSR_GIM_HV_CRASH_P3 UINT32_C(0x40000103)
375	/** Guest crash MSR 4. */
376	#define MSR_GIM_HV_CRASH_P4 UINT32_C(0x40000104)
377	/** Guest crash control. */
378	#define MSR_GIM_HV_CRASH_CTL UINT32_C(0x40000105)
379	/** End of range 11. */
380	#define MSR_GIM_HV_RANGE11_END MSR_GIM_HV_CRASH_CTL
381	/** @} */
382
383	AssertCompile(MSR_GIM_HV_RANGE0_START <= MSR_GIM_HV_RANGE0_END);
384	AssertCompile(MSR_GIM_HV_RANGE1_START <= MSR_GIM_HV_RANGE1_END);
385	AssertCompile(MSR_GIM_HV_RANGE2_START <= MSR_GIM_HV_RANGE2_END);
386	AssertCompile(MSR_GIM_HV_RANGE3_START <= MSR_GIM_HV_RANGE3_END);
387	AssertCompile(MSR_GIM_HV_RANGE4_START <= MSR_GIM_HV_RANGE4_END);
388	AssertCompile(MSR_GIM_HV_RANGE5_START <= MSR_GIM_HV_RANGE5_END);
389	AssertCompile(MSR_GIM_HV_RANGE6_START <= MSR_GIM_HV_RANGE6_END);
390	AssertCompile(MSR_GIM_HV_RANGE7_START <= MSR_GIM_HV_RANGE7_END);
391	AssertCompile(MSR_GIM_HV_RANGE8_START <= MSR_GIM_HV_RANGE8_END);
392	AssertCompile(MSR_GIM_HV_RANGE9_START <= MSR_GIM_HV_RANGE9_END);
393	AssertCompile(MSR_GIM_HV_RANGE10_START <= MSR_GIM_HV_RANGE10_END);
394	AssertCompile(MSR_GIM_HV_RANGE11_START <= MSR_GIM_HV_RANGE11_END);
395
396	/** @name Hyper-V MSR - Reset (MSR_GIM_HV_RESET).
397	* @{
398	*/
399	/** The hypercall enable bit. */
400	#define MSR_GIM_HV_RESET_BIT RT_BIT_64(0)
401	/** Whether the hypercall-page is enabled or not. */
402	#define MSR_GIM_HV_RESET_IS_SET(a) RT_BOOL((a) & MSR_GIM_HV_RESET_BIT)
403	/** @} */
404
405	/** @name Hyper-V MSR - Hypercall (MSR_GIM_HV_HYPERCALL).
406	* @{
407	*/
408	/** Guest-physical page frame number of the hypercall-page. */
409	#define MSR_GIM_HV_HYPERCALL_GUEST_PFN(a) ((a) >> 12)
410	/** The hypercall enable bit. */
411	#define MSR_GIM_HV_HYPERCALL_ENABLE_BIT RT_BIT_64(0)
412	/** Whether the hypercall-page is enabled or not. */
413	#define MSR_GIM_HV_HYPERCALL_IS_ENABLED(a) RT_BOOL((a) & MSR_GIM_HV_HYPERCALL_ENABLE_BIT)
414	/** @} */
415
416	/** @name Hyper-V MSR - Reference TSC (MSR_GIM_HV_REF_TSC).
417	* @{
418	*/
419	/** Guest-physical page frame number of the TSC-page. */
420	#define MSR_GIM_HV_REF_TSC_GUEST_PFN(a) ((a) >> 12)
421	/** The TSC-page enable bit. */
422	#define MSR_GIM_HV_REF_TSC_ENABLE_BIT RT_BIT_64(0)
423	/** Whether the TSC-page is enabled or not. */
424	#define MSR_GIM_HV_REF_TSC_IS_ENABLED(a) RT_BOOL((a) & MSR_GIM_HV_REF_TSC_ENABLE_BIT)
425	/** @} */
426
427	/** Hyper-V page size. */
428	#define GIM_HV_PAGE_SIZE 0x1000
429
430	/**
431	* MMIO2 region indices.
432	*/
433	/** The hypercall page region. */
434	#define GIM_HV_HYPERCALL_PAGE_REGION_IDX UINT8_C(0)
435	/** The TSC page region. */
436	#define GIM_HV_REF_TSC_PAGE_REGION_IDX UINT8_C(1)
437	/** The maximum region index (must be <= UINT8_MAX). */
438	#define GIM_HV_REGION_IDX_MAX GIM_HV_REF_TSC_PAGE_REGION_IDX
439
440	/**
441	* Hyper-V TSC (HV_REFERENCE_TSC_PAGE) structure placed in the TSC reference
442	* page.
443	*/
444	typedef struct GIMHVREFTSC
445	{
446	uint32_t volatile u32TscSequence;
447	uint32_t uReserved0;
448	uint64_t volatile u64TscScale;
449	int64_t volatile i64TscOffset;
450	} GIMHVTSCPAGE;
451	/** Pointer to Hyper-V reference TSC. */
452	typedef GIMHVREFTSC *PGIMHVREFTSC;
453	/** Pointer to a const Hyper-V reference TSC. */
454	typedef GIMHVREFTSC const *PCGIMHVREFTSC;
455
456
457	/**
458	* GIM Hyper-V VM Instance data.
459	* Changes to this must checked against the padding of the gim union in VM!
460	*/
461	typedef struct GIMHV
462	{
463	/** Guest OS identity MSR. */
464	uint64_t u64GuestOsIdMsr;
465	/** Hypercall MSR. */
466	uint64_t u64HypercallMsr;
467	/** Reference TSC page MSR. */
468	uint64_t u64TscPageMsr;
469
470	/** Basic features. */
471	uint32_t uBaseFeat;
472	/** Partition flags. */
473	uint32_t uPartFlags;
474	/** Power management features. */
475	uint32_t uPowMgmtFeat;
476	/** Miscellaneous features. */
477	uint32_t uMiscFeat;
478	/** Hypervisor hints to the guest. */
479	uint32_t uHyperHints;
480	/** Hypervisor capabilities. */
481	uint32_t uHyperCaps;
482
483	/** Per-VM R0 Spinlock for protecting EMT writes to the TSC page. */
484	RTSPINLOCK hSpinlockR0;
485	#if HC_ARCH_BITS == 32
486	uint32_t u32Alignment1;
487	#endif
488
489	/** Array of MMIO2 regions. */
490	GIMMMIO2REGION aMmio2Regions[GIM_HV_REGION_IDX_MAX + 1];
491	} GIMHV;
492	/** Pointer to per-VM GIM Hyper-V instance data. */
493	typedef GIMHV *PGIMHV;
494	/** Pointer to const per-VM GIM Hyper-V instance data. */
495	typedef GIMHV const *PCGIMHV;
496	AssertCompileMemberAlignment(GIMHV, aMmio2Regions, 8);
497	AssertCompileMemberAlignment(GIMHV, hSpinlockR0, sizeof(uintptr_t));
498
499	RT_C_DECLS_BEGIN
500
501	#ifdef IN_RING0
502	VMMR0_INT_DECL(int) GIMR0HvInitVM(PVM pVM);
503	VMMR0_INT_DECL(int) GIMR0HvTermVM(PVM pVM);
504	VMMR0_INT_DECL(int) GIMR0HvUpdateParavirtTsc(PVM pVM, uint64_t u64Offset);
505	#endif /* IN_RING0 */
506
507	#ifdef IN_RING3
508	VMMR3_INT_DECL(int) GIMR3HvInit(PVM pVM);
509	VMMR3_INT_DECL(int) GIMR3HvTerm(PVM pVM);
510	VMMR3_INT_DECL(void) GIMR3HvRelocate(PVM pVM, RTGCINTPTR offDelta);
511	VMMR3_INT_DECL(void) GIMR3HvReset(PVM pVM);
512	VMMR3_INT_DECL(PGIMMMIO2REGION) GIMR3HvGetMmio2Regions(PVM pVM, uint32_t *pcRegions);
513	VMMR3_INT_DECL(int) GIMR3HvSave(PVM pVM, PSSMHANDLE pSSM);
514	VMMR3_INT_DECL(int) GIMR3HvLoad(PVM pVM, PSSMHANDLE pSSM, uint32_t uSSMVersion);
515
516	VMMR3_INT_DECL(int) GIMR3HvDisableTscPage(PVM pVM);
517	VMMR3_INT_DECL(int) GIMR3HvEnableTscPage(PVM pVM, RTGCPHYS GCPhysTscPage, bool fUseThisTscSequence, uint32_t uTscSequence);
518	VMMR3_INT_DECL(int) GIMR3HvDisableHypercallPage(PVM pVM);
519	VMMR3_INT_DECL(int) GIMR3HvEnableHypercallPage(PVM pVM, RTGCPHYS GCPhysHypercallPage);
520	#endif /* IN_RING3 */
521
522	VMM_INT_DECL(bool) GIMHvIsParavirtTscEnabled(PVM pVM);
523	VMM_INT_DECL(bool) GIMHvAreHypercallsEnabled(PVMCPU pVCpu);
524	VMM_INT_DECL(int) GIMHvHypercall(PVMCPU pVCpu, PCPUMCTX pCtx);
525	VMM_INT_DECL(int) GIMHvReadMsr(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue);
526	VMM_INT_DECL(int) GIMHvWriteMsr(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uRawValue);
527
528	RT_C_DECLS_END
529
530	#endif /* ___GIMHvInternal_h */
531

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source: vbox/trunk/src/VBox/VMM/include/GIMHvInternal.h@ 52343

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