VirtualBox

source: vbox/trunk/src/VBox/VMM/include/GIMHvInternal.h@ 75142

Last change on this file since 75142 was 73340, checked in by vboxsync, 6 years ago

VMM/GIM: Address todo mentioned in r123944.
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File size: 59.0 KB
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1/* $Id: GIMHvInternal.h 73340 2018-07-24 03:12:17Z vboxsync $ */
2/** @file
3 * GIM - Hyper-V, Internal header file.
4 */
5
6/*
7 * Copyright (C) 2014-2017 Oracle Corporation
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 */
17
18#ifndef ___GIMHvInternal_h
19#define ___GIMHvInternal_h
20
21#include <VBox/vmm/gim.h>
22#include <VBox/vmm/cpum.h>
23
24#include <iprt/net.h>
25
26/** @name Hyper-V base feature identification.
27 * Features based on current partition privileges (per-VM).
28 * @{
29 */
30/** Virtual processor runtime MSR available. */
31#define GIM_HV_BASE_FEAT_VP_RUNTIME_MSR RT_BIT(0)
32/** Partition reference counter MSR available. */
33#define GIM_HV_BASE_FEAT_PART_TIME_REF_COUNT_MSR RT_BIT(1)
34/** Basic Synthetic Interrupt Controller MSRs available. */
35#define GIM_HV_BASE_FEAT_BASIC_SYNIC_MSRS RT_BIT(2)
36/** Synthetic Timer MSRs available. */
37#define GIM_HV_BASE_FEAT_STIMER_MSRS RT_BIT(3)
38/** APIC access MSRs (EOI, ICR, TPR) available. */
39#define GIM_HV_BASE_FEAT_APIC_ACCESS_MSRS RT_BIT(4)
40/** Hypercall MSRs available. */
41#define GIM_HV_BASE_FEAT_HYPERCALL_MSRS RT_BIT(5)
42/** Access to VCPU index MSR available. */
43#define GIM_HV_BASE_FEAT_VP_ID_MSR RT_BIT(6)
44/** Virtual system reset MSR available. */
45#define GIM_HV_BASE_FEAT_VIRT_SYS_RESET_MSR RT_BIT(7)
46/** Statistic pages MSRs available. */
47#define GIM_HV_BASE_FEAT_STAT_PAGES_MSR RT_BIT(8)
48/** Paritition reference TSC MSR available. */
49#define GIM_HV_BASE_FEAT_PART_REF_TSC_MSR RT_BIT(9)
50/** Virtual guest idle state MSR available. */
51#define GIM_HV_BASE_FEAT_GUEST_IDLE_STATE_MSR RT_BIT(10)
52/** Timer frequency MSRs (TSC and APIC) available. */
53#define GIM_HV_BASE_FEAT_TIMER_FREQ_MSRS RT_BIT(11)
54/** Debug MSRs available. */
55#define GIM_HV_BASE_FEAT_DEBUG_MSRS RT_BIT(12)
56/** @} */
57
58/** @name Hyper-V partition-creation feature identification.
59 * Indicates flags specified during partition creation.
60 * @{
61 */
62/** Create partitions. */
63#define GIM_HV_PART_FLAGS_CREATE_PART RT_BIT(0)
64/** Access partition Id. */
65#define GIM_HV_PART_FLAGS_ACCESS_PART_ID RT_BIT(1)
66/** Access memory pool. */
67#define GIM_HV_PART_FLAGS_ACCESS_MEMORY_POOL RT_BIT(2)
68/** Adjust message buffers. */
69#define GIM_HV_PART_FLAGS_ADJUST_MSG_BUFFERS RT_BIT(3)
70/** Post messages. */
71#define GIM_HV_PART_FLAGS_POST_MSGS RT_BIT(4)
72/** Signal events. */
73#define GIM_HV_PART_FLAGS_SIGNAL_EVENTS RT_BIT(5)
74/** Create port. */
75#define GIM_HV_PART_FLAGS_CREATE_PORT RT_BIT(6)
76/** Connect port. */
77#define GIM_HV_PART_FLAGS_CONNECT_PORT RT_BIT(7)
78/** Access statistics. */
79#define GIM_HV_PART_FLAGS_ACCESS_STATS RT_BIT(8)
80/** Debugging.*/
81#define GIM_HV_PART_FLAGS_DEBUGGING RT_BIT(11)
82/** CPU management. */
83#define GIM_HV_PART_FLAGS_CPU_MGMT RT_BIT(12)
84/** CPU profiler. */
85#define GIM_HV_PART_FLAGS_CPU_PROFILER RT_BIT(13)
86/** Enable expanded stack walking. */
87#define GIM_HV_PART_FLAGS_EXPANDED_STACK_WALK RT_BIT(14)
88/** Access VSM. */
89#define GIM_HV_PART_FLAGS_ACCESS_VSM RT_BIT(16)
90/** Access VP registers. */
91#define GIM_HV_PART_FLAGS_ACCESS_VP_REGS RT_BIT(17)
92/** Enable extended hypercalls. */
93#define GIM_HV_PART_FLAGS_EXTENDED_HYPERCALLS RT_BIT(20)
94/** Start virtual processor. */
95#define GIM_HV_PART_FLAGS_START_VP RT_BIT(21)
96/** @} */
97
98/** @name Hyper-V power management feature identification.
99 * @{
100 */
101/** Maximum CPU power state C0. */
102#define GIM_HV_PM_MAX_CPU_POWER_STATE_C0 RT_BIT(0)
103/** Maximum CPU power state C1. */
104#define GIM_HV_PM_MAX_CPU_POWER_STATE_C1 RT_BIT(1)
105/** Maximum CPU power state C2. */
106#define GIM_HV_PM_MAX_CPU_POWER_STATE_C2 RT_BIT(2)
107/** Maximum CPU power state C3. */
108#define GIM_HV_PM_MAX_CPU_POWER_STATE_C3 RT_BIT(3)
109/** HPET is required to enter C3 power state. */
110#define GIM_HV_PM_HPET_REQD_FOR_C3 RT_BIT(4)
111/** @} */
112
113/** @name Hyper-V miscellaneous feature identification.
114 * Miscellaneous features available for the current partition.
115 * @{
116 */
117/** MWAIT instruction available. */
118#define GIM_HV_MISC_FEAT_MWAIT RT_BIT(0)
119/** Guest debugging support available. */
120#define GIM_HV_MISC_FEAT_GUEST_DEBUGGING RT_BIT(1)
121/** Performance monitor support is available. */
122#define GIM_HV_MISC_FEAT_PERF_MON RT_BIT(2)
123/** Support for physical CPU dynamic partitioning events. */
124#define GIM_HV_MISC_FEAT_PCPU_DYN_PART_EVENT RT_BIT(3)
125/** Support for passing hypercall input parameter block via XMM registers. */
126#define GIM_HV_MISC_FEAT_XMM_HYPERCALL_INPUT RT_BIT(4)
127/** Support for virtual guest idle state. */
128#define GIM_HV_MISC_FEAT_GUEST_IDLE_STATE RT_BIT(5)
129/** Support for hypervisor sleep state. */
130#define GIM_HV_MISC_FEAT_HYPERVISOR_SLEEP_STATE RT_BIT(6)
131/** Support for querying NUMA distances. */
132#define GIM_HV_MISC_FEAT_QUERY_NUMA_DISTANCE RT_BIT(7)
133/** Support for determining timer frequencies. */
134#define GIM_HV_MISC_FEAT_TIMER_FREQ RT_BIT(8)
135/** Support for injecting synthetic machine checks. */
136#define GIM_HV_MISC_FEAT_INJECT_SYNMC_XCPT RT_BIT(9)
137/** Support for guest crash MSRs. */
138#define GIM_HV_MISC_FEAT_GUEST_CRASH_MSRS RT_BIT(10)
139/** Support for debug MSRs. */
140#define GIM_HV_MISC_FEAT_DEBUG_MSRS RT_BIT(11)
141/** Npiep1 Available */ /** @todo What the heck is this? */
142#define GIM_HV_MISC_FEAT_NPIEP1 RT_BIT(12)
143/** Disable hypervisor available. */
144#define GIM_HV_MISC_FEAT_DISABLE_HYPERVISOR RT_BIT(13)
145/** Extended GVA ranges for FlushVirtualAddressList available. */
146#define GIM_HV_MISC_FEAT_EXT_GVA_RANGE_FOR_FLUSH_VA_LIST RT_BIT(14)
147/** Support for returning hypercall output via XMM registers. */
148#define GIM_HV_MISC_FEAT_HYPERCALL_OUTPUT_XMM RT_BIT(15)
149/** Synthetic interrupt source polling mode available. */
150#define GIM_HV_MISC_FEAT_SINT_POLLING_MODE RT_BIT(17)
151/** Hypercall MSR lock available. */
152#define GIM_HV_MISC_FEAT_HYPERCALL_MSR_LOCK RT_BIT(18)
153/** Use direct synthetic MSRs. */
154#define GIM_HV_MISC_FEAT_USE_DIRECT_SYNTH_MSRS RT_BIT(19)
155/** @} */
156
157/** @name Hyper-V implementation recommendations.
158 * Recommendations from the hypervisor for the guest for optimal performance.
159 * @{
160 */
161/** Use hypercall for address space switches rather than MOV CR3. */
162#define GIM_HV_HINT_HYPERCALL_FOR_PROCESS_SWITCH RT_BIT(0)
163/** Use hypercall for local TLB flushes rather than INVLPG/MOV CR3. */
164#define GIM_HV_HINT_HYPERCALL_FOR_TLB_FLUSH RT_BIT(1)
165/** Use hypercall for inter-CPU TLB flushes rather than IPIs. */
166#define GIM_HV_HINT_HYPERCALL_FOR_TLB_SHOOTDOWN RT_BIT(2)
167/** Use MSRs for APIC access (EOI, ICR, TPR) rather than MMIO. */
168#define GIM_HV_HINT_MSR_FOR_APIC_ACCESS RT_BIT(3)
169/** Use hypervisor provided MSR for a system reset. */
170#define GIM_HV_HINT_MSR_FOR_SYS_RESET RT_BIT(4)
171/** Relax timer-related checks (watchdogs/deadman timeouts) that rely on
172 * timely deliver of external interrupts. */
173#define GIM_HV_HINT_RELAX_TIME_CHECKS RT_BIT(5)
174/** Recommend using DMA remapping. */
175#define GIM_HV_HINT_DMA_REMAPPING RT_BIT(6)
176/** Recommend using interrupt remapping. */
177#define GIM_HV_HINT_INTERRUPT_REMAPPING RT_BIT(7)
178/** Recommend using X2APIC MSRs rather than MMIO. */
179#define GIM_HV_HINT_X2APIC_MSRS RT_BIT(8)
180/** Recommend deprecating Auto EOI (end of interrupt). */
181#define GIM_HV_HINT_DEPRECATE_AUTO_EOI RT_BIT(9)
182/** Recommend using SyntheticClusterIpi hypercall. */
183#define GIM_HV_HINT_SYNTH_CLUSTER_IPI_HYPERCALL RT_BIT(10)
184/** Recommend using newer ExProcessMasks interface. */
185#define GIM_HV_HINT_EX_PROC_MASKS_INTERFACE RT_BIT(11)
186/** Indicate that Hyper-V is nested within a Hyper-V partition. */
187#define GIM_HV_HINT_NESTED_HYPERV RT_BIT(12)
188/** Recommend using INT for MBEC system calls. */
189#define GIM_HV_HINT_INT_FOR_MBEC_SYSCALLS RT_BIT(13)
190/** Recommend using enlightened VMCS interfacea and nested enlightenments. */
191#define GIM_HV_HINT_NESTED_ENLIGHTENED_VMCS_INTERFACE RT_BIT(14)
192/** @} */
193
194
195/** @name Hyper-V implementation hardware features.
196 * Which hardware features are in use by the hypervisor.
197 * @{
198 */
199/** APIC overlay is used. */
200#define GIM_HV_HOST_FEAT_AVIC RT_BIT(0)
201/** MSR bitmaps is used. */
202#define GIM_HV_HOST_FEAT_MSR_BITMAP RT_BIT(1)
203/** Architectural performance counter supported. */
204#define GIM_HV_HOST_FEAT_PERF_COUNTER RT_BIT(2)
205/** Nested paging is used. */
206#define GIM_HV_HOST_FEAT_NESTED_PAGING RT_BIT(3)
207/** DMA remapping is used. */
208#define GIM_HV_HOST_FEAT_DMA_REMAPPING RT_BIT(4)
209/** Interrupt remapping is used. */
210#define GIM_HV_HOST_FEAT_INTERRUPT_REMAPPING RT_BIT(5)
211/** Memory patrol scrubber is present. */
212#define GIM_HV_HOST_FEAT_MEM_PATROL_SCRUBBER RT_BIT(6)
213/** DMA protection is in use. */
214#define GIM_HV_HOST_FEAT_DMA_PROT_IN_USE RT_BIT(7)
215/** HPET is requested. */
216#define GIM_HV_HOST_FEAT_HPET_REQUESTED RT_BIT(8)
217/** Synthetic timers are volatile. */
218#define GIM_HV_HOST_FEAT_STIMER_VOLATILE RT_BIT(9)
219/** @} */
220
221
222/** @name Hyper-V MSRs.
223 * @{
224 */
225/** Start of range 0. */
226#define MSR_GIM_HV_RANGE0_FIRST UINT32_C(0x40000000)
227/** Guest OS identification (R/W) */
228#define MSR_GIM_HV_GUEST_OS_ID UINT32_C(0x40000000)
229/** Enable hypercall interface (R/W) */
230#define MSR_GIM_HV_HYPERCALL UINT32_C(0x40000001)
231/** Virtual processor's (VCPU) index (R) */
232#define MSR_GIM_HV_VP_INDEX UINT32_C(0x40000002)
233/** Reset operation (R/W) */
234#define MSR_GIM_HV_RESET UINT32_C(0x40000003)
235/** End of range 0. */
236#define MSR_GIM_HV_RANGE0_LAST MSR_GIM_HV_RESET
237
238/** Start of range 1. */
239#define MSR_GIM_HV_RANGE1_FIRST UINT32_C(0x40000010)
240/** Virtual processor's (VCPU) runtime (R) */
241#define MSR_GIM_HV_VP_RUNTIME UINT32_C(0x40000010)
242/** End of range 1. */
243#define MSR_GIM_HV_RANGE1_LAST MSR_GIM_HV_VP_RUNTIME
244
245/** Start of range 2. */
246#define MSR_GIM_HV_RANGE2_FIRST UINT32_C(0x40000020)
247/** Per-VM reference counter (R) */
248#define MSR_GIM_HV_TIME_REF_COUNT UINT32_C(0x40000020)
249/** Per-VM TSC page (R/W) */
250#define MSR_GIM_HV_REF_TSC UINT32_C(0x40000021)
251/** Frequency of TSC in Hz as reported by the hypervisor (R) */
252#define MSR_GIM_HV_TSC_FREQ UINT32_C(0x40000022)
253/** Frequency of LAPIC in Hz as reported by the hypervisor (R) */
254#define MSR_GIM_HV_APIC_FREQ UINT32_C(0x40000023)
255/** End of range 2. */
256#define MSR_GIM_HV_RANGE2_LAST MSR_GIM_HV_APIC_FREQ
257
258/** Start of range 3. */
259#define MSR_GIM_HV_RANGE3_FIRST UINT32_C(0x40000070)
260/** Access to APIC EOI (End-Of-Interrupt) register (W) */
261#define MSR_GIM_HV_EOI UINT32_C(0x40000070)
262/** Access to APIC ICR (Interrupt Command) register (R/W) */
263#define MSR_GIM_HV_ICR UINT32_C(0x40000071)
264/** Access to APIC TPR (Task Priority) register (R/W) */
265#define MSR_GIM_HV_TPR UINT32_C(0x40000072)
266/** Enables lazy EOI processing (R/W) */
267#define MSR_GIM_HV_APIC_ASSIST_PAGE UINT32_C(0x40000073)
268/** End of range 3. */
269#define MSR_GIM_HV_RANGE3_LAST MSR_GIM_HV_APIC_ASSIST_PAGE
270
271/** Start of range 4. */
272#define MSR_GIM_HV_RANGE4_FIRST UINT32_C(0x40000080)
273/** Control behaviour of synthetic interrupt controller (R/W) */
274#define MSR_GIM_HV_SCONTROL UINT32_C(0x40000080)
275/** Synthetic interrupt controller version (R) */
276#define MSR_GIM_HV_SVERSION UINT32_C(0x40000081)
277/** Base address of synthetic interrupt event flag (R/W) */
278#define MSR_GIM_HV_SIEFP UINT32_C(0x40000082)
279/** Base address of synthetic interrupt message page (R/W) */
280#define MSR_GIM_HV_SIMP UINT32_C(0x40000083)
281/** End-Of-Message in synthetic interrupt parameter page (W) */
282#define MSR_GIM_HV_EOM UINT32_C(0x40000084)
283/** End of range 4. */
284#define MSR_GIM_HV_RANGE4_LAST MSR_GIM_HV_EOM
285
286/** Start of range 5. */
287#define MSR_GIM_HV_RANGE5_FIRST UINT32_C(0x40000090)
288/** Configures synthetic interrupt source 0 (R/W) */
289#define MSR_GIM_HV_SINT0 UINT32_C(0x40000090)
290/** Configures synthetic interrupt source 1 (R/W) */
291#define MSR_GIM_HV_SINT1 UINT32_C(0x40000091)
292/** Configures synthetic interrupt source 2 (R/W) */
293#define MSR_GIM_HV_SINT2 UINT32_C(0x40000092)
294/** Configures synthetic interrupt source 3 (R/W) */
295#define MSR_GIM_HV_SINT3 UINT32_C(0x40000093)
296/** Configures synthetic interrupt source 4 (R/W) */
297#define MSR_GIM_HV_SINT4 UINT32_C(0x40000094)
298/** Configures synthetic interrupt source 5 (R/W) */
299#define MSR_GIM_HV_SINT5 UINT32_C(0x40000095)
300/** Configures synthetic interrupt source 6 (R/W) */
301#define MSR_GIM_HV_SINT6 UINT32_C(0x40000096)
302/** Configures synthetic interrupt source 7 (R/W) */
303#define MSR_GIM_HV_SINT7 UINT32_C(0x40000097)
304/** Configures synthetic interrupt source 8 (R/W) */
305#define MSR_GIM_HV_SINT8 UINT32_C(0x40000098)
306/** Configures synthetic interrupt source 9 (R/W) */
307#define MSR_GIM_HV_SINT9 UINT32_C(0x40000099)
308/** Configures synthetic interrupt source 10 (R/W) */
309#define MSR_GIM_HV_SINT10 UINT32_C(0x4000009A)
310/** Configures synthetic interrupt source 11 (R/W) */
311#define MSR_GIM_HV_SINT11 UINT32_C(0x4000009B)
312/** Configures synthetic interrupt source 12 (R/W) */
313#define MSR_GIM_HV_SINT12 UINT32_C(0x4000009C)
314/** Configures synthetic interrupt source 13 (R/W) */
315#define MSR_GIM_HV_SINT13 UINT32_C(0x4000009D)
316/** Configures synthetic interrupt source 14 (R/W) */
317#define MSR_GIM_HV_SINT14 UINT32_C(0x4000009E)
318/** Configures synthetic interrupt source 15 (R/W) */
319#define MSR_GIM_HV_SINT15 UINT32_C(0x4000009F)
320/** End of range 5. */
321#define MSR_GIM_HV_RANGE5_LAST MSR_GIM_HV_SINT15
322
323/** Start of range 6. */
324#define MSR_GIM_HV_RANGE6_FIRST UINT32_C(0x400000B0)
325/** Configures register for synthetic timer 0 (R/W) */
326#define MSR_GIM_HV_STIMER0_CONFIG UINT32_C(0x400000B0)
327/** Expiration time or period for synthetic timer 0 (R/W) */
328#define MSR_GIM_HV_STIMER0_COUNT UINT32_C(0x400000B1)
329/** Configures register for synthetic timer 1 (R/W) */
330#define MSR_GIM_HV_STIMER1_CONFIG UINT32_C(0x400000B2)
331/** Expiration time or period for synthetic timer 1 (R/W) */
332#define MSR_GIM_HV_STIMER1_COUNT UINT32_C(0x400000B3)
333/** Configures register for synthetic timer 2 (R/W) */
334#define MSR_GIM_HV_STIMER2_CONFIG UINT32_C(0x400000B4)
335/** Expiration time or period for synthetic timer 2 (R/W) */
336#define MSR_GIM_HV_STIMER2_COUNT UINT32_C(0x400000B5)
337/** Configures register for synthetic timer 3 (R/W) */
338#define MSR_GIM_HV_STIMER3_CONFIG UINT32_C(0x400000B6)
339/** Expiration time or period for synthetic timer 3 (R/W) */
340#define MSR_GIM_HV_STIMER3_COUNT UINT32_C(0x400000B7)
341/** End of range 6. */
342#define MSR_GIM_HV_RANGE6_LAST MSR_GIM_HV_STIMER3_COUNT
343
344/** Start of range 7. */
345#define MSR_GIM_HV_RANGE7_FIRST UINT32_C(0x400000C1)
346/** Trigger to transition to power state C1 (R) */
347#define MSR_GIM_HV_POWER_STATE_TRIGGER_C1 UINT32_C(0x400000C1)
348/** Trigger to transition to power state C2 (R) */
349#define MSR_GIM_HV_POWER_STATE_TRIGGER_C2 UINT32_C(0x400000C2)
350/** Trigger to transition to power state C3 (R) */
351#define MSR_GIM_HV_POWER_STATE_TRIGGER_C3 UINT32_C(0x400000C3)
352/** End of range 7. */
353#define MSR_GIM_HV_RANGE7_LAST MSR_GIM_HV_POWER_STATE_TRIGGER_C3
354
355/** Start of range 8. */
356#define MSR_GIM_HV_RANGE8_FIRST UINT32_C(0x400000D1)
357/** Configure the recipe for power state transitions to C1 (R/W) */
358#define MSR_GIM_HV_POWER_STATE_CONFIG_C1 UINT32_C(0x400000D1)
359/** Configure the recipe for power state transitions to C2 (R/W) */
360#define MSR_GIM_HV_POWER_STATE_CONFIG_C2 UINT32_C(0x400000D2)
361/** Configure the recipe for power state transitions to C3 (R/W) */
362#define MSR_GIM_HV_POWER_STATE_CONFIG_C3 UINT32_C(0x400000D3)
363/** End of range 8. */
364#define MSR_GIM_HV_RANGE8_LAST MSR_GIM_HV_POWER_STATE_CONFIG_C3
365
366/** Start of range 9. */
367#define MSR_GIM_HV_RANGE9_FIRST UINT32_C(0x400000E0)
368/** Map the guest's retail partition stats page (R/W) */
369#define MSR_GIM_HV_STATS_PART_RETAIL_PAGE UINT32_C(0x400000E0)
370/** Map the guest's internal partition stats page (R/W) */
371#define MSR_GIM_HV_STATS_PART_INTERNAL_PAGE UINT32_C(0x400000E1)
372/** Map the guest's retail VP stats page (R/W) */
373#define MSR_GIM_HV_STATS_VP_RETAIL_PAGE UINT32_C(0x400000E2)
374/** Map the guest's internal VP stats page (R/W) */
375#define MSR_GIM_HV_STATS_VP_INTERNAL_PAGE UINT32_C(0x400000E3)
376/** End of range 9. */
377#define MSR_GIM_HV_RANGE9_LAST MSR_GIM_HV_STATS_VP_INTERNAL_PAGE
378
379/** Start of range 10. */
380#define MSR_GIM_HV_RANGE10_FIRST UINT32_C(0x400000F0)
381/** Trigger the guest's transition to idle power state (R) */
382#define MSR_GIM_HV_GUEST_IDLE UINT32_C(0x400000F0)
383/** Synthetic debug control. */
384#define MSR_GIM_HV_SYNTH_DEBUG_CONTROL UINT32_C(0x400000F1)
385/** Synthetic debug status. */
386#define MSR_GIM_HV_SYNTH_DEBUG_STATUS UINT32_C(0x400000F2)
387/** Synthetic debug send buffer. */
388#define MSR_GIM_HV_SYNTH_DEBUG_SEND_BUFFER UINT32_C(0x400000F3)
389/** Synthetic debug receive buffer. */
390#define MSR_GIM_HV_SYNTH_DEBUG_RECEIVE_BUFFER UINT32_C(0x400000F4)
391/** Synthetic debug pending buffer. */
392#define MSR_GIM_HV_SYNTH_DEBUG_PENDING_BUFFER UINT32_C(0x400000F5)
393/** End of range 10. */
394#define MSR_GIM_HV_RANGE10_LAST MSR_GIM_HV_SYNTH_DEBUG_PENDING_BUFFER
395
396/** Start of range 11. */
397#define MSR_GIM_HV_RANGE11_FIRST UINT32_C(0x400000FF)
398/** Undocumented debug options MSR. */
399#define MSR_GIM_HV_DEBUG_OPTIONS_MSR UINT32_C(0x400000FF)
400/** End of range 11. */
401#define MSR_GIM_HV_RANGE11_LAST MSR_GIM_HV_DEBUG_OPTIONS_MSR
402
403/** Start of range 12. */
404#define MSR_GIM_HV_RANGE12_FIRST UINT32_C(0x40000100)
405/** Guest crash MSR 0. */
406#define MSR_GIM_HV_CRASH_P0 UINT32_C(0x40000100)
407/** Guest crash MSR 1. */
408#define MSR_GIM_HV_CRASH_P1 UINT32_C(0x40000101)
409/** Guest crash MSR 2. */
410#define MSR_GIM_HV_CRASH_P2 UINT32_C(0x40000102)
411/** Guest crash MSR 3. */
412#define MSR_GIM_HV_CRASH_P3 UINT32_C(0x40000103)
413/** Guest crash MSR 4. */
414#define MSR_GIM_HV_CRASH_P4 UINT32_C(0x40000104)
415/** Guest crash control. */
416#define MSR_GIM_HV_CRASH_CTL UINT32_C(0x40000105)
417/** End of range 12. */
418#define MSR_GIM_HV_RANGE12_LAST MSR_GIM_HV_CRASH_CTL
419/** @} */
420
421AssertCompile(MSR_GIM_HV_RANGE0_FIRST <= MSR_GIM_HV_RANGE0_LAST);
422AssertCompile(MSR_GIM_HV_RANGE1_FIRST <= MSR_GIM_HV_RANGE1_LAST);
423AssertCompile(MSR_GIM_HV_RANGE2_FIRST <= MSR_GIM_HV_RANGE2_LAST);
424AssertCompile(MSR_GIM_HV_RANGE3_FIRST <= MSR_GIM_HV_RANGE3_LAST);
425AssertCompile(MSR_GIM_HV_RANGE4_FIRST <= MSR_GIM_HV_RANGE4_LAST);
426AssertCompile(MSR_GIM_HV_RANGE5_FIRST <= MSR_GIM_HV_RANGE5_LAST);
427AssertCompile(MSR_GIM_HV_RANGE6_FIRST <= MSR_GIM_HV_RANGE6_LAST);
428AssertCompile(MSR_GIM_HV_RANGE7_FIRST <= MSR_GIM_HV_RANGE7_LAST);
429AssertCompile(MSR_GIM_HV_RANGE8_FIRST <= MSR_GIM_HV_RANGE8_LAST);
430AssertCompile(MSR_GIM_HV_RANGE9_FIRST <= MSR_GIM_HV_RANGE9_LAST);
431AssertCompile(MSR_GIM_HV_RANGE10_FIRST <= MSR_GIM_HV_RANGE10_LAST);
432AssertCompile(MSR_GIM_HV_RANGE11_FIRST <= MSR_GIM_HV_RANGE11_LAST);
433
434/** @name Hyper-V MSR - Reset (MSR_GIM_HV_RESET).
435 * @{
436 */
437/** The reset enable mask. */
438#define MSR_GIM_HV_RESET_ENABLE RT_BIT_64(0)
439/** Whether the reset MSR is enabled. */
440#define MSR_GIM_HV_RESET_IS_ENABLED(a) RT_BOOL((a) & MSR_GIM_HV_RESET_ENABLE)
441/** @} */
442
443/** @name Hyper-V MSR - Hypercall (MSR_GIM_HV_HYPERCALL).
444 * @{
445 */
446/** Guest-physical page frame number of the hypercall-page. */
447#define MSR_GIM_HV_HYPERCALL_GUEST_PFN(a) ((a) >> 12)
448/** The hypercall enable mask. */
449#define MSR_GIM_HV_HYPERCALL_PAGE_ENABLE RT_BIT_64(0)
450/** Whether the hypercall-page is enabled or not. */
451#define MSR_GIM_HV_HYPERCALL_PAGE_IS_ENABLED(a) RT_BOOL((a) & MSR_GIM_HV_HYPERCALL_PAGE_ENABLE)
452/** @} */
453
454/** @name Hyper-V MSR - Reference TSC (MSR_GIM_HV_REF_TSC).
455 * @{
456 */
457/** Guest-physical page frame number of the TSC-page. */
458#define MSR_GIM_HV_REF_TSC_GUEST_PFN(a) ((a) >> 12)
459/** The TSC-page enable mask. */
460#define MSR_GIM_HV_REF_TSC_ENABLE RT_BIT_64(0)
461/** Whether the TSC-page is enabled or not. */
462#define MSR_GIM_HV_REF_TSC_IS_ENABLED(a) RT_BOOL((a) & MSR_GIM_HV_REF_TSC_ENABLE)
463/** @} */
464
465/** @name Hyper-V MSR - Guest crash control (MSR_GIM_HV_CRASH_CTL).
466 * @{
467 */
468/** The Crash Control notify mask. */
469#define MSR_GIM_HV_CRASH_CTL_NOTIFY RT_BIT_64(63)
470/** @} */
471
472/** @name Hyper-V MSR - Guest OS ID (MSR_GIM_HV_GUEST_OS_ID).
473 * @{
474 */
475/** An open-source operating system. */
476#define MSR_GIM_HV_GUEST_OS_ID_IS_OPENSOURCE(a) RT_BOOL((a) & RT_BIT_64(63))
477/** Vendor ID. */
478#define MSR_GIM_HV_GUEST_OS_ID_VENDOR(a) (uint32_t)(((a) >> 48) & 0xfff)
479/** Guest OS variant, depending on the vendor ID. */
480#define MSR_GIM_HV_GUEST_OS_ID_OS_VARIANT(a) (uint32_t)(((a) >> 40) & 0xff)
481/** Guest OS major version. */
482#define MSR_GIM_HV_GUEST_OS_ID_MAJOR_VERSION(a) (uint32_t)(((a) >> 32) & 0xff)
483/** Guest OS minor version. */
484#define MSR_GIM_HV_GUEST_OS_ID_MINOR_VERSION(a) (uint32_t)(((a) >> 24) & 0xff)
485/** Guest OS service version (e.g. service pack number in case of Windows). */
486#define MSR_GIM_HV_GUEST_OS_ID_SERVICE_VERSION(a) (uint32_t)(((a) >> 16) & 0xff)
487/** Guest OS build number. */
488#define MSR_GIM_HV_GUEST_OS_ID_BUILD(a) (uint32_t)((a) & 0xffff)
489/** @} */
490
491/** @name Hyper-V MSR - APIC-assist page (MSR_GIM_HV_APIC_ASSIST_PAGE).
492 * @{
493 */
494/** Guest-physical page frame number of the APIC-assist page. */
495#define MSR_GIM_HV_APICASSIST_GUEST_PFN(a) ((a) >> 12)
496/** The APIC-assist page enable mask. */
497#define MSR_GIM_HV_APICASSIST_PAGE_ENABLE RT_BIT_64(0)
498/** Whether the APIC-assist page is enabled or not. */
499#define MSR_GIM_HV_APICASSIST_PAGE_IS_ENABLED(a) RT_BOOL((a) & MSR_GIM_HV_APICASSIST_PAGE_ENABLE)
500/** @} */
501
502/** @name Hyper-V MSR - Synthetic Interrupt Event Flags page
503 * (MSR_GIM_HV_SIEFP).
504 * @{
505 */
506/** Guest-physical page frame number of the APIC-assist page. */
507#define MSR_GIM_HV_SIEF_GUEST_PFN(a) ((a) >> 12)
508/** The SIEF enable mask. */
509#define MSR_GIM_HV_SIEF_PAGE_ENABLE RT_BIT_64(0)
510/** Whether the SIEF page is enabled or not. */
511#define MSR_GIM_HV_SIEF_PAGE_IS_ENABLED(a) RT_BOOL((a) & MSR_GIM_HV_SIEF_PAGE_ENABLE)
512/** @} */
513
514/** @name Hyper-V MSR - Synthetic Interrupt Control (MSR_GIM_HV_CONTROL).
515 * @{
516 */
517/** The SControl enable mask. */
518#define MSR_GIM_HV_SCONTROL_ENABLE RT_BIT_64(0)
519/** Whether SControl is enabled or not. */
520#define MSR_GIM_HV_SCONTROL_IS_ENABLED(a) RT_BOOL((a) & MSR_GIM_HV_SCONTROL_ENABLE)
521/** @} */
522
523/** @name Hyper-V MSR - Synthetic Timer Config (MSR_GIM_HV_STIMER_CONFIG).
524 * @{
525 */
526/** The Stimer enable mask. */
527#define MSR_GIM_HV_STIMER_ENABLE RT_BIT_64(0)
528/** Whether Stimer is enabled or not. */
529#define MSR_GIM_HV_STIMER_IS_ENABLED(a) RT_BOOL((a) & MSR_GIM_HV_STIMER_ENABLE)
530/** The Stimer periodic mask. */
531#define MSR_GIM_HV_STIMER_PERIODIC RT_BIT_64(1)
532/** Whether Stimer is enabled or not. */
533#define MSR_GIM_HV_STIMER_IS_PERIODIC(a) RT_BOOL((a) & MSR_GIM_HV_STIMER_PERIODIC)
534/** The Stimer lazy mask. */
535#define MSR_GIM_HV_STIMER_LAZY RT_BIT_64(2)
536/** Whether Stimer is enabled or not. */
537#define MSR_GIM_HV_STIMER_IS_LAZY(a) RT_BOOL((a) & MSR_GIM_HV_STIMER_LAZY)
538/** The Stimer auto-enable mask. */
539#define MSR_GIM_HV_STIMER_AUTO_ENABLE RT_BIT_64(3)
540/** Whether Stimer is enabled or not. */
541#define MSR_GIM_HV_STIMER_IS_AUTO_ENABLED(a) RT_BOOL((a) & MSR_GIM_HV_STIMER_AUTO_ENABLE)
542/** The Stimer SINTx mask (bits 16:19). */
543#define MSR_GIM_HV_STIMER_SINTX UINT64_C(0xf0000)
544/** Gets the Stimer synthetic interrupt source. */
545#define MSR_GIM_HV_STIMER_GET_SINTX(a) (((a) >> 16) & 0xf)
546/** The Stimer valid read/write mask. */
547#define MSR_GIM_HV_STIMER_RW_VALID ( MSR_GIM_HV_STIMER_ENABLE | MSR_GIM_HV_STIMER_PERIODIC \
548 | MSR_GIM_HV_STIMER_LAZY | MSR_GIM_HV_STIMER_AUTO_ENABLE \
549 | MSR_GIM_HV_STIMER_SINTX)
550/** @} */
551
552/**
553 * Hyper-V APIC-assist (HV_REFERENCE_TSC_PAGE) structure placed in the TSC
554 * reference page.
555 */
556typedef struct GIMHVAPICASSIST
557{
558 uint32_t fNoEoiRequired : 1;
559 uint32_t u31Reserved0 : 31;
560} GIMHVAPICASSIST;
561/** Pointer to Hyper-V reference TSC. */
562typedef GIMHVAPICASSIST *PGIMHVAPICASSIST;
563/** Pointer to a const Hyper-V reference TSC. */
564typedef GIMHVAPICASSIST const *PCGIMHVAPICASSIST;
565AssertCompileSize(GIMHVAPICASSIST, 4);
566
567/**
568 * Hypercall parameter type.
569 */
570typedef enum GIMHVHYPERCALLPARAM
571{
572 GIMHVHYPERCALLPARAM_IN = 0,
573 GIMHVHYPERCALLPARAM_OUT
574} GIMHVHYPERCALLPARAM;
575
576
577/** @name Hyper-V hypercall op codes.
578 * @{
579 */
580/** Post message to hypervisor or VMs. */
581#define GIM_HV_HYPERCALL_OP_POST_MESSAGE 0x5C
582/** Post debug data to hypervisor. */
583#define GIM_HV_HYPERCALL_OP_POST_DEBUG_DATA 0x69
584/** Retreive debug data from hypervisor. */
585#define GIM_HV_HYPERCALL_OP_RETREIVE_DEBUG_DATA 0x6A
586/** Reset debug session. */
587#define GIM_HV_HYPERCALL_OP_RESET_DEBUG_SESSION 0x6B
588/** @} */
589
590/** @name Hyper-V extended hypercall op codes.
591 * @{
592 */
593/** Query extended hypercall capabilities. */
594#define GIM_HV_EXT_HYPERCALL_OP_QUERY_CAP 0x8001
595/** Query guest physical address range that has zero'd filled memory. */
596#define GIM_HV_EXT_HYPERCALL_OP_GET_BOOT_ZEROED_MEM 0x8002
597/** @} */
598
599
600/** @name Hyper-V Extended hypercall - HvExtCallQueryCapabilities.
601 * @{
602 */
603/** Boot time zeroed pages. */
604#define GIM_HV_EXT_HYPERCALL_CAP_ZERO_MEM RT_BIT_64(0)
605/** Whether boot time zeroed pages capability is enabled. */
606#define GIM_HV_EXT_HYPERCALL_CAP_IS_ZERO_MEM_ENABLED(a) RT_BOOL((a) & GIM_HV_EXT_HYPERCALL_CAP_ZERO_MEM)
607/** @} */
608
609
610/** @name Hyper-V hypercall inputs.
611 * @{
612 */
613/** The hypercall call operation code. */
614#define GIM_HV_HYPERCALL_IN_CALL_CODE(a) ((a) & UINT64_C(0xffff))
615/** Whether it's a fast (register based) hypercall or not (memory-based). */
616#define GIM_HV_HYPERCALL_IN_IS_FAST(a) RT_BOOL((a) & RT_BIT_64(16))
617/** Total number of reps for a rep hypercall. */
618#define GIM_HV_HYPERCALL_IN_REP_COUNT(a) (((a) << 32) & UINT64_C(0xfff))
619/** Rep start index for a rep hypercall. */
620#define GIM_HV_HYPERCALL_IN_REP_START_IDX(a) (((a) << 48) & UINT64_C(0xfff))
621/** Reserved bits range 1. */
622#define GIM_HV_HYPERCALL_IN_RSVD_1(a) (((a) << 17) & UINT64_C(0x7fff))
623/** Reserved bits range 2. */
624#define GIM_HV_HYPERCALL_IN_RSVD_2(a) (((a) << 44) & UINT64_C(0xf))
625/** Reserved bits range 3. */
626#define GIM_HV_HYPERCALL_IN_RSVD_3(a) (((a) << 60) & UINT64_C(0x7))
627/** @} */
628
629
630/** @name Hyper-V hypercall status codes.
631 * @{
632 */
633/** Success. */
634#define GIM_HV_STATUS_SUCCESS 0x00
635/** Unrecognized hypercall. */
636#define GIM_HV_STATUS_INVALID_HYPERCALL_CODE 0x02
637/** Invalid hypercall input (rep count, rsvd bits). */
638#define GIM_HV_STATUS_INVALID_HYPERCALL_INPUT 0x03
639/** Hypercall guest-physical address not 8-byte aligned or crosses page boundary. */
640#define GIM_HV_STATUS_INVALID_ALIGNMENT 0x04
641/** Invalid hypercall parameters. */
642#define GIM_HV_STATUS_INVALID_PARAMETER 0x05
643/** Access denied. */
644#define GIM_HV_STATUS_ACCESS_DENIED 0x06
645/** The partition state not valid for specified op. */
646#define GIM_HV_STATUS_INVALID_PARTITION_STATE 0x07
647/** The hypercall operation could not be performed. */
648#define GIM_HV_STATUS_OPERATION_DENIED 0x08
649/** Specified partition property ID not recognized. */
650#define GIM_HV_STATUS_UNKNOWN_PROPERTY 0x09
651/** Specified partition property value not within range. */
652#define GIM_HV_STATUS_PROPERTY_VALUE_OUT_OF_RANGE 0x0a
653/** Insufficient memory for performing the hypercall. */
654#define GIM_HV_STATUS_INSUFFICIENT_MEMORY 0x0b
655/** Maximum partition depth has been exceeded for the partition hierarchy. */
656#define GIM_HV_STATUS_PARTITION_TOO_DEEP 0x0c
657/** The specified partition ID is not valid. */
658#define GIM_HV_STATUS_INVALID_PARTITION_ID 0x0d
659/** The specified virtual processor index in invalid. */
660#define GIM_HV_STATUS_INVALID_VP_INDEX 0x0e
661/** The specified port ID is not unique or doesn't exist. */
662#define GIM_HV_STATUS_INVALID_PORT_ID 0x11
663/** The specified connection ID is not unique or doesn't exist. */
664#define GIM_HV_STATUS_INVALID_CONNECTION_ID 0x12
665/** The target port doesn't have sufficient buffers for the caller to post a message. */
666#define GIM_HV_STATUS_INSUFFICIENT_BUFFERS 0x13
667/** External interrupt not acknowledged.*/
668#define GIM_HV_STATUS_NOT_ACKNOWLEDGED 0x14
669/** External interrupt acknowledged. */
670#define GIM_HV_STATUS_ACKNOWLEDGED 0x16
671/** Invalid state due to misordering Hv[Save|Restore]PartitionState. */
672#define GIM_HV_STATUS_INVALID_SAVE_RESTORE_STATE 0x17
673/** Operation not perform due to a required feature of SynIc was disabled. */
674#define GIM_HV_STATUS_INVALID_SYNIC_STATE 0x18
675/** Object or value already in use. */
676#define GIM_HV_STATUS_OBJECT_IN_USE 0x19
677/** Invalid proximity domain information. */
678#define GIM_HV_STATUS_INVALID_PROXIMITY_DOMAIN_INFO 0x1A
679/** Attempt to retrieve data failed. */
680#define GIM_HV_STATUS_NO_DATA 0x1B
681/** Debug connection has not recieved any new data since the last time. */
682#define GIM_HV_STATUS_INACTIVE 0x1C
683/** A resource is unavailable for allocation. */
684#define GIM_HV_STATUS_NO_RESOURCES 0x1D
685/** A hypervisor feature is not available to the caller. */
686#define GIM_HV_STATUS_FEATURE_UNAVAILABLE 0x1E
687/** The debug packet returned is partial due to an I/O error. */
688#define GIM_HV_STATUS_PARTIAL_PACKET 0x1F
689/** Processor feature SSE3 unsupported. */
690#define GIM_HV_STATUS_PROC_FEAT_SSE3_NOT_SUPPORTED 0x20
691/** Processor feature LAHSAHF unsupported. */
692#define GIM_HV_STATUS_PROC_FEAT_LAHSAHF_NOT_SUPPORTED 0x21
693/** Processor feature SSSE3 unsupported. */
694#define GIM_HV_STATUS_PROC_FEAT_SSSE3_NOT_SUPPORTED 0x22
695/** Processor feature SSE4.1 unsupported. */
696#define GIM_HV_STATUS_PROC_FEAT_SSE4_1_NOT_SUPPORTED 0x23
697/** Processor feature SSE4.2 unsupported. */
698#define GIM_HV_STATUS_PROC_FEAT_SSE4_2_NOT_SUPPORTED 0x24
699/** Processor feature SSE4A unsupported. */
700#define GIM_HV_STATUS_PROC_FEAT_SSE4A_NOT_SUPPORTED 0x25
701/** Processor feature XOP unsupported. */
702#define GIM_HV_STATUS_PROC_FEAT_XOP_NOT_SUPPORTED 0x26
703/** Processor feature POPCNT unsupported. */
704#define GIM_HV_STATUS_PROC_FEAT_POPCNT_NOT_SUPPORTED 0x27
705/** Processor feature CMPXCHG16B unsupported. */
706#define GIM_HV_STATUS_PROC_FEAT_CMPXCHG16B_NOT_SUPPORTED 0x28
707/** Processor feature ALTMOVCR8 unsupported. */
708#define GIM_HV_STATUS_PROC_FEAT_ALTMOVCR8_NOT_SUPPORTED 0x29
709/** Processor feature LZCNT unsupported. */
710#define GIM_HV_STATUS_PROC_FEAT_LZCNT_NOT_SUPPORTED 0x2A
711/** Processor feature misaligned SSE unsupported. */
712#define GIM_HV_STATUS_PROC_FEAT_MISALIGNED_SSE_NOT_SUPPORTED 0x2B
713/** Processor feature MMX extensions unsupported. */
714#define GIM_HV_STATUS_PROC_FEAT_MMX_EXT_NOT_SUPPORTED 0x2C
715/** Processor feature 3DNow! unsupported. */
716#define GIM_HV_STATUS_PROC_FEAT_3DNOW_NOT_SUPPORTED 0x2D
717/** Processor feature Extended 3DNow! unsupported. */
718#define GIM_HV_STATUS_PROC_FEAT_EXTENDED_3DNOW_NOT_SUPPORTED 0x2E
719/** Processor feature 1GB large page unsupported. */
720#define GIM_HV_STATUS_PROC_FEAT_PAGE_1GB_NOT_SUPPORTED 0x2F
721/** Processor cache line flush size incompatible. */
722#define GIM_HV_STATUS_PROC_CACHE_LINE_FLUSH_SIZE_INCOMPATIBLE 0x30
723/** Processor feature XSAVE unsupported. */
724#define GIM_HV_STATUS_PROC_FEAT_XSAVE_NOT_SUPPORTED 0x31
725/** Processor feature XSAVEOPT unsupported. */
726#define GIM_HV_STATUS_PROC_FEAT_XSAVEOPT_NOT_SUPPORTED 0x32
727/** The specified buffer was too small for all requested data. */
728#define GIM_HV_STATUS_INSUFFICIENT_BUFFER 0x33
729/** Processor feature XSAVEOPT unsupported. */
730#define GIM_HV_STATUS_PROC_FEAT_XSAVE_AVX_NOT_SUPPORTED 0x34
731/** Processor feature XSAVEOPT unsupported. */
732#define GIM_HV_STATUS_PROC_FEAT_XSAVE_FEAT_NOT_SUPPORTED 0x35 /** Huh, isn't this same as 0x31? */
733/** Processor feature XSAVEOPT unsupported. */
734#define GIM_HV_STATUS_PROC_FEAT_PAGE_XSAVE_SAVE_AREA_INCOMPATIBLE 0x36
735/** Processor architecture unsupoorted. */
736#define GIM_HV_STATUS_INCOMPATIBLE_PROCESSOR 0x37
737/** Max. domains for platform I/O remapping reached. */
738#define GIM_HV_STATUS_INSUFFICIENT_DEVICE_DOMAINS 0x38
739/** Processor feature AES unsupported. */
740#define GIM_HV_STATUS_PROC_FEAT_AES_NOT_SUPPORTED 0x39
741/** Processor feature PCMULQDQ unsupported. */
742#define GIM_HV_STATUS_PROC_FEAT_PCMULQDQ_NOT_SUPPORTED 0x3A
743/** Processor feature XSAVE features unsupported. */
744#define GIM_HV_STATUS_PROC_FEAT_XSAVE_FEATURES_INCOMPATIBLE 0x3B
745/** Generic CPUID validation error. */
746#define GIM_HV_STATUS_CPUID_FEAT_VALIDATION_ERROR 0x3C
747/** XSAVE CPUID validation error. */
748#define GIM_HV_STATUS_CPUID_XSAVE_FEAT_VALIDATION_ERROR 0x3D
749/** Processor startup timed out. */
750#define GIM_HV_STATUS_PROCESSOR_STARTUP_TIMEOUT 0x3E
751/** SMX enabled by the BIOS. */
752#define GIM_HV_STATUS_SMX_ENABLED 0x3F
753/** Processor feature PCID unsupported. */
754#define GIM_HV_STATUS_PROC_FEAT_PCID_NOT_SUPPORTED 0x40
755/** Invalid LP index. */
756#define GIM_HV_STATUS_INVALID_LP_INDEX 0x41
757/** Processor feature PCID unsupported. */
758#define GIM_HV_STATUS_FEAT_FMA4_NOT_SUPPORTED 0x42
759/** Processor feature PCID unsupported. */
760#define GIM_HV_STATUS_FEAT_F16C_NOT_SUPPORTED 0x43
761/** Processor feature PCID unsupported. */
762#define GIM_HV_STATUS_PROC_FEAT_RDRAND_NOT_SUPPORTED 0x44
763/** Processor feature RDWRFSGS unsupported. */
764#define GIM_HV_STATUS_PROC_FEAT_RDWRFSGS_NOT_SUPPORTED 0x45
765/** Processor feature SMEP unsupported. */
766#define GIM_HV_STATUS_PROC_FEAT_SMEP_NOT_SUPPORTED 0x46
767/** Processor feature enhanced fast string unsupported. */
768#define GIM_HV_STATUS_PROC_FEAT_ENHANCED_FAST_STRING_NOT_SUPPORTED 0x47
769/** Processor feature MOVBE unsupported. */
770#define GIM_HV_STATUS_PROC_FEAT_MOVBE_NOT_SUPPORTED 0x48
771/** Processor feature BMI1 unsupported. */
772#define GIM_HV_STATUS_PROC_FEAT_BMI1_NOT_SUPPORTED 0x49
773/** Processor feature BMI2 unsupported. */
774#define GIM_HV_STATUS_PROC_FEAT_BMI2_NOT_SUPPORTED 0x4A
775/** Processor feature HLE unsupported. */
776#define GIM_HV_STATUS_PROC_FEAT_HLE_NOT_SUPPORTED 0x4B
777/** Processor feature RTM unsupported. */
778#define GIM_HV_STATUS_PROC_FEAT_RTM_NOT_SUPPORTED 0x4C
779/** Processor feature XSAVE FMA unsupported. */
780#define GIM_HV_STATUS_PROC_FEAT_XSAVE_FMA_NOT_SUPPORTED 0x4D
781/** Processor feature XSAVE AVX2 unsupported. */
782#define GIM_HV_STATUS_PROC_FEAT_XSAVE_AVX2_NOT_SUPPORTED 0x4E
783/** Processor feature NPIEP1 unsupported. */
784#define GIM_HV_STATUS_PROC_FEAT_NPIEP1_NOT_SUPPORTED 0x4F
785/** @} */
786
787
788/** @name Hyper-V MSR - Debug control (MSR_GIM_HV_SYNTH_DEBUG_CONTROL).
789 * @{
790 */
791/** Perform debug write. */
792#define MSR_GIM_HV_SYNTH_DEBUG_CONTROL_IS_WRITE(a) RT_BOOL((a) & RT_BIT_64(0))
793/** Perform debug read. */
794#define MSR_GIM_HV_SYNTH_DEBUG_CONTROL_IS_READ(a) RT_BOOL((a) & RT_BIT_64(1))
795/** Returns length of the debug write buffer. */
796#define MSR_GIM_HV_SYNTH_DEBUG_CONTROL_W_LEN(a) (((a) & UINT64_C(0xffff0000)) >> 16)
797/** @} */
798
799
800/** @name Hyper-V MSR - Debug status (MSR_GIM_HV_SYNTH_DEBUG_STATUS).
801 * @{
802 */
803/** Debug send buffer operation success. */
804#define MSR_GIM_HV_SYNTH_DEBUG_STATUS_W_SUCCESS RT_BIT_64(0)
805/** Debug receive buffer operation success. */
806#define MSR_GIM_HV_SYNTH_DEBUG_STATUS_R_SUCCESS RT_BIT_64(2)
807/** Debug connection was reset. */
808#define MSR_GIM_HV_SYNTH_DEBUG_STATUS_CONN_RESET RT_BIT_64(3)
809/** @} */
810
811
812/** @name Hyper-V MSR - synthetic interrupt (MSR_GIM_HV_SINTx).
813 * @{
814 */
815/** The interrupt masked mask. */
816#define MSR_GIM_HV_SINT_MASKED RT_BIT_64(16)
817/** Whether the interrupt source is masked. */
818#define MSR_GIM_HV_SINT_IS_MASKED(a) RT_BOOL((a) & MSR_GIM_HV_SINT_MASKED)
819/** Gets the interrupt vector. */
820#define MSR_GIM_HV_SINT_GET_VECTOR(a) ((a) & UINT64_C(0xff))
821/** The AutoEoi mask. */
822#define MSR_GIM_HV_SINT_AUTOEOI RT_BIT_64(17)
823/** Gets whether AutoEoi is enabled for the synthetic interrupt. */
824#define MSR_GIM_HV_SINT_IS_AUTOEOI(a) RT_BOOL((a) & MSR_GIM_HV_SINT_AUTOEOI)
825/** @} */
826
827
828/** @name Hyper-V MSR - synthetic interrupt message page (MSR_GIM_HV_SIMP).
829 * @{
830 */
831/** The SIMP enable mask. */
832#define MSR_GIM_HV_SIMP_ENABLE RT_BIT_64(0)
833/** Whether the SIMP is enabled. */
834#define MSR_GIM_HV_SIMP_IS_ENABLED(a) RT_BOOL((a) & MSR_GIM_HV_SIMP_ENABLE)
835/** The SIMP guest-physical address. */
836#define MSR_GIM_HV_SIMP_GPA(a) ((a) & UINT64_C(0xfffffffffffff000))
837/** @} */
838
839
840/** @name Hyper-V hypercall debug options.
841 * @{ */
842/** Maximum debug data payload size in bytes. */
843#define GIM_HV_DEBUG_MAX_DATA_SIZE 4088
844
845/** The undocumented bit for MSR_GIM_HV_DEBUG_OPTIONS_MSR that makes it all
846 * work. */
847#define GIM_HV_DEBUG_OPTIONS_USE_HYPERCALLS RT_BIT(2)
848
849/** Guest will perform the HvPostDebugData hypercall until completion. */
850#define GIM_HV_DEBUG_POST_LOOP RT_BIT_32(0)
851/** Mask of valid HvPostDebugData options. */
852#define GIM_HV_DEBUG_POST_OPTIONS_MASK RT_BIT_32(0)
853
854/** Guest will perform the HvRetrieveDebugData hypercall until completion. */
855#define GIM_HV_DEBUG_RETREIVE_LOOP RT_BIT_32(0)
856/** Guest checks if any global debug session is active. */
857#define GIM_HV_DEBUG_RETREIVE_TEST_ACTIVITY RT_BIT_32(1)
858/** Mask of valid HvRetrieveDebugData options. */
859#define GIM_HV_DEBUG_RETREIVE_OPTIONS_MASK RT_BIT_32(0) | RT_BIT_32(1)
860
861/** Guest requests purging of incoming debug data. */
862#define GIM_HV_DEBUG_PURGE_INCOMING_DATA RT_BIT_32(0)
863/** Guest requests purging of outgoing debug data. */
864#define GIM_HV_DEBUG_PURGE_OUTGOING_DATA RT_BIT_32(1)
865/** @}*/
866
867
868/** @name VMBus.
869 * These are just arbitrary definitions made up by Microsoft without
870 * any publicly available specification behind it.
871 * @{ */
872/** VMBus connection ID. */
873#define GIM_HV_VMBUS_MSG_CONNECTION_ID 1
874/** VMBus synthetic interrupt source (see VMBUS_MESSAGE_SINT in linux
875 * sources). */
876#define GIM_HV_VMBUS_MSG_SINT 2
877/** @} */
878
879/** @name SynIC.
880 * Synthetic Interrupt Controller definitions.
881 */
882/** SynIC version register. */
883#define GIM_HV_SVERSION 1
884/** Number of synthetic interrupt sources (warning, fixed in saved-states!). */
885#define GIM_HV_SINT_COUNT 16
886/** Lowest valid vector for synthetic interrupt. */
887#define GIM_HV_SINT_VECTOR_VALID_MIN 16
888/** Highest valid vector for synthetic interrupt. */
889#define GIM_HV_SINT_VECTOR_VALID_MAX 255
890/** Number of synthetic timers. */
891#define GIM_HV_STIMER_COUNT 4
892/** @} */
893
894/** @name Hyper-V synthetic interrupt message type.
895 * See 14.8.2 "SynIC Message Types"
896 * @{
897 */
898typedef enum GIMHVMSGTYPE
899{
900 GIMHVMSGTYPE_NONE = 0, /* Common messages */
901 GIMHVMSGTYPE_VMBUS = 1, /* Guest messages */
902 GIMHVMSGTYPE_UNMAPPEDGPA = 0x80000000, /* Hypervisor messages */
903 GIMHVMSGTYPE_GPAINTERCEPT = 0x80000001,
904 GIMHVMSGTYPE_TIMEREXPIRED = 0x80000010,
905 GIMHVMSGTYPE_INVALIDVPREGVAL = 0x80000020,
906 GIMHVMSGTYPE_UNRECOVERABLEXCPT = 0x80000021,
907 GIMHVMSGTYPE_UNSUPPORTEDFEAT = 0x80000022,
908 GIMHVMSGTYPE_APICEOI = 0x80000030,
909 GIMHVMSGTYPE_X64LEGACYFPERROR = 0x80000031,
910 GIMHVMSGTYPE_EVENTLOGBUFSCOMPLETE = 0x80000040,
911 GIMHVMSGTYPE_X64IOPORTINTERCEPT = 0x80010000,
912 GIMHVMSGTYPE_X64MSRINTERCEPT = 0x80010001,
913 GIMHVMSGTYPE_X64CPUIDINTERCEPT = 0x80010002,
914 GIMHVMSGTYPE_X64XCPTINTERCEPT = 0x80010003
915} GIMHVMSGTYPE;
916AssertCompileSize(GIMHVMSGTYPE, 4);
917/** @} */
918
919
920/** @name Hyper-V synthetic interrupt message format.
921 * @{ */
922#define GIM_HV_MSG_SIZE 256
923#define GIM_HV_MSG_MAX_PAYLOAD_SIZE 240
924#define GIM_HV_MSG_MAX_PAYLOAD_UNITS 30
925
926/**
927 * Synthetic interrupt message flags.
928 */
929typedef union GIMHVMSGFLAGS
930{
931 struct
932 {
933 uint8_t u1Pending : 1;
934 uint8_t u7Reserved : 7;
935 } n;
936 uint8_t u;
937} GIMHVMSGFLAGS;
938AssertCompileSize(GIMHVMSGFLAGS, sizeof(uint8_t));
939
940/**
941 * Synthetic interrupt message header.
942 *
943 * @remarks The layout of this structure differs from
944 * the Hyper-V spec. Aug 8, 2013 v4.0a. Layout
945 * in accordance w/ VMBus client expectations.
946 */
947typedef struct GIMHVMSGHDR
948{
949 GIMHVMSGTYPE enmMessageType;
950 uint8_t cbPayload;
951 GIMHVMSGFLAGS MessageFlags;
952 uint16_t uRsvd;
953 union
954 {
955 uint64_t uOriginatorId;
956 uint64_t uPartitionId;
957 uint64_t uPortId;
958 } msgid;
959} GIMHVMSGHDR;
960/** Pointer to a synthetic interrupt message header. */
961typedef GIMHVMSGHDR *PGIMHVMSGHDR;
962AssertCompileMemberOffset(GIMHVMSGHDR, cbPayload, 4);
963AssertCompileMemberOffset(GIMHVMSGHDR, MessageFlags, 5);
964AssertCompileMemberOffset(GIMHVMSGHDR, msgid, 8);
965AssertCompileSize(GIMHVMSGHDR, GIM_HV_MSG_SIZE - GIM_HV_MSG_MAX_PAYLOAD_SIZE);
966
967/**
968 * Synthetic interrupt message.
969 */
970typedef struct GIMHVMSG
971{
972 GIMHVMSGHDR MsgHdr;
973 uint64_t aPayload[GIM_HV_MSG_MAX_PAYLOAD_UNITS];
974} GIMHVMSG;
975/** Pointer to a synthetic interrupt message. */
976typedef GIMHVMSG *PGIMHVMSG;
977AssertCompileSize(GIMHVMSG, GIM_HV_MSG_SIZE);
978/** @} */
979
980
981/** @name Hyper-V hypercall parameters.
982 * @{ */
983/**
984 * HvPostMessage hypercall input.
985 */
986typedef struct GIMHVPOSTMESSAGEIN
987{
988 uint32_t uConnectionId;
989 uint32_t uPadding;
990 GIMHVMSGTYPE enmMessageType;
991 uint32_t cbPayload;
992} GIMHVPOSTMESSAGEIN;
993/** Pointer to a HvPostMessage input struct. */
994typedef GIMHVPOSTMESSAGEIN *PGIMHVPOSTMESSAGEIN;
995AssertCompileSize(GIMHVPOSTMESSAGEIN, 16);
996
997/**
998 * HvResetDebugData hypercall input.
999 */
1000typedef struct GIMHVDEBUGRESETIN
1001{
1002 uint32_t fFlags;
1003 uint32_t uPadding;
1004} GIMHVDEBUGRESETIN;
1005/** Pointer to a HvResetDebugData input struct. */
1006typedef GIMHVDEBUGRESETIN *PGIMHVDEBUGRESETIN;
1007AssertCompileSize(GIMHVDEBUGRESETIN, 8);
1008
1009/**
1010 * HvPostDebugData hypercall input.
1011 */
1012typedef struct GIMHVDEBUGPOSTIN
1013{
1014 uint32_t cbWrite;
1015 uint32_t fFlags;
1016} GIMHVDEBUGPOSTIN;
1017/** Pointer to a HvPostDebugData input struct. */
1018typedef GIMHVDEBUGPOSTIN *PGIMHVDEBUGPOSTIN;
1019AssertCompileSize(GIMHVDEBUGPOSTIN, 8);
1020
1021/**
1022 * HvPostDebugData hypercall output.
1023 */
1024typedef struct GIMHVDEBUGPOSTOUT
1025{
1026 uint32_t cbPending;
1027 uint32_t uPadding;
1028} GIMHVDEBUGPOSTOUT;
1029/** Pointer to a HvPostDebugData output struct. */
1030typedef GIMHVDEBUGPOSTOUT *PGIMHVDEBUGPOSTOUT;
1031AssertCompileSize(GIMHVDEBUGPOSTOUT, 8);
1032
1033/**
1034 * HvRetrieveDebugData hypercall input.
1035 */
1036typedef struct GIMHVDEBUGRETRIEVEIN
1037{
1038 uint32_t cbRead;
1039 uint32_t fFlags;
1040 uint64_t u64Timeout;
1041} GIMHVDEBUGRETRIEVEIN;
1042/** Pointer to a HvRetrieveDebugData input struct. */
1043typedef GIMHVDEBUGRETRIEVEIN *PGIMHVDEBUGRETRIEVEIN;
1044AssertCompileSize(GIMHVDEBUGRETRIEVEIN, 16);
1045
1046/**
1047 * HvRetriveDebugData hypercall output.
1048 */
1049typedef struct GIMHVDEBUGRETRIEVEOUT
1050{
1051 uint32_t cbRead;
1052 uint32_t cbRemaining;
1053} GIMHVDEBUGRETRIEVEOUT;
1054/** Pointer to a HvRetrieveDebugData output struct. */
1055typedef GIMHVDEBUGRETRIEVEOUT *PGIMHVDEBUGRETRIEVEOUT;
1056AssertCompileSize(GIMHVDEBUGRETRIEVEOUT, 8);
1057
1058/**
1059 * HvExtCallQueryCapabilities hypercall output.
1060 */
1061typedef struct GIMHVEXTQUERYCAP
1062{
1063 uint64_t fCapabilities;
1064} GIMHVEXTQUERYCAP;
1065/** Pointer to a HvExtCallQueryCapabilities output struct. */
1066typedef GIMHVEXTQUERYCAP *PGIMHVEXTQUERYCAP;
1067AssertCompileSize(GIMHVEXTQUERYCAP, 8);
1068
1069/**
1070 * HvExtCallGetBootZeroedMemory hypercall output.
1071 */
1072typedef struct GIMHVEXTGETBOOTZEROMEM
1073{
1074 RTGCPHYS GCPhysStart;
1075 uint64_t cPages;
1076} GIMHVEXTGETBOOTZEROMEM;
1077/** Pointer to a HvExtCallGetBootZeroedMemory output struct. */
1078typedef GIMHVEXTGETBOOTZEROMEM *PGIMHVEXTGETBOOTZEROMEM;
1079AssertCompileSize(GIMHVEXTGETBOOTZEROMEM, 16);
1080/** @} */
1081
1082
1083/** Hyper-V page size. */
1084#define GIM_HV_PAGE_SIZE 4096
1085/** Hyper-V page shift. */
1086#define GIM_HV_PAGE_SHIFT 12
1087
1088/** Microsoft Hyper-V vendor signature. */
1089#define GIM_HV_VENDOR_MICROSOFT "Microsoft Hv"
1090
1091/**
1092 * MMIO2 region indices.
1093 */
1094/** The hypercall page region. */
1095#define GIM_HV_HYPERCALL_PAGE_REGION_IDX UINT8_C(0)
1096/** The TSC page region. */
1097#define GIM_HV_REF_TSC_PAGE_REGION_IDX UINT8_C(1)
1098/** The maximum region index (must be <= UINT8_MAX). */
1099#define GIM_HV_REGION_IDX_MAX GIM_HV_REF_TSC_PAGE_REGION_IDX
1100
1101/**
1102 * Hyper-V TSC (HV_REFERENCE_TSC_PAGE) structure placed in the TSC reference
1103 * page.
1104 */
1105typedef struct GIMHVREFTSC
1106{
1107 uint32_t u32TscSequence;
1108 uint32_t uReserved0;
1109 uint64_t u64TscScale;
1110 int64_t i64TscOffset;
1111} GIMHVTSCPAGE;
1112/** Pointer to Hyper-V reference TSC. */
1113typedef GIMHVREFTSC *PGIMHVREFTSC;
1114/** Pointer to a const Hyper-V reference TSC. */
1115typedef GIMHVREFTSC const *PCGIMHVREFTSC;
1116
1117/**
1118 * Type of the next reply to be sent to the debug connection of the guest.
1119 *
1120 * @remarks This is saved as part of saved-state, so don't re-order or
1121 * alter the size!
1122 */
1123typedef enum GIMHVDEBUGREPLY
1124{
1125 /** Send UDP packet. */
1126 GIMHVDEBUGREPLY_UDP = 0,
1127 /** Send DHCP offer for DHCP discover. */
1128 GIMHVDEBUGREPLY_DHCP_OFFER,
1129 /** DHCP offer sent. */
1130 GIMHVDEBUGREPLY_DHCP_OFFER_SENT,
1131 /** Send DHCP acknowledgement for DHCP request. */
1132 GIMHVDEBUGREPLY_DHCP_ACK,
1133 /** DHCP acknowledgement sent. */
1134 GIMHVDEBUGREPLY_DHCP_ACK_SENT,
1135 /** Sent ARP reply. */
1136 GIMHVDEBUGREPLY_ARP_REPLY,
1137 /** ARP reply sent. */
1138 GIMHVDEBUGREPLY_ARP_REPLY_SENT,
1139 /** Customary 32-bit type hack. */
1140 GIMHVDEBUGREPLY_32BIT_HACK = 0x7fffffff
1141} GIMHVDEBUGREPLY;
1142AssertCompileSize(GIMHVDEBUGREPLY, sizeof(uint32_t));
1143
1144/**
1145 * GIM Hyper-V VM instance data.
1146 * Changes to this must checked against the padding of the gim union in VM!
1147 */
1148typedef struct GIMHV
1149{
1150 /** @name Primary MSRs.
1151 * @{ */
1152 /** Guest OS identity MSR. */
1153 uint64_t u64GuestOsIdMsr;
1154 /** Hypercall MSR. */
1155 uint64_t u64HypercallMsr;
1156 /** Reference TSC page MSR. */
1157 uint64_t u64TscPageMsr;
1158 /** @} */
1159
1160 /** @name CPUID features.
1161 * @{ */
1162 /** Basic features. */
1163 uint32_t uBaseFeat;
1164 /** Partition flags. */
1165 uint32_t uPartFlags;
1166 /** Power management. */
1167 uint32_t uPowMgmtFeat;
1168 /** Miscellaneous. */
1169 uint32_t uMiscFeat;
1170 /** Hypervisor hints to the guest. */
1171 uint32_t uHyperHints;
1172 /** Hypervisor capabilities. */
1173 uint32_t uHyperCaps;
1174 /** @} */
1175
1176 /** @name Guest Crash MSRs.
1177 * @{
1178 */
1179 /** Guest crash control MSR. */
1180 uint64_t uCrashCtlMsr;
1181 /** Guest crash parameter 0 MSR. */
1182 uint64_t uCrashP0Msr;
1183 /** Guest crash parameter 1 MSR. */
1184 uint64_t uCrashP1Msr;
1185 /** Guest crash parameter 2 MSR. */
1186 uint64_t uCrashP2Msr;
1187 /** Guest crash parameter 3 MSR. */
1188 uint64_t uCrashP3Msr;
1189 /** Guest crash parameter 4 MSR. */
1190 uint64_t uCrashP4Msr;
1191 /** @} */
1192
1193 /** @name Time management.
1194 * @{ */
1195 /** Per-VM R0 Spinlock for protecting EMT writes to the TSC page. */
1196 RTSPINLOCK hSpinlockR0;
1197#if HC_ARCH_BITS == 32
1198 uint32_t u32Alignment1;
1199#endif
1200 /** The TSC frequency (in HZ) reported to the guest. */
1201 uint64_t cTscTicksPerSecond;
1202 /** @} */
1203
1204 /** @name Hypercalls. */
1205 /* @{ */
1206 /** Guest address of the hypercall input parameter page. */
1207 RTGCPHYS GCPhysHypercallIn;
1208 /** Guest address of the hypercall output parameter page. */
1209 RTGCPHYS GCPhysHypercallOut;
1210 /** Pointer to the hypercall input parameter page - R3. */
1211 R3PTRTYPE(uint8_t *) pbHypercallIn;
1212 /** Pointer to the hypercall output parameter page - R3. */
1213 R3PTRTYPE(uint8_t *) pbHypercallOut;
1214 /** @} */
1215
1216 /** @name Guest debugging.
1217 * @{ */
1218 /** Whether we're posing as the Microsoft vendor. */
1219 bool fIsVendorMsHv;
1220 /** Whether we're posing as the Microsoft virtualization service. */
1221 bool fIsInterfaceVs;
1222 /** Whether debugging support is enabled. */
1223 bool fDbgEnabled;
1224 /** Whether we should suggest a hypercall-based debug interface to the guest. */
1225 bool fDbgHypercallInterface;
1226 bool afAlignment0[4];
1227 /** The action to take while sending replies. */
1228 GIMHVDEBUGREPLY enmDbgReply;
1229 /** The IP address chosen by/assigned to the guest. */
1230 RTNETADDRIPV4 DbgGuestIp4Addr;
1231 /** Transaction ID for the BOOTP+DHCP sequence. */
1232 uint32_t uDbgBootpXId;
1233 /** The source UDP port used by the guest while sending debug packets. */
1234 uint16_t uUdpGuestSrcPort;
1235 /** The destination UDP port used by the guest while sending debug packets. */
1236 uint16_t uUdpGuestDstPort;
1237 /** Debug send buffer MSR. */
1238 uint64_t uDbgSendBufferMsr;
1239 /** Debug receive buffer MSR. */
1240 uint64_t uDbgRecvBufferMsr;
1241 /** Debug pending buffer MSR. */
1242 uint64_t uDbgPendingBufferMsr;
1243 /** Debug status MSR. */
1244 uint64_t uDbgStatusMsr;
1245 /** Intermediate debug I/O buffer. */
1246 R3PTRTYPE(void *) pvDbgBuffer;
1247 R3PTRTYPE(void *) pvAlignment0;
1248 /** @} */
1249
1250 /** Array of MMIO2 regions. */
1251 GIMMMIO2REGION aMmio2Regions[GIM_HV_REGION_IDX_MAX + 1];
1252} GIMHV;
1253/** Pointer to per-VM GIM Hyper-V instance data. */
1254typedef GIMHV *PGIMHV;
1255/** Pointer to const per-VM GIM Hyper-V instance data. */
1256typedef GIMHV const *PCGIMHV;
1257AssertCompileMemberAlignment(GIMHV, aMmio2Regions, 8);
1258AssertCompileMemberAlignment(GIMHV, hSpinlockR0, sizeof(uintptr_t));
1259
1260/**
1261 * Hyper-V per-VCPU synthetic timer.
1262 */
1263typedef struct GIMHVSTIMER
1264{
1265 /** Synthetic timer object - R0 ptr. */
1266 PTMTIMERR0 pTimerR0;
1267 /** Synthetic timer object - R3 ptr. */
1268 PTMTIMERR3 pTimerR3;
1269 /** Synthetic timer object - RC ptr. */
1270 PTMTIMERRC pTimerRC;
1271 /** RC alignment padding. */
1272 RTRCPTR uAlignment0;
1273 /** Virtual CPU ID this timer belongs to (for reverse mapping). */
1274 VMCPUID idCpu;
1275 /** The index of this timer in the auStimers array (for reverse mapping). */
1276 uint32_t idxStimer;
1277 /** Synthetic timer config MSR. */
1278 uint64_t uStimerConfigMsr;
1279 /** Synthetic timer count MSR. */
1280 uint64_t uStimerCountMsr;
1281 /** Timer description. */
1282 char szTimerDesc[24];
1283
1284} GIMHVSTIMER;
1285/** Pointer to per-VCPU Hyper-V synthetic timer. */
1286typedef GIMHVSTIMER *PGIMHVSTIMER;
1287/** Pointer to a const per-VCPU Hyper-V synthetic timer. */
1288typedef GIMHVSTIMER const *PCGIMHVSTIMER;
1289AssertCompileSizeAlignment(GIMHVSTIMER, 8);
1290
1291/**
1292 * Hyper-V VCPU instance data.
1293 * Changes to this must checked against the padding of the gim union in VMCPU!
1294 */
1295typedef struct GIMHVCPU
1296{
1297 /** @name Synthetic interrupt MSRs.
1298 * @{ */
1299 /** Synthetic interrupt message page MSR. */
1300 uint64_t uSimpMsr;
1301 /** Interrupt source MSRs. */
1302 uint64_t auSintMsrs[GIM_HV_SINT_COUNT];
1303 /** Synethtic interrupt events flag page MSR. */
1304 uint64_t uSiefpMsr;
1305 /** APIC-assist page MSR. */
1306 uint64_t uApicAssistPageMsr;
1307 /** Synthetic interrupt control MSR. */
1308 uint64_t uSControlMsr;
1309 /** Synthetic timers. */
1310 GIMHVSTIMER aStimers[GIM_HV_STIMER_COUNT];
1311 /** @} */
1312
1313 /** @name Statistics.
1314 * @{ */
1315 STAMCOUNTER aStatStimerFired[GIM_HV_STIMER_COUNT];
1316 /** @} */
1317} GIMHVCPU;
1318/** Pointer to per-VCPU GIM Hyper-V instance data. */
1319typedef GIMHVCPU *PGIMHVCPU;
1320/** Pointer to const per-VCPU GIM Hyper-V instance data. */
1321typedef GIMHVCPU const *PCGIMHVCPU;
1322
1323
1324RT_C_DECLS_BEGIN
1325
1326#ifdef IN_RING0
1327VMMR0_INT_DECL(int) gimR0HvInitVM(PVM pVM);
1328VMMR0_INT_DECL(int) gimR0HvTermVM(PVM pVM);
1329VMMR0_INT_DECL(int) gimR0HvUpdateParavirtTsc(PVM pVM, uint64_t u64Offset);
1330#endif /* IN_RING0 */
1331
1332#ifdef IN_RING3
1333VMMR3_INT_DECL(int) gimR3HvInit(PVM pVM, PCFGMNODE pGimCfg);
1334VMMR3_INT_DECL(int) gimR3HvInitCompleted(PVM pVM);
1335VMMR3_INT_DECL(int) gimR3HvTerm(PVM pVM);
1336VMMR3_INT_DECL(void) gimR3HvRelocate(PVM pVM, RTGCINTPTR offDelta);
1337VMMR3_INT_DECL(void) gimR3HvReset(PVM pVM);
1338VMMR3_INT_DECL(PGIMMMIO2REGION) gimR3HvGetMmio2Regions(PVM pVM, uint32_t *pcRegions);
1339VMMR3_INT_DECL(int) gimR3HvSave(PVM pVM, PSSMHANDLE pSSM);
1340VMMR3_INT_DECL(int) gimR3HvLoad(PVM pVM, PSSMHANDLE pSSM);
1341VMMR3_INT_DECL(int) gimR3HvLoadDone(PVM pVM, PSSMHANDLE pSSM);
1342VMMR3_INT_DECL(int) gimR3HvGetDebugSetup(PVM pVM, PGIMDEBUGSETUP pDbgSetup);
1343
1344VMMR3_INT_DECL(int) gimR3HvDisableSiefPage(PVMCPU pVCpu);
1345VMMR3_INT_DECL(int) gimR3HvEnableSiefPage(PVMCPU pVCpu, RTGCPHYS GCPhysSiefPage);
1346VMMR3_INT_DECL(int) gimR3HvEnableSimPage(PVMCPU pVCpu, RTGCPHYS GCPhysSimPage);
1347VMMR3_INT_DECL(int) gimR3HvDisableSimPage(PVMCPU pVCpu);
1348VMMR3_INT_DECL(int) gimR3HvDisableApicAssistPage(PVMCPU pVCpu);
1349VMMR3_INT_DECL(int) gimR3HvEnableApicAssistPage(PVMCPU pVCpu, RTGCPHYS GCPhysTscPage);
1350VMMR3_INT_DECL(int) gimR3HvDisableTscPage(PVM pVM);
1351VMMR3_INT_DECL(int) gimR3HvEnableTscPage(PVM pVM, RTGCPHYS GCPhysTscPage, bool fUseThisTscSeq, uint32_t uTscSeq);
1352VMMR3_INT_DECL(int) gimR3HvDisableHypercallPage(PVM pVM);
1353VMMR3_INT_DECL(int) gimR3HvEnableHypercallPage(PVM pVM, RTGCPHYS GCPhysHypercallPage);
1354
1355VMMR3_INT_DECL(int) gimR3HvHypercallPostDebugData(PVM pVM, int *prcHv);
1356VMMR3_INT_DECL(int) gimR3HvHypercallRetrieveDebugData(PVM pVM, int *prcHv);
1357VMMR3_INT_DECL(int) gimR3HvDebugWrite(PVM pVM, void *pvData, uint32_t cbWrite, uint32_t *pcbWritten, bool fUdpPkt);
1358VMMR3_INT_DECL(int) gimR3HvDebugRead(PVM pVM, void *pvBuf, uint32_t cbBuf, uint32_t cbRead, uint32_t *pcbRead,
1359 uint32_t cMsTimeout, bool fUdpPkt);
1360VMMR3_INT_DECL(int) gimR3HvHypercallExtQueryCap(PVM pVM, int *prcHv);
1361VMMR3_INT_DECL(int) gimR3HvHypercallExtGetBootZeroedMem(PVM pVM, int *prcHv);
1362
1363#endif /* IN_RING3 */
1364
1365VMM_INT_DECL(bool) gimHvIsParavirtTscEnabled(PVM pVM);
1366VMM_INT_DECL(bool) gimHvAreHypercallsEnabled(PVMCPU pVCpu);
1367VMM_INT_DECL(bool) gimHvShouldTrapXcptUD(PVMCPU pVCpu);
1368VMM_INT_DECL(VBOXSTRICTRC) gimHvXcptUD(PVMCPU pVCpu, PCPUMCTX pCtx, PDISCPUSTATE pDis, uint8_t *pcbInstr);
1369VMM_INT_DECL(VBOXSTRICTRC) gimHvHypercall(PVMCPU pVCpu, PCPUMCTX pCtx);
1370VMM_INT_DECL(VBOXSTRICTRC) gimHvHypercallEx(PVMCPU pVCpu, PCPUMCTX pCtx, unsigned uDisOpcode, uint8_t cbInstr);
1371VMM_INT_DECL(VBOXSTRICTRC) gimHvReadMsr(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue);
1372VMM_INT_DECL(VBOXSTRICTRC) gimHvWriteMsr(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uRawValue);
1373
1374VMM_INT_DECL(void) gimHvStartStimer(PVMCPU pVCpu, PCGIMHVSTIMER pHvStimer);
1375
1376RT_C_DECLS_END
1377
1378#endif
1379
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