| 1 | /* $Id: GIMHvInternal.h 54701 2015-03-09 16:42:11Z vboxsync $ */
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| 2 | /** @file
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| 3 | * GIM - Hyper-V, Internal header file.
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| 4 | */
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| 5 |
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| 6 | /*
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| 7 | * Copyright (C) 2014-2015 Oracle Corporation
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| 8 | *
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| 9 | * This file is part of VirtualBox Open Source Edition (OSE), as
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| 10 | * available from http://www.virtualbox.org. This file is free software;
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| 11 | * you can redistribute it and/or modify it under the terms of the GNU
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| 12 | * General Public License (GPL) as published by the Free Software
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| 13 | * Foundation, in version 2 as it comes in the "COPYING" file of the
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| 14 | * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
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| 15 | * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
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| 16 | */
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| 17 |
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| 18 | #ifndef ___GIMHvInternal_h
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| 19 | #define ___GIMHvInternal_h
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| 20 |
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| 21 | #include <VBox/vmm/gim.h>
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| 22 | #include <VBox/vmm/cpum.h>
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| 23 |
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| 24 |
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| 25 | /** @name Hyper-V base feature identification.
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| 26 | * Features based on current partition privileges (per-VM).
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| 27 | * @{
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| 28 | */
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| 29 | /** Virtual processor runtime MSR available. */
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| 30 | #define GIM_HV_BASE_FEAT_VP_RUNTIME_MSR RT_BIT(0)
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| 31 | /** Partition reference counter MSR available. */
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| 32 | #define GIM_HV_BASE_FEAT_PART_TIME_REF_COUNT_MSR RT_BIT(1)
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| 33 | /** Basic Synthetic Interrupt Controller MSRs available. */
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| 34 | #define GIM_HV_BASE_FEAT_BASIC_SYNTH_IC RT_BIT(2)
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| 35 | /** Synthetic Timer MSRs available. */
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| 36 | #define GIM_HV_BASE_FEAT_SYNTH_TIMER_MSRS RT_BIT(3)
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| 37 | /** APIC access MSRs (EOI, ICR, TPR) available. */
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| 38 | #define GIM_HV_BASE_FEAT_APIC_ACCESS_MSRS RT_BIT(4)
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| 39 | /** Hypercall MSRs available. */
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| 40 | #define GIM_HV_BASE_FEAT_HYPERCALL_MSRS RT_BIT(5)
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| 41 | /** Access to VCPU index MSR available. */
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| 42 | #define GIM_HV_BASE_FEAT_VP_ID_MSR RT_BIT(6)
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| 43 | /** Virtual system reset MSR available. */
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| 44 | #define GIM_HV_BASE_FEAT_VIRT_SYS_RESET_MSR RT_BIT(7)
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| 45 | /** Statistic pages MSRs available. */
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| 46 | #define GIM_HV_BASE_FEAT_STAT_PAGES_MSR RT_BIT(8)
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| 47 | /** Paritition reference TSC MSR available. */
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| 48 | #define GIM_HV_BASE_FEAT_PART_REF_TSC_MSR RT_BIT(9)
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| 49 | /** Virtual guest idle state MSR available. */
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| 50 | #define GIM_HV_BASE_FEAT_GUEST_IDLE_STATE_MSR RT_BIT(10)
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| 51 | /** Timer frequency MSRs (TSC and APIC) available. */
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| 52 | #define GIM_HV_BASE_FEAT_TIMER_FREQ_MSRS RT_BIT(11)
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| 53 | /** Debug MSRs available. */
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| 54 | #define GIM_HV_BASE_FEAT_DEBUG_MSRS RT_BIT(12)
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| 55 | /** @} */
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| 56 |
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| 57 | /** @name Hyper-V partition-creation feature identification.
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| 58 | * Indicates flags specified during partition creation.
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| 59 | * @{
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| 60 | */
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| 61 | /** Create partitions. */
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| 62 | #define GIM_HV_PART_FLAGS_CREATE_PART RT_BIT(0)
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| 63 | /** Access partition Id. */
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| 64 | #define GIM_HV_PART_FLAGS_ACCESS_PART_ID RT_BIT(1)
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| 65 | /** Access memory pool. */
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| 66 | #define GIM_HV_PART_FLAGS_ACCESS_MEMORY_POOL RT_BIT(2)
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| 67 | /** Adjust message buffers. */
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| 68 | #define GIM_HV_PART_FLAGS_ADJUST_MSG_BUFFERS RT_BIT(3)
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| 69 | /** Post messages. */
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| 70 | #define GIM_HV_PART_FLAGS_POST_MSGS RT_BIT(4)
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| 71 | /** Signal events. */
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| 72 | #define GIM_HV_PART_FLAGS_SIGNAL_EVENTS RT_BIT(5)
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| 73 | /** Create port. */
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| 74 | #define GIM_HV_PART_FLAGS_CREATE_PORT RT_BIT(6)
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| 75 | /** Connect port. */
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| 76 | #define GIM_HV_PART_FLAGS_CONNECT_PORT RT_BIT(7)
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| 77 | /** Access statistics. */
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| 78 | #define GIM_HV_PART_FLAGS_ACCESS_STATS RT_BIT(8)
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| 79 | /** Debugging.*/
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| 80 | #define GIM_HV_PART_FLAGS_DEBUGGING RT_BIT(11)
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| 81 | /** CPU management. */
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| 82 | #define GIM_HV_PART_FLAGS_CPU_MGMT RT_BIT(12)
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| 83 | /** CPU profiler. */
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| 84 | #define GIM_HV_PART_FLAGS_CPU_PROFILER RT_BIT(13)
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| 85 | /** Enable expanded stack walking. */
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| 86 | #define GIM_HV_PART_FLAGS_EXPANDED_STACK_WALK RT_BIT(14)
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| 87 | /** @} */
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| 88 |
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| 89 | /** @name Hyper-V power management feature identification.
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| 90 | * @{
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| 91 | */
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| 92 | /** Maximum CPU power state C0. */
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| 93 | #define GIM_HV_PM_MAX_CPU_POWER_STATE_C0 RT_BIT(0)
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| 94 | /** Maximum CPU power state C1. */
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| 95 | #define GIM_HV_PM_MAX_CPU_POWER_STATE_C1 RT_BIT(1)
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| 96 | /** Maximum CPU power state C2. */
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| 97 | #define GIM_HV_PM_MAX_CPU_POWER_STATE_C2 RT_BIT(2)
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| 98 | /** Maximum CPU power state C3. */
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| 99 | #define GIM_HV_PM_MAX_CPU_POWER_STATE_C3 RT_BIT(3)
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| 100 | /** HPET is required to enter C3 power state. */
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| 101 | #define GIM_HV_PM_HPET_REQD_FOR_C3 RT_BIT(4)
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| 102 | /** @} */
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| 103 |
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| 104 | /** @name Hyper-V miscellaneous feature identification.
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| 105 | * Miscellaneous features available for the current partition.
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| 106 | * @{
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| 107 | */
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| 108 | /** MWAIT instruction available. */
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| 109 | #define GIM_HV_MISC_FEAT_MWAIT RT_BIT(0)
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| 110 | /** Guest debugging support available. */
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| 111 | #define GIM_HV_MISC_FEAT_GUEST_DEBUGGING RT_BIT(1)
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| 112 | /** Performance monitor support is available. */
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| 113 | #define GIM_HV_MISC_FEAT_PERF_MON RT_BIT(2)
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| 114 | /** Support for physical CPU dynamic partitioning events. */
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| 115 | #define GIM_HV_MISC_FEAT_PCPU_DYN_PART_EVENT RT_BIT(3)
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| 116 | /** Support for passing hypercall input parameter block via XMM registers. */
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| 117 | #define GIM_HV_MISC_FEAT_XMM_HYPERCALL_INPUT RT_BIT(4)
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| 118 | /** Support for virtual guest idle state. */
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| 119 | #define GIM_HV_MISC_FEAT_GUEST_IDLE_STATE RT_BIT(5)
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| 120 | /** Support for hypervisor sleep state. */
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| 121 | #define GIM_HV_MISC_FEAT_HYPERVISOR_SLEEP_STATE RT_BIT(6)
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| 122 | /** Support for querying NUMA distances. */
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| 123 | #define GIM_HV_MISC_FEAT_QUERY_NUMA_DISTANCE RT_BIT(7)
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| 124 | /** Support for determining timer frequencies. */
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| 125 | #define GIM_HV_MISC_FEAT_TIMER_FREQ RT_BIT(8)
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| 126 | /** Support for injecting synthetic machine checks. */
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| 127 | #define GIM_HV_MISC_FEAT_INJECT_SYNTH_MC_XCPT RT_BIT(9)
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| 128 | /** Support for guest crash MSRs. */
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| 129 | #define GIM_HV_MISC_FEAT_GUEST_CRASH_MSRS RT_BIT(10)
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| 130 | /** Support for debug MSRs. */
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| 131 | #define GIM_HV_MISC_FEAT_DEBUG_MSRS RT_BIT(11)
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| 132 | /** Npiep1 Available */ /** @todo What the heck is this? */
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| 133 | #define GIM_HV_MISC_FEAT_NPIEP1 RT_BIT(12)
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| 134 | /** Disable hypervisor available. */
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| 135 | #define GIM_HV_MISC_FEAT_DISABLE_HYPERVISOR RT_BIT(13)
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| 136 | /** @} */
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| 137 |
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| 138 | /** @name Hyper-V implementation recommendations.
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| 139 | * Recommendations from the hypervisor for the guest for optimal performance.
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| 140 | * @{
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| 141 | */
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| 142 | /** Use hypercall for address space switches rather than MOV CR3. */
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| 143 | #define GIM_HV_HINT_HYPERCALL_FOR_PROCESS_SWITCH RT_BIT(0)
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| 144 | /** Use hypercall for local TLB flushes rather than INVLPG/MOV CR3. */
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| 145 | #define GIM_HV_HINT_HYPERCALL_FOR_TLB_FLUSH RT_BIT(1)
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| 146 | /** Use hypercall for inter-CPU TLB flushes rather than IPIs. */
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| 147 | #define GIM_HV_HINT_HYPERCALL_FOR_TLB_SHOOTDOWN RT_BIT(2)
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| 148 | /** Use MSRs for APIC access (EOI, ICR, TPR) rather than MMIO. */
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| 149 | #define GIM_HV_HINT_MSR_FOR_APIC_ACCESS RT_BIT(3)
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| 150 | /** Use hypervisor provided MSR for a system reset. */
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| 151 | #define GIM_HV_HINT_MSR_FOR_SYS_RESET RT_BIT(4)
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| 152 | /** Relax timer-related checks (watchdogs/deadman timeouts) that rely on
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| 153 | * timely deliver of external interrupts. */
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| 154 | #define GIM_HV_HINT_RELAX_TIME_CHECKS RT_BIT(5)
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| 155 | /** Use DMA remapping. */
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| 156 | #define GIM_HV_HINT_DMA_REMAPPING RT_BIT(6)
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| 157 | /** Use interrupt remapping. */
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| 158 | #define GIM_HV_HINT_INTERRUPT_REMAPPING RT_BIT(7)
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| 159 | /** Use X2APIC MSRs rather than MMIO. */
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| 160 | #define GIM_HV_HINT_X2APIC_MSRS RT_BIT(8)
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| 161 | /** Deprecate Auto EOI (end of interrupt). */
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| 162 | #define GIM_HV_HINT_DEPRECATE_AUTO_EOI RT_BIT(9)
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| 163 | /** @} */
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| 164 |
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| 165 |
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| 166 | /** @name Hyper-V implementation hardware features.
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| 167 | * Which hardware features are in use by the hypervisor.
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| 168 | * @{
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| 169 | */
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| 170 | /** APIC overlay is used. */
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| 171 | #define GIM_HV_HOST_FEAT_AVIC RT_BIT(0)
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| 172 | /** MSR bitmaps is used. */
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| 173 | #define GIM_HV_HOST_FEAT_MSR_BITMAP RT_BIT(1)
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| 174 | /** Architectural performance counter supported. */
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| 175 | #define GIM_HV_HOST_FEAT_PERF_COUNTER RT_BIT(2)
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| 176 | /** Nested paging is used. */
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| 177 | #define GIM_HV_HOST_FEAT_NESTED_PAGING RT_BIT(3)
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| 178 | /** DMA remapping is used. */
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| 179 | #define GIM_HV_HOST_FEAT_DMA_REMAPPING RT_BIT(4)
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| 180 | /** Interrupt remapping is used. */
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| 181 | #define GIM_HV_HOST_FEAT_INTERRUPT_REMAPPING RT_BIT(5)
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| 182 | /** Memory patrol scrubber is present. */
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| 183 | #define GIM_HV_HOST_FEAT_MEM_PATROL_SCRUBBER RT_BIT(6)
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| 184 | /** @} */
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| 185 |
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| 186 |
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| 187 | /** @name Hyper-V MSRs.
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| 188 | * @{
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| 189 | */
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| 190 | /** Start of range 0. */
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| 191 | #define MSR_GIM_HV_RANGE0_START UINT32_C(0x40000000)
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| 192 | /** Guest OS identification (R/W) */
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| 193 | #define MSR_GIM_HV_GUEST_OS_ID UINT32_C(0x40000000)
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| 194 | /** Enable hypercall interface (R/W) */
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| 195 | #define MSR_GIM_HV_HYPERCALL UINT32_C(0x40000001)
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| 196 | /** Virtual processor's (VCPU) index (R) */
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| 197 | #define MSR_GIM_HV_VP_INDEX UINT32_C(0x40000002)
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| 198 | /** Reset operation (R/W) */
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| 199 | #define MSR_GIM_HV_RESET UINT32_C(0x40000003)
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| 200 | /** End of range 0. */
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| 201 | #define MSR_GIM_HV_RANGE0_END MSR_GIM_HV_RESET
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| 202 |
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| 203 | /** Start of range 1. */
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| 204 | #define MSR_GIM_HV_RANGE1_START UINT32_C(0x40000010)
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| 205 | /** Virtual processor's (VCPU) runtime (R) */
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| 206 | #define MSR_GIM_HV_VP_RUNTIME UINT32_C(0x40000010)
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| 207 | /** End of range 1. */
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| 208 | #define MSR_GIM_HV_RANGE1_END MSR_GIM_HV_VP_RUNTIME
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| 209 |
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| 210 | /** Start of range 2. */
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| 211 | #define MSR_GIM_HV_RANGE2_START UINT32_C(0x40000020)
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| 212 | /** Per-VM reference counter (R) */
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| 213 | #define MSR_GIM_HV_TIME_REF_COUNT UINT32_C(0x40000020)
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| 214 | /** Per-VM TSC page (R/W) */
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| 215 | #define MSR_GIM_HV_REF_TSC UINT32_C(0x40000021)
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| 216 | /** Frequency of TSC in Hz as reported by the hypervisor (R) */
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| 217 | #define MSR_GIM_HV_TSC_FREQ UINT32_C(0x40000022)
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| 218 | /** Frequency of LAPIC in Hz as reported by the hypervisor (R) */
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| 219 | #define MSR_GIM_HV_APIC_FREQ UINT32_C(0x40000023)
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| 220 | /** End of range 2. */
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| 221 | #define MSR_GIM_HV_RANGE2_END MSR_GIM_HV_APIC_FREQ
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| 222 |
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| 223 | /** Start of range 3. */
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| 224 | #define MSR_GIM_HV_RANGE3_START UINT32_C(0x40000070)
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| 225 | /** Access to APIC EOI (End-Of-Interrupt) register (W) */
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| 226 | #define MSR_GIM_HV_EOI UINT32_C(0x40000070)
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| 227 | /** Access to APIC ICR (Interrupt Command) register (R/W) */
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| 228 | #define MSR_GIM_HV_ICR UINT32_C(0x40000071)
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| 229 | /** Access to APIC TPR (Task Priority) register (R/W) */
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| 230 | #define MSR_GIM_HV_TPR UINT32_C(0x40000072)
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| 231 | /** Enables lazy EOI processing (R/W) */
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| 232 | #define MSR_GIM_HV_APIC_ASSIST_PAGE UINT32_C(0x40000073)
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| 233 | /** End of range 3. */
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| 234 | #define MSR_GIM_HV_RANGE3_END MSR_GIM_HV_APIC_ASSIST_PAGE
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| 235 |
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| 236 | /** Start of range 4. */
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| 237 | #define MSR_GIM_HV_RANGE4_START UINT32_C(0x40000080)
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| 238 | /** Control behaviour of synthetic interrupt controller (R/W) */
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| 239 | #define MSR_GIM_HV_SCONTROL UINT32_C(0x40000080)
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| 240 | /** Synthetic interrupt controller version (R) */
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| 241 | #define MSR_GIM_HV_SVERSION UINT32_C(0x40000081)
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| 242 | /** Base address of synthetic interrupt event flag (R/W) */
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| 243 | #define MSR_GIM_HV_SIEFP UINT32_C(0x40000082)
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| 244 | /** Base address of synthetic interrupt parameter page (R/W) */
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| 245 | #define MSR_GIM_HV_SIMP UINT32_C(0x40000083)
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| 246 | /** End-Of-Message in synthetic interrupt parameter page (W) */
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| 247 | #define MSR_GIM_HV_EOM UINT32_C(0x40000084)
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| 248 | /** End of range 4. */
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| 249 | #define MSR_GIM_HV_RANGE4_END MSR_GIM_HV_EOM
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| 250 |
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| 251 | /** Start of range 5. */
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| 252 | #define MSR_GIM_HV_RANGE5_START UINT32_C(0x40000090)
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| 253 | /** Configures synthetic interrupt source 0 (R/W) */
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| 254 | #define MSR_GIM_HV_SINT0 UINT32_C(0x40000090)
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| 255 | /** Configures synthetic interrupt source 1 (R/W) */
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| 256 | #define MSR_GIM_HV_SINT1 UINT32_C(0x40000091)
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| 257 | /** Configures synthetic interrupt source 2 (R/W) */
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| 258 | #define MSR_GIM_HV_SINT2 UINT32_C(0x40000092)
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| 259 | /** Configures synthetic interrupt source 3 (R/W) */
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| 260 | #define MSR_GIM_HV_SINT3 UINT32_C(0x40000093)
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| 261 | /** Configures synthetic interrupt source 4 (R/W) */
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| 262 | #define MSR_GIM_HV_SINT4 UINT32_C(0x40000094)
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| 263 | /** Configures synthetic interrupt source 5 (R/W) */
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| 264 | #define MSR_GIM_HV_SINT5 UINT32_C(0x40000095)
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| 265 | /** Configures synthetic interrupt source 6 (R/W) */
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| 266 | #define MSR_GIM_HV_SINT6 UINT32_C(0x40000096)
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| 267 | /** Configures synthetic interrupt source 7 (R/W) */
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| 268 | #define MSR_GIM_HV_SINT7 UINT32_C(0x40000097)
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| 269 | /** Configures synthetic interrupt source 8 (R/W) */
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| 270 | #define MSR_GIM_HV_SINT8 UINT32_C(0x40000098)
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| 271 | /** Configures synthetic interrupt source 9 (R/W) */
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| 272 | #define MSR_GIM_HV_SINT9 UINT32_C(0x40000099)
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| 273 | /** Configures synthetic interrupt source 10 (R/W) */
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| 274 | #define MSR_GIM_HV_SINT10 UINT32_C(0x4000009A)
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| 275 | /** Configures synthetic interrupt source 11 (R/W) */
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| 276 | #define MSR_GIM_HV_SINT11 UINT32_C(0x4000009B)
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| 277 | /** Configures synthetic interrupt source 12 (R/W) */
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| 278 | #define MSR_GIM_HV_SINT12 UINT32_C(0x4000009C)
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| 279 | /** Configures synthetic interrupt source 13 (R/W) */
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| 280 | #define MSR_GIM_HV_SINT13 UINT32_C(0x4000009D)
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| 281 | /** Configures synthetic interrupt source 14 (R/W) */
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| 282 | #define MSR_GIM_HV_SINT14 UINT32_C(0x4000009E)
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| 283 | /** Configures synthetic interrupt source 15 (R/W) */
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| 284 | #define MSR_GIM_HV_SINT15 UINT32_C(0x4000009F)
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| 285 | /** End of range 5. */
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| 286 | #define MSR_GIM_HV_RANGE5_END MSR_GIM_HV_SINT15
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| 287 |
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| 288 | /** Start of range 6. */
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| 289 | #define MSR_GIM_HV_RANGE6_START UINT32_C(0x400000B0)
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| 290 | /** Configures register for synthetic timer 0 (R/W) */
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| 291 | #define MSR_GIM_HV_STIMER0_CONFIG UINT32_C(0x400000B0)
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| 292 | /** Expiration time or period for synthetic timer 0 (R/W) */
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| 293 | #define MSR_GIM_HV_STIMER0_COUNT UINT32_C(0x400000B1)
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| 294 | /** Configures register for synthetic timer 1 (R/W) */
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| 295 | #define MSR_GIM_HV_STIMER1_CONFIG UINT32_C(0x400000B2)
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| 296 | /** Expiration time or period for synthetic timer 1 (R/W) */
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| 297 | #define MSR_GIM_HV_STIMER1_COUNT UINT32_C(0x400000B3)
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| 298 | /** Configures register for synthetic timer 2 (R/W) */
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| 299 | #define MSR_GIM_HV_STIMER2_CONFIG UINT32_C(0x400000B4)
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| 300 | /** Expiration time or period for synthetic timer 2 (R/W) */
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| 301 | #define MSR_GIM_HV_STIMER2_COUNT UINT32_C(0x400000B5)
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| 302 | /** Configures register for synthetic timer 3 (R/W) */
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| 303 | #define MSR_GIM_HV_STIMER3_CONFIG UINT32_C(0x400000B6)
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| 304 | /** Expiration time or period for synthetic timer 3 (R/W) */
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| 305 | #define MSR_GIM_HV_STIMER3_COUNT UINT32_C(0x400000B7)
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| 306 | /** End of range 6. */
|
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| 307 | #define MSR_GIM_HV_RANGE6_END MSR_GIM_HV_STIMER3_COUNT
|
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| 308 |
|
|---|
| 309 | /** Start of range 7. */
|
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| 310 | #define MSR_GIM_HV_RANGE7_START UINT32_C(0x400000C1)
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| 311 | /** Trigger to transition to power state C1 (R) */
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| 312 | #define MSR_GIM_HV_POWER_STATE_TRIGGER_C1 UINT32_C(0x400000C1)
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| 313 | /** Trigger to transition to power state C2 (R) */
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| 314 | #define MSR_GIM_HV_POWER_STATE_TRIGGER_C2 UINT32_C(0x400000C2)
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| 315 | /** Trigger to transition to power state C3 (R) */
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| 316 | #define MSR_GIM_HV_POWER_STATE_TRIGGER_C3 UINT32_C(0x400000C3)
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| 317 | /** End of range 7. */
|
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| 318 | #define MSR_GIM_HV_RANGE7_END MSR_GIM_HV_POWER_STATE_TRIGGER_C3
|
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| 319 |
|
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| 320 | /** Start of range 8. */
|
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| 321 | #define MSR_GIM_HV_RANGE8_START UINT32_C(0x400000D1)
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| 322 | /** Configure the recipe for power state transitions to C1 (R/W) */
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| 323 | #define MSR_GIM_HV_POWER_STATE_CONFIG_C1 UINT32_C(0x400000D1)
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| 324 | /** Configure the recipe for power state transitions to C2 (R/W) */
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| 325 | #define MSR_GIM_HV_POWER_STATE_CONFIG_C2 UINT32_C(0x400000D2)
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| 326 | /** Configure the recipe for power state transitions to C3 (R/W) */
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| 327 | #define MSR_GIM_HV_POWER_STATE_CONFIG_C3 UINT32_C(0x400000D3)
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| 328 | /** End of range 8. */
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| 329 | #define MSR_GIM_HV_RANGE8_END MSR_GIM_HV_POWER_STATE_CONFIG_C3
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| 330 |
|
|---|
| 331 | /** Start of range 9. */
|
|---|
| 332 | #define MSR_GIM_HV_RANGE9_START UINT32_C(0x400000E0)
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| 333 | /** Map the guest's retail partition stats page (R/W) */
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| 334 | #define MSR_GIM_HV_STATS_PART_RETAIL_PAGE UINT32_C(0x400000E0)
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| 335 | /** Map the guest's internal partition stats page (R/W) */
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| 336 | #define MSR_GIM_HV_STATS_PART_INTERNAL_PAGE UINT32_C(0x400000E1)
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|---|
| 337 | /** Map the guest's retail VP stats page (R/W) */
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|---|
| 338 | #define MSR_GIM_HV_STATS_VP_RETAIL_PAGE UINT32_C(0x400000E2)
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|---|
| 339 | /** Map the guest's internal VP stats page (R/W) */
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|---|
| 340 | #define MSR_GIM_HV_STATS_VP_INTERNAL_PAGE UINT32_C(0x400000E3)
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|---|
| 341 | /** End of range 9. */
|
|---|
| 342 | #define MSR_GIM_HV_RANGE9_END MSR_GIM_HV_STATS_VP_INTERNAL_PAGE
|
|---|
| 343 |
|
|---|
| 344 | /** Start of range 10. */
|
|---|
| 345 | #define MSR_GIM_HV_RANGE10_START UINT32_C(0x400000F0)
|
|---|
| 346 | /** Trigger the guest's transition to idle power state (R) */
|
|---|
| 347 | #define MSR_GIM_HV_GUEST_IDLE UINT32_C(0x400000F0)
|
|---|
| 348 | /** Synthetic debug control. */
|
|---|
| 349 | #define MSR_GIM_HV_SYNTH_DEBUG_CONTROL UINT32_C(0x400000F1)
|
|---|
| 350 | /** Synthetic debug status. */
|
|---|
| 351 | #define MSR_GIM_HV_SYNTH_DEBUG_STATUS UINT32_C(0x400000F2)
|
|---|
| 352 | /** Synthetic debug send buffer. */
|
|---|
| 353 | #define MSR_GIM_HV_SYNTH_DEBUG_SEND_BUFFER UINT32_C(0x400000F3)
|
|---|
| 354 | /** Synthetic debug receive buffer. */
|
|---|
| 355 | #define MSR_GIM_HV_SYNTH_DEBUG_RECEIVE_BUFFER UINT32_C(0x400000F4)
|
|---|
| 356 | /** Synthetic debug pending buffer. */
|
|---|
| 357 | #define MSR_GIM_HV_SYNTH_DEBUG_PENDING_BUFFER UINT32_C(0x400000F5)
|
|---|
| 358 | /** End of range 10. */
|
|---|
| 359 | #define MSR_GIM_HV_RANGE10_END MSR_GIM_HV_SYNTH_DEBUG_PENDING_BUFFER
|
|---|
| 360 |
|
|---|
| 361 | /** Start of range 11. */
|
|---|
| 362 | #define MSR_GIM_HV_RANGE11_START UINT32_C(0x40000100)
|
|---|
| 363 | /** Guest crash MSR 0. */
|
|---|
| 364 | #define MSR_GIM_HV_CRASH_P0 UINT32_C(0x40000100)
|
|---|
| 365 | /** Guest crash MSR 1. */
|
|---|
| 366 | #define MSR_GIM_HV_CRASH_P1 UINT32_C(0x40000101)
|
|---|
| 367 | /** Guest crash MSR 2. */
|
|---|
| 368 | #define MSR_GIM_HV_CRASH_P2 UINT32_C(0x40000102)
|
|---|
| 369 | /** Guest crash MSR 3. */
|
|---|
| 370 | #define MSR_GIM_HV_CRASH_P3 UINT32_C(0x40000103)
|
|---|
| 371 | /** Guest crash MSR 4. */
|
|---|
| 372 | #define MSR_GIM_HV_CRASH_P4 UINT32_C(0x40000104)
|
|---|
| 373 | /** Guest crash control. */
|
|---|
| 374 | #define MSR_GIM_HV_CRASH_CTL UINT32_C(0x40000105)
|
|---|
| 375 | /** End of range 11. */
|
|---|
| 376 | #define MSR_GIM_HV_RANGE11_END MSR_GIM_HV_CRASH_CTL
|
|---|
| 377 | /** @} */
|
|---|
| 378 |
|
|---|
| 379 | AssertCompile(MSR_GIM_HV_RANGE0_START <= MSR_GIM_HV_RANGE0_END);
|
|---|
| 380 | AssertCompile(MSR_GIM_HV_RANGE1_START <= MSR_GIM_HV_RANGE1_END);
|
|---|
| 381 | AssertCompile(MSR_GIM_HV_RANGE2_START <= MSR_GIM_HV_RANGE2_END);
|
|---|
| 382 | AssertCompile(MSR_GIM_HV_RANGE3_START <= MSR_GIM_HV_RANGE3_END);
|
|---|
| 383 | AssertCompile(MSR_GIM_HV_RANGE4_START <= MSR_GIM_HV_RANGE4_END);
|
|---|
| 384 | AssertCompile(MSR_GIM_HV_RANGE5_START <= MSR_GIM_HV_RANGE5_END);
|
|---|
| 385 | AssertCompile(MSR_GIM_HV_RANGE6_START <= MSR_GIM_HV_RANGE6_END);
|
|---|
| 386 | AssertCompile(MSR_GIM_HV_RANGE7_START <= MSR_GIM_HV_RANGE7_END);
|
|---|
| 387 | AssertCompile(MSR_GIM_HV_RANGE8_START <= MSR_GIM_HV_RANGE8_END);
|
|---|
| 388 | AssertCompile(MSR_GIM_HV_RANGE9_START <= MSR_GIM_HV_RANGE9_END);
|
|---|
| 389 | AssertCompile(MSR_GIM_HV_RANGE10_START <= MSR_GIM_HV_RANGE10_END);
|
|---|
| 390 | AssertCompile(MSR_GIM_HV_RANGE11_START <= MSR_GIM_HV_RANGE11_END);
|
|---|
| 391 |
|
|---|
| 392 | /** @name Hyper-V MSR - Reset (MSR_GIM_HV_RESET).
|
|---|
| 393 | * @{
|
|---|
| 394 | */
|
|---|
| 395 | /** The hypercall enable bit. */
|
|---|
| 396 | #define MSR_GIM_HV_RESET_BIT RT_BIT_64(0)
|
|---|
| 397 | /** Whether the hypercall-page is enabled or not. */
|
|---|
| 398 | #define MSR_GIM_HV_RESET_IS_SET(a) RT_BOOL((a) & MSR_GIM_HV_RESET_BIT)
|
|---|
| 399 | /** @} */
|
|---|
| 400 |
|
|---|
| 401 | /** @name Hyper-V MSR - Hypercall (MSR_GIM_HV_HYPERCALL).
|
|---|
| 402 | * @{
|
|---|
| 403 | */
|
|---|
| 404 | /** Guest-physical page frame number of the hypercall-page. */
|
|---|
| 405 | #define MSR_GIM_HV_HYPERCALL_GUEST_PFN(a) ((a) >> 12)
|
|---|
| 406 | /** The hypercall enable bit. */
|
|---|
| 407 | #define MSR_GIM_HV_HYPERCALL_ENABLE_BIT RT_BIT_64(0)
|
|---|
| 408 | /** Whether the hypercall-page is enabled or not. */
|
|---|
| 409 | #define MSR_GIM_HV_HYPERCALL_IS_ENABLED(a) RT_BOOL((a) & MSR_GIM_HV_HYPERCALL_ENABLE_BIT)
|
|---|
| 410 | /** @} */
|
|---|
| 411 |
|
|---|
| 412 | /** @name Hyper-V MSR - Reference TSC (MSR_GIM_HV_REF_TSC).
|
|---|
| 413 | * @{
|
|---|
| 414 | */
|
|---|
| 415 | /** Guest-physical page frame number of the TSC-page. */
|
|---|
| 416 | #define MSR_GIM_HV_REF_TSC_GUEST_PFN(a) ((a) >> 12)
|
|---|
| 417 | /** The TSC-page enable bit. */
|
|---|
| 418 | #define MSR_GIM_HV_REF_TSC_ENABLE_BIT RT_BIT_64(0)
|
|---|
| 419 | /** Whether the TSC-page is enabled or not. */
|
|---|
| 420 | #define MSR_GIM_HV_REF_TSC_IS_ENABLED(a) RT_BOOL((a) & MSR_GIM_HV_REF_TSC_ENABLE_BIT)
|
|---|
| 421 | /** @} */
|
|---|
| 422 |
|
|---|
| 423 | /** Hyper-V page size. */
|
|---|
| 424 | #define GIM_HV_PAGE_SIZE 0x1000
|
|---|
| 425 |
|
|---|
| 426 | /**
|
|---|
| 427 | * MMIO2 region indices.
|
|---|
| 428 | */
|
|---|
| 429 | /** The hypercall page region. */
|
|---|
| 430 | #define GIM_HV_HYPERCALL_PAGE_REGION_IDX UINT8_C(0)
|
|---|
| 431 | /** The TSC page region. */
|
|---|
| 432 | #define GIM_HV_REF_TSC_PAGE_REGION_IDX UINT8_C(1)
|
|---|
| 433 | /** The maximum region index (must be <= UINT8_MAX). */
|
|---|
| 434 | #define GIM_HV_REGION_IDX_MAX GIM_HV_REF_TSC_PAGE_REGION_IDX
|
|---|
| 435 |
|
|---|
| 436 | /**
|
|---|
| 437 | * Hyper-V TSC (HV_REFERENCE_TSC_PAGE) structure placed in the TSC reference
|
|---|
| 438 | * page.
|
|---|
| 439 | */
|
|---|
| 440 | typedef struct GIMHVREFTSC
|
|---|
| 441 | {
|
|---|
| 442 | uint32_t u32TscSequence;
|
|---|
| 443 | uint32_t uReserved0;
|
|---|
| 444 | uint64_t u64TscScale;
|
|---|
| 445 | int64_t i64TscOffset;
|
|---|
| 446 | } GIMHVTSCPAGE;
|
|---|
| 447 | /** Pointer to Hyper-V reference TSC. */
|
|---|
| 448 | typedef GIMHVREFTSC *PGIMHVREFTSC;
|
|---|
| 449 | /** Pointer to a const Hyper-V reference TSC. */
|
|---|
| 450 | typedef GIMHVREFTSC const *PCGIMHVREFTSC;
|
|---|
| 451 |
|
|---|
| 452 |
|
|---|
| 453 | /**
|
|---|
| 454 | * GIM Hyper-V VM instance data.
|
|---|
| 455 | * Changes to this must checked against the padding of the gim union in VM!
|
|---|
| 456 | */
|
|---|
| 457 | typedef struct GIMHV
|
|---|
| 458 | {
|
|---|
| 459 | /** @name MSRs.
|
|---|
| 460 | * { */
|
|---|
| 461 | /** Guest OS identity MSR. */
|
|---|
| 462 | uint64_t u64GuestOsIdMsr;
|
|---|
| 463 | /** Hypercall MSR. */
|
|---|
| 464 | uint64_t u64HypercallMsr;
|
|---|
| 465 | /** Reference TSC page MSR. */
|
|---|
| 466 | uint64_t u64TscPageMsr;
|
|---|
| 467 | /** @} */
|
|---|
| 468 |
|
|---|
| 469 | /** @name CPUID features.
|
|---|
| 470 | * { */
|
|---|
| 471 | /** Basic features. */
|
|---|
| 472 | uint32_t uBaseFeat;
|
|---|
| 473 | /** Partition flags. */
|
|---|
| 474 | uint32_t uPartFlags;
|
|---|
| 475 | /** Power management. */
|
|---|
| 476 | uint32_t uPowMgmtFeat;
|
|---|
| 477 | /** Miscellaneous. */
|
|---|
| 478 | uint32_t uMiscFeat;
|
|---|
| 479 | /** Hypervisor hints to the guest. */
|
|---|
| 480 | uint32_t uHyperHints;
|
|---|
| 481 | /** Hypervisor capabilities. */
|
|---|
| 482 | uint32_t uHyperCaps;
|
|---|
| 483 | /** @} */
|
|---|
| 484 |
|
|---|
| 485 | /** Per-VM R0 Spinlock for protecting EMT writes to the TSC page. */
|
|---|
| 486 | RTSPINLOCK hSpinlockR0;
|
|---|
| 487 | #if HC_ARCH_BITS == 32
|
|---|
| 488 | uint32_t u32Alignment1;
|
|---|
| 489 | #endif
|
|---|
| 490 |
|
|---|
| 491 | /** Array of MMIO2 regions. */
|
|---|
| 492 | GIMMMIO2REGION aMmio2Regions[GIM_HV_REGION_IDX_MAX + 1];
|
|---|
| 493 | } GIMHV;
|
|---|
| 494 | /** Pointer to per-VM GIM Hyper-V instance data. */
|
|---|
| 495 | typedef GIMHV *PGIMHV;
|
|---|
| 496 | /** Pointer to const per-VM GIM Hyper-V instance data. */
|
|---|
| 497 | typedef GIMHV const *PCGIMHV;
|
|---|
| 498 | AssertCompileMemberAlignment(GIMHV, aMmio2Regions, 8);
|
|---|
| 499 | AssertCompileMemberAlignment(GIMHV, hSpinlockR0, sizeof(uintptr_t));
|
|---|
| 500 |
|
|---|
| 501 | RT_C_DECLS_BEGIN
|
|---|
| 502 |
|
|---|
| 503 | #ifdef IN_RING0
|
|---|
| 504 | VMMR0_INT_DECL(int) gimR0HvInitVM(PVM pVM);
|
|---|
| 505 | VMMR0_INT_DECL(int) gimR0HvTermVM(PVM pVM);
|
|---|
| 506 | VMMR0_INT_DECL(int) gimR0HvUpdateParavirtTsc(PVM pVM, uint64_t u64Offset);
|
|---|
| 507 | #endif /* IN_RING0 */
|
|---|
| 508 |
|
|---|
| 509 | #ifdef IN_RING3
|
|---|
| 510 | VMMR3_INT_DECL(int) gimR3HvInit(PVM pVM);
|
|---|
| 511 | VMMR3_INT_DECL(int) gimR3HvInitCompleted(PVM pVM);
|
|---|
| 512 | VMMR3_INT_DECL(int) gimR3HvTerm(PVM pVM);
|
|---|
| 513 | VMMR3_INT_DECL(void) gimR3HvRelocate(PVM pVM, RTGCINTPTR offDelta);
|
|---|
| 514 | VMMR3_INT_DECL(void) gimR3HvReset(PVM pVM);
|
|---|
| 515 | VMMR3_INT_DECL(PGIMMMIO2REGION) gimR3HvGetMmio2Regions(PVM pVM, uint32_t *pcRegions);
|
|---|
| 516 | VMMR3_INT_DECL(int) gimR3HvSave(PVM pVM, PSSMHANDLE pSSM);
|
|---|
| 517 | VMMR3_INT_DECL(int) gimR3HvLoad(PVM pVM, PSSMHANDLE pSSM, uint32_t uSSMVersion);
|
|---|
| 518 |
|
|---|
| 519 | VMMR3_INT_DECL(int) gimR3HvDisableTscPage(PVM pVM);
|
|---|
| 520 | VMMR3_INT_DECL(int) gimR3HvEnableTscPage(PVM pVM, RTGCPHYS GCPhysTscPage, bool fUseThisTscSeq, uint32_t uTscSeq);
|
|---|
| 521 | VMMR3_INT_DECL(int) gimR3HvDisableHypercallPage(PVM pVM);
|
|---|
| 522 | VMMR3_INT_DECL(int) gimR3HvEnableHypercallPage(PVM pVM, RTGCPHYS GCPhysHypercallPage);
|
|---|
| 523 | #endif /* IN_RING3 */
|
|---|
| 524 |
|
|---|
| 525 | VMM_INT_DECL(bool) gimHvIsParavirtTscEnabled(PVM pVM);
|
|---|
| 526 | VMM_INT_DECL(bool) gimHvAreHypercallsEnabled(PVMCPU pVCpu);
|
|---|
| 527 | VMM_INT_DECL(int) gimHvHypercall(PVMCPU pVCpu, PCPUMCTX pCtx);
|
|---|
| 528 | VMM_INT_DECL(VBOXSTRICTRC) gimHvReadMsr(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue);
|
|---|
| 529 | VMM_INT_DECL(VBOXSTRICTRC) gimHvWriteMsr(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uRawValue);
|
|---|
| 530 |
|
|---|
| 531 | RT_C_DECLS_END
|
|---|
| 532 |
|
|---|
| 533 | #endif
|
|---|
| 534 |
|
|---|
