VirtualBox

source: vbox/trunk/src/VBox/VMM/include/GIMHvInternal.h@ 58944

Last change on this file since 58944 was 58392, checked in by vboxsync, 9 years ago

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1/* $Id: GIMHvInternal.h 58392 2015-10-23 13:08:58Z vboxsync $ */
2/** @file
3 * GIM - Hyper-V, Internal header file.
4 */
5
6/*
7 * Copyright (C) 2014-2015 Oracle Corporation
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 */
17
18#ifndef ___GIMHvInternal_h
19#define ___GIMHvInternal_h
20
21#include <VBox/vmm/gim.h>
22#include <VBox/vmm/cpum.h>
23
24#include <iprt/net.h>
25
26/** @name Hyper-V base feature identification.
27 * Features based on current partition privileges (per-VM).
28 * @{
29 */
30/** Virtual processor runtime MSR available. */
31#define GIM_HV_BASE_FEAT_VP_RUNTIME_MSR RT_BIT(0)
32/** Partition reference counter MSR available. */
33#define GIM_HV_BASE_FEAT_PART_TIME_REF_COUNT_MSR RT_BIT(1)
34/** Basic Synthetic Interrupt Controller MSRs available. */
35#define GIM_HV_BASE_FEAT_BASIC_SYNIC_MSRS RT_BIT(2)
36/** Synthetic Timer MSRs available. */
37#define GIM_HV_BASE_FEAT_STIMER_MSRS RT_BIT(3)
38/** APIC access MSRs (EOI, ICR, TPR) available. */
39#define GIM_HV_BASE_FEAT_APIC_ACCESS_MSRS RT_BIT(4)
40/** Hypercall MSRs available. */
41#define GIM_HV_BASE_FEAT_HYPERCALL_MSRS RT_BIT(5)
42/** Access to VCPU index MSR available. */
43#define GIM_HV_BASE_FEAT_VP_ID_MSR RT_BIT(6)
44/** Virtual system reset MSR available. */
45#define GIM_HV_BASE_FEAT_VIRT_SYS_RESET_MSR RT_BIT(7)
46/** Statistic pages MSRs available. */
47#define GIM_HV_BASE_FEAT_STAT_PAGES_MSR RT_BIT(8)
48/** Paritition reference TSC MSR available. */
49#define GIM_HV_BASE_FEAT_PART_REF_TSC_MSR RT_BIT(9)
50/** Virtual guest idle state MSR available. */
51#define GIM_HV_BASE_FEAT_GUEST_IDLE_STATE_MSR RT_BIT(10)
52/** Timer frequency MSRs (TSC and APIC) available. */
53#define GIM_HV_BASE_FEAT_TIMER_FREQ_MSRS RT_BIT(11)
54/** Debug MSRs available. */
55#define GIM_HV_BASE_FEAT_DEBUG_MSRS RT_BIT(12)
56/** @} */
57
58/** @name Hyper-V partition-creation feature identification.
59 * Indicates flags specified during partition creation.
60 * @{
61 */
62/** Create partitions. */
63#define GIM_HV_PART_FLAGS_CREATE_PART RT_BIT(0)
64/** Access partition Id. */
65#define GIM_HV_PART_FLAGS_ACCESS_PART_ID RT_BIT(1)
66/** Access memory pool. */
67#define GIM_HV_PART_FLAGS_ACCESS_MEMORY_POOL RT_BIT(2)
68/** Adjust message buffers. */
69#define GIM_HV_PART_FLAGS_ADJUST_MSG_BUFFERS RT_BIT(3)
70/** Post messages. */
71#define GIM_HV_PART_FLAGS_POST_MSGS RT_BIT(4)
72/** Signal events. */
73#define GIM_HV_PART_FLAGS_SIGNAL_EVENTS RT_BIT(5)
74/** Create port. */
75#define GIM_HV_PART_FLAGS_CREATE_PORT RT_BIT(6)
76/** Connect port. */
77#define GIM_HV_PART_FLAGS_CONNECT_PORT RT_BIT(7)
78/** Access statistics. */
79#define GIM_HV_PART_FLAGS_ACCESS_STATS RT_BIT(8)
80/** Debugging.*/
81#define GIM_HV_PART_FLAGS_DEBUGGING RT_BIT(11)
82/** CPU management. */
83#define GIM_HV_PART_FLAGS_CPU_MGMT RT_BIT(12)
84/** CPU profiler. */
85#define GIM_HV_PART_FLAGS_CPU_PROFILER RT_BIT(13)
86/** Enable expanded stack walking. */
87#define GIM_HV_PART_FLAGS_EXPANDED_STACK_WALK RT_BIT(14)
88/** @} */
89
90/** @name Hyper-V power management feature identification.
91 * @{
92 */
93/** Maximum CPU power state C0. */
94#define GIM_HV_PM_MAX_CPU_POWER_STATE_C0 RT_BIT(0)
95/** Maximum CPU power state C1. */
96#define GIM_HV_PM_MAX_CPU_POWER_STATE_C1 RT_BIT(1)
97/** Maximum CPU power state C2. */
98#define GIM_HV_PM_MAX_CPU_POWER_STATE_C2 RT_BIT(2)
99/** Maximum CPU power state C3. */
100#define GIM_HV_PM_MAX_CPU_POWER_STATE_C3 RT_BIT(3)
101/** HPET is required to enter C3 power state. */
102#define GIM_HV_PM_HPET_REQD_FOR_C3 RT_BIT(4)
103/** @} */
104
105/** @name Hyper-V miscellaneous feature identification.
106 * Miscellaneous features available for the current partition.
107 * @{
108 */
109/** MWAIT instruction available. */
110#define GIM_HV_MISC_FEAT_MWAIT RT_BIT(0)
111/** Guest debugging support available. */
112#define GIM_HV_MISC_FEAT_GUEST_DEBUGGING RT_BIT(1)
113/** Performance monitor support is available. */
114#define GIM_HV_MISC_FEAT_PERF_MON RT_BIT(2)
115/** Support for physical CPU dynamic partitioning events. */
116#define GIM_HV_MISC_FEAT_PCPU_DYN_PART_EVENT RT_BIT(3)
117/** Support for passing hypercall input parameter block via XMM registers. */
118#define GIM_HV_MISC_FEAT_XMM_HYPERCALL_INPUT RT_BIT(4)
119/** Support for virtual guest idle state. */
120#define GIM_HV_MISC_FEAT_GUEST_IDLE_STATE RT_BIT(5)
121/** Support for hypervisor sleep state. */
122#define GIM_HV_MISC_FEAT_HYPERVISOR_SLEEP_STATE RT_BIT(6)
123/** Support for querying NUMA distances. */
124#define GIM_HV_MISC_FEAT_QUERY_NUMA_DISTANCE RT_BIT(7)
125/** Support for determining timer frequencies. */
126#define GIM_HV_MISC_FEAT_TIMER_FREQ RT_BIT(8)
127/** Support for injecting synthetic machine checks. */
128#define GIM_HV_MISC_FEAT_INJECT_SYNMC_XCPT RT_BIT(9)
129/** Support for guest crash MSRs. */
130#define GIM_HV_MISC_FEAT_GUEST_CRASH_MSRS RT_BIT(10)
131/** Support for debug MSRs. */
132#define GIM_HV_MISC_FEAT_DEBUG_MSRS RT_BIT(11)
133/** Npiep1 Available */ /** @todo What the heck is this? */
134#define GIM_HV_MISC_FEAT_NPIEP1 RT_BIT(12)
135/** Disable hypervisor available. */
136#define GIM_HV_MISC_FEAT_DISABLE_HYPERVISOR RT_BIT(13)
137/** @} */
138
139/** @name Hyper-V implementation recommendations.
140 * Recommendations from the hypervisor for the guest for optimal performance.
141 * @{
142 */
143/** Use hypercall for address space switches rather than MOV CR3. */
144#define GIM_HV_HINT_HYPERCALL_FOR_PROCESS_SWITCH RT_BIT(0)
145/** Use hypercall for local TLB flushes rather than INVLPG/MOV CR3. */
146#define GIM_HV_HINT_HYPERCALL_FOR_TLB_FLUSH RT_BIT(1)
147/** Use hypercall for inter-CPU TLB flushes rather than IPIs. */
148#define GIM_HV_HINT_HYPERCALL_FOR_TLB_SHOOTDOWN RT_BIT(2)
149/** Use MSRs for APIC access (EOI, ICR, TPR) rather than MMIO. */
150#define GIM_HV_HINT_MSR_FOR_APIC_ACCESS RT_BIT(3)
151/** Use hypervisor provided MSR for a system reset. */
152#define GIM_HV_HINT_MSR_FOR_SYS_RESET RT_BIT(4)
153/** Relax timer-related checks (watchdogs/deadman timeouts) that rely on
154 * timely deliver of external interrupts. */
155#define GIM_HV_HINT_RELAX_TIME_CHECKS RT_BIT(5)
156/** Use DMA remapping. */
157#define GIM_HV_HINT_DMA_REMAPPING RT_BIT(6)
158/** Use interrupt remapping. */
159#define GIM_HV_HINT_INTERRUPT_REMAPPING RT_BIT(7)
160/** Use X2APIC MSRs rather than MMIO. */
161#define GIM_HV_HINT_X2APIC_MSRS RT_BIT(8)
162/** Deprecate Auto EOI (end of interrupt). */
163#define GIM_HV_HINT_DEPRECATE_AUTO_EOI RT_BIT(9)
164/** @} */
165
166
167/** @name Hyper-V implementation hardware features.
168 * Which hardware features are in use by the hypervisor.
169 * @{
170 */
171/** APIC overlay is used. */
172#define GIM_HV_HOST_FEAT_AVIC RT_BIT(0)
173/** MSR bitmaps is used. */
174#define GIM_HV_HOST_FEAT_MSR_BITMAP RT_BIT(1)
175/** Architectural performance counter supported. */
176#define GIM_HV_HOST_FEAT_PERF_COUNTER RT_BIT(2)
177/** Nested paging is used. */
178#define GIM_HV_HOST_FEAT_NESTED_PAGING RT_BIT(3)
179/** DMA remapping is used. */
180#define GIM_HV_HOST_FEAT_DMA_REMAPPING RT_BIT(4)
181/** Interrupt remapping is used. */
182#define GIM_HV_HOST_FEAT_INTERRUPT_REMAPPING RT_BIT(5)
183/** Memory patrol scrubber is present. */
184#define GIM_HV_HOST_FEAT_MEM_PATROL_SCRUBBER RT_BIT(6)
185/** @} */
186
187
188/** @name Hyper-V MSRs.
189 * @{
190 */
191/** Start of range 0. */
192#define MSR_GIM_HV_RANGE0_START UINT32_C(0x40000000)
193/** Guest OS identification (R/W) */
194#define MSR_GIM_HV_GUEST_OS_ID UINT32_C(0x40000000)
195/** Enable hypercall interface (R/W) */
196#define MSR_GIM_HV_HYPERCALL UINT32_C(0x40000001)
197/** Virtual processor's (VCPU) index (R) */
198#define MSR_GIM_HV_VP_INDEX UINT32_C(0x40000002)
199/** Reset operation (R/W) */
200#define MSR_GIM_HV_RESET UINT32_C(0x40000003)
201/** End of range 0. */
202#define MSR_GIM_HV_RANGE0_END MSR_GIM_HV_RESET
203
204/** Start of range 1. */
205#define MSR_GIM_HV_RANGE1_START UINT32_C(0x40000010)
206/** Virtual processor's (VCPU) runtime (R) */
207#define MSR_GIM_HV_VP_RUNTIME UINT32_C(0x40000010)
208/** End of range 1. */
209#define MSR_GIM_HV_RANGE1_END MSR_GIM_HV_VP_RUNTIME
210
211/** Start of range 2. */
212#define MSR_GIM_HV_RANGE2_START UINT32_C(0x40000020)
213/** Per-VM reference counter (R) */
214#define MSR_GIM_HV_TIME_REF_COUNT UINT32_C(0x40000020)
215/** Per-VM TSC page (R/W) */
216#define MSR_GIM_HV_REF_TSC UINT32_C(0x40000021)
217/** Frequency of TSC in Hz as reported by the hypervisor (R) */
218#define MSR_GIM_HV_TSC_FREQ UINT32_C(0x40000022)
219/** Frequency of LAPIC in Hz as reported by the hypervisor (R) */
220#define MSR_GIM_HV_APIC_FREQ UINT32_C(0x40000023)
221/** End of range 2. */
222#define MSR_GIM_HV_RANGE2_END MSR_GIM_HV_APIC_FREQ
223
224/** Start of range 3. */
225#define MSR_GIM_HV_RANGE3_START UINT32_C(0x40000070)
226/** Access to APIC EOI (End-Of-Interrupt) register (W) */
227#define MSR_GIM_HV_EOI UINT32_C(0x40000070)
228/** Access to APIC ICR (Interrupt Command) register (R/W) */
229#define MSR_GIM_HV_ICR UINT32_C(0x40000071)
230/** Access to APIC TPR (Task Priority) register (R/W) */
231#define MSR_GIM_HV_TPR UINT32_C(0x40000072)
232/** Enables lazy EOI processing (R/W) */
233#define MSR_GIM_HV_APIC_ASSIST_PAGE UINT32_C(0x40000073)
234/** End of range 3. */
235#define MSR_GIM_HV_RANGE3_END MSR_GIM_HV_APIC_ASSIST_PAGE
236
237/** Start of range 4. */
238#define MSR_GIM_HV_RANGE4_START UINT32_C(0x40000080)
239/** Control behaviour of synthetic interrupt controller (R/W) */
240#define MSR_GIM_HV_SCONTROL UINT32_C(0x40000080)
241/** Synthetic interrupt controller version (R) */
242#define MSR_GIM_HV_SVERSION UINT32_C(0x40000081)
243/** Base address of synthetic interrupt event flag (R/W) */
244#define MSR_GIM_HV_SIEFP UINT32_C(0x40000082)
245/** Base address of synthetic interrupt message page (R/W) */
246#define MSR_GIM_HV_SIMP UINT32_C(0x40000083)
247/** End-Of-Message in synthetic interrupt parameter page (W) */
248#define MSR_GIM_HV_EOM UINT32_C(0x40000084)
249/** End of range 4. */
250#define MSR_GIM_HV_RANGE4_END MSR_GIM_HV_EOM
251
252/** Start of range 5. */
253#define MSR_GIM_HV_RANGE5_START UINT32_C(0x40000090)
254/** Configures synthetic interrupt source 0 (R/W) */
255#define MSR_GIM_HV_SINT0 UINT32_C(0x40000090)
256/** Configures synthetic interrupt source 1 (R/W) */
257#define MSR_GIM_HV_SINT1 UINT32_C(0x40000091)
258/** Configures synthetic interrupt source 2 (R/W) */
259#define MSR_GIM_HV_SINT2 UINT32_C(0x40000092)
260/** Configures synthetic interrupt source 3 (R/W) */
261#define MSR_GIM_HV_SINT3 UINT32_C(0x40000093)
262/** Configures synthetic interrupt source 4 (R/W) */
263#define MSR_GIM_HV_SINT4 UINT32_C(0x40000094)
264/** Configures synthetic interrupt source 5 (R/W) */
265#define MSR_GIM_HV_SINT5 UINT32_C(0x40000095)
266/** Configures synthetic interrupt source 6 (R/W) */
267#define MSR_GIM_HV_SINT6 UINT32_C(0x40000096)
268/** Configures synthetic interrupt source 7 (R/W) */
269#define MSR_GIM_HV_SINT7 UINT32_C(0x40000097)
270/** Configures synthetic interrupt source 8 (R/W) */
271#define MSR_GIM_HV_SINT8 UINT32_C(0x40000098)
272/** Configures synthetic interrupt source 9 (R/W) */
273#define MSR_GIM_HV_SINT9 UINT32_C(0x40000099)
274/** Configures synthetic interrupt source 10 (R/W) */
275#define MSR_GIM_HV_SINT10 UINT32_C(0x4000009A)
276/** Configures synthetic interrupt source 11 (R/W) */
277#define MSR_GIM_HV_SINT11 UINT32_C(0x4000009B)
278/** Configures synthetic interrupt source 12 (R/W) */
279#define MSR_GIM_HV_SINT12 UINT32_C(0x4000009C)
280/** Configures synthetic interrupt source 13 (R/W) */
281#define MSR_GIM_HV_SINT13 UINT32_C(0x4000009D)
282/** Configures synthetic interrupt source 14 (R/W) */
283#define MSR_GIM_HV_SINT14 UINT32_C(0x4000009E)
284/** Configures synthetic interrupt source 15 (R/W) */
285#define MSR_GIM_HV_SINT15 UINT32_C(0x4000009F)
286/** End of range 5. */
287#define MSR_GIM_HV_RANGE5_END MSR_GIM_HV_SINT15
288
289/** Start of range 6. */
290#define MSR_GIM_HV_RANGE6_START UINT32_C(0x400000B0)
291/** Configures register for synthetic timer 0 (R/W) */
292#define MSR_GIM_HV_STIMER0_CONFIG UINT32_C(0x400000B0)
293/** Expiration time or period for synthetic timer 0 (R/W) */
294#define MSR_GIM_HV_STIMER0_COUNT UINT32_C(0x400000B1)
295/** Configures register for synthetic timer 1 (R/W) */
296#define MSR_GIM_HV_STIMER1_CONFIG UINT32_C(0x400000B2)
297/** Expiration time or period for synthetic timer 1 (R/W) */
298#define MSR_GIM_HV_STIMER1_COUNT UINT32_C(0x400000B3)
299/** Configures register for synthetic timer 2 (R/W) */
300#define MSR_GIM_HV_STIMER2_CONFIG UINT32_C(0x400000B4)
301/** Expiration time or period for synthetic timer 2 (R/W) */
302#define MSR_GIM_HV_STIMER2_COUNT UINT32_C(0x400000B5)
303/** Configures register for synthetic timer 3 (R/W) */
304#define MSR_GIM_HV_STIMER3_CONFIG UINT32_C(0x400000B6)
305/** Expiration time or period for synthetic timer 3 (R/W) */
306#define MSR_GIM_HV_STIMER3_COUNT UINT32_C(0x400000B7)
307/** End of range 6. */
308#define MSR_GIM_HV_RANGE6_END MSR_GIM_HV_STIMER3_COUNT
309
310/** Start of range 7. */
311#define MSR_GIM_HV_RANGE7_START UINT32_C(0x400000C1)
312/** Trigger to transition to power state C1 (R) */
313#define MSR_GIM_HV_POWER_STATE_TRIGGER_C1 UINT32_C(0x400000C1)
314/** Trigger to transition to power state C2 (R) */
315#define MSR_GIM_HV_POWER_STATE_TRIGGER_C2 UINT32_C(0x400000C2)
316/** Trigger to transition to power state C3 (R) */
317#define MSR_GIM_HV_POWER_STATE_TRIGGER_C3 UINT32_C(0x400000C3)
318/** End of range 7. */
319#define MSR_GIM_HV_RANGE7_END MSR_GIM_HV_POWER_STATE_TRIGGER_C3
320
321/** Start of range 8. */
322#define MSR_GIM_HV_RANGE8_START UINT32_C(0x400000D1)
323/** Configure the recipe for power state transitions to C1 (R/W) */
324#define MSR_GIM_HV_POWER_STATE_CONFIG_C1 UINT32_C(0x400000D1)
325/** Configure the recipe for power state transitions to C2 (R/W) */
326#define MSR_GIM_HV_POWER_STATE_CONFIG_C2 UINT32_C(0x400000D2)
327/** Configure the recipe for power state transitions to C3 (R/W) */
328#define MSR_GIM_HV_POWER_STATE_CONFIG_C3 UINT32_C(0x400000D3)
329/** End of range 8. */
330#define MSR_GIM_HV_RANGE8_END MSR_GIM_HV_POWER_STATE_CONFIG_C3
331
332/** Start of range 9. */
333#define MSR_GIM_HV_RANGE9_START UINT32_C(0x400000E0)
334/** Map the guest's retail partition stats page (R/W) */
335#define MSR_GIM_HV_STATS_PART_RETAIL_PAGE UINT32_C(0x400000E0)
336/** Map the guest's internal partition stats page (R/W) */
337#define MSR_GIM_HV_STATS_PART_INTERNAL_PAGE UINT32_C(0x400000E1)
338/** Map the guest's retail VP stats page (R/W) */
339#define MSR_GIM_HV_STATS_VP_RETAIL_PAGE UINT32_C(0x400000E2)
340/** Map the guest's internal VP stats page (R/W) */
341#define MSR_GIM_HV_STATS_VP_INTERNAL_PAGE UINT32_C(0x400000E3)
342/** End of range 9. */
343#define MSR_GIM_HV_RANGE9_END MSR_GIM_HV_STATS_VP_INTERNAL_PAGE
344
345/** Start of range 10. */
346#define MSR_GIM_HV_RANGE10_START UINT32_C(0x400000F0)
347/** Trigger the guest's transition to idle power state (R) */
348#define MSR_GIM_HV_GUEST_IDLE UINT32_C(0x400000F0)
349/** Synthetic debug control. */
350#define MSR_GIM_HV_SYNTH_DEBUG_CONTROL UINT32_C(0x400000F1)
351/** Synthetic debug status. */
352#define MSR_GIM_HV_SYNTH_DEBUG_STATUS UINT32_C(0x400000F2)
353/** Synthetic debug send buffer. */
354#define MSR_GIM_HV_SYNTH_DEBUG_SEND_BUFFER UINT32_C(0x400000F3)
355/** Synthetic debug receive buffer. */
356#define MSR_GIM_HV_SYNTH_DEBUG_RECEIVE_BUFFER UINT32_C(0x400000F4)
357/** Synthetic debug pending buffer. */
358#define MSR_GIM_HV_SYNTH_DEBUG_PENDING_BUFFER UINT32_C(0x400000F5)
359/** End of range 10. */
360#define MSR_GIM_HV_RANGE10_END MSR_GIM_HV_SYNTH_DEBUG_PENDING_BUFFER
361
362/** Start of range 11. */
363#define MSR_GIM_HV_RANGE11_START UINT32_C(0x400000FF)
364/** Undocumented debug options MSR. */
365#define MSR_GIM_HV_DEBUG_OPTIONS_MSR UINT32_C(0x400000FF)
366/** End of range 11. */
367#define MSR_GIM_HV_RANGE11_END MSR_GIM_HV_DEBUG_OPTIONS_MSR
368
369/** Start of range 12. */
370#define MSR_GIM_HV_RANGE12_START UINT32_C(0x40000100)
371/** Guest crash MSR 0. */
372#define MSR_GIM_HV_CRASH_P0 UINT32_C(0x40000100)
373/** Guest crash MSR 1. */
374#define MSR_GIM_HV_CRASH_P1 UINT32_C(0x40000101)
375/** Guest crash MSR 2. */
376#define MSR_GIM_HV_CRASH_P2 UINT32_C(0x40000102)
377/** Guest crash MSR 3. */
378#define MSR_GIM_HV_CRASH_P3 UINT32_C(0x40000103)
379/** Guest crash MSR 4. */
380#define MSR_GIM_HV_CRASH_P4 UINT32_C(0x40000104)
381/** Guest crash control. */
382#define MSR_GIM_HV_CRASH_CTL UINT32_C(0x40000105)
383/** End of range 12. */
384#define MSR_GIM_HV_RANGE12_END MSR_GIM_HV_CRASH_CTL
385/** @} */
386
387AssertCompile(MSR_GIM_HV_RANGE0_START <= MSR_GIM_HV_RANGE0_END);
388AssertCompile(MSR_GIM_HV_RANGE1_START <= MSR_GIM_HV_RANGE1_END);
389AssertCompile(MSR_GIM_HV_RANGE2_START <= MSR_GIM_HV_RANGE2_END);
390AssertCompile(MSR_GIM_HV_RANGE3_START <= MSR_GIM_HV_RANGE3_END);
391AssertCompile(MSR_GIM_HV_RANGE4_START <= MSR_GIM_HV_RANGE4_END);
392AssertCompile(MSR_GIM_HV_RANGE5_START <= MSR_GIM_HV_RANGE5_END);
393AssertCompile(MSR_GIM_HV_RANGE6_START <= MSR_GIM_HV_RANGE6_END);
394AssertCompile(MSR_GIM_HV_RANGE7_START <= MSR_GIM_HV_RANGE7_END);
395AssertCompile(MSR_GIM_HV_RANGE8_START <= MSR_GIM_HV_RANGE8_END);
396AssertCompile(MSR_GIM_HV_RANGE9_START <= MSR_GIM_HV_RANGE9_END);
397AssertCompile(MSR_GIM_HV_RANGE10_START <= MSR_GIM_HV_RANGE10_END);
398AssertCompile(MSR_GIM_HV_RANGE11_START <= MSR_GIM_HV_RANGE11_END);
399
400/** @name Hyper-V MSR - Reset (MSR_GIM_HV_RESET).
401 * @{
402 */
403/** The hypercall enable bit. */
404#define MSR_GIM_HV_RESET_BIT RT_BIT_64(0)
405/** Whether the hypercall-page is enabled or not. */
406#define MSR_GIM_HV_RESET_IS_SET(a) RT_BOOL((a) & MSR_GIM_HV_RESET_BIT)
407/** @} */
408
409/** @name Hyper-V MSR - Hypercall (MSR_GIM_HV_HYPERCALL).
410 * @{
411 */
412/** Guest-physical page frame number of the hypercall-page. */
413#define MSR_GIM_HV_HYPERCALL_GUEST_PFN(a) ((a) >> 12)
414/** The hypercall enable bit. */
415#define MSR_GIM_HV_HYPERCALL_PAGE_ENABLE_BIT RT_BIT_64(0)
416/** Whether the hypercall-page is enabled or not. */
417#define MSR_GIM_HV_HYPERCALL_PAGE_IS_ENABLED(a) RT_BOOL((a) & MSR_GIM_HV_HYPERCALL_PAGE_ENABLE_BIT)
418/** @} */
419
420/** @name Hyper-V MSR - Reference TSC (MSR_GIM_HV_REF_TSC).
421 * @{
422 */
423/** Guest-physical page frame number of the TSC-page. */
424#define MSR_GIM_HV_REF_TSC_GUEST_PFN(a) ((a) >> 12)
425/** The TSC-page enable bit. */
426#define MSR_GIM_HV_REF_TSC_ENABLE_BIT RT_BIT_64(0)
427/** Whether the TSC-page is enabled or not. */
428#define MSR_GIM_HV_REF_TSC_IS_ENABLED(a) RT_BOOL((a) & MSR_GIM_HV_REF_TSC_ENABLE_BIT)
429/** @} */
430
431/** @name Hyper-V MSR - Guest crash control (MSR_GIM_HV_CRASH_CTL).
432 * @{
433 */
434/** The Crash Notify bit. */
435#define MSR_GIM_HV_CRASH_CTL_NOTIFY_BIT RT_BIT_64(63)
436/** @} */
437
438/** @name Hyper-V MSR - Guest OS ID (MSR_GIM_HV_GUEST_OS_ID).
439 * @{
440 */
441/** An open-source operating system. */
442#define MSR_GIM_HV_GUEST_OS_ID_IS_OPENSOURCE(a) RT_BOOL((a) & RT_BIT_64(63))
443/** Vendor ID. */
444#define MSR_GIM_HV_GUEST_OS_ID_VENDOR(a) (((a) >> 48) & 0xfff)
445/** Guest OS variant, depending on the vendor ID. */
446#define MSR_GIM_HV_GUEST_OS_ID_OS_VARIANT(a) (((a) >> 40) & 0xff)
447/** Guest OS major version. */
448#define MSR_GIM_HV_GUEST_OS_ID_MAJOR_VERSION(a) (((a) >> 32) & 0xff)
449/** Guest OS minor version. */
450#define MSR_GIM_HV_GUEST_OS_ID_MINOR_VERSION(a) (((a) >> 24) & 0xff)
451/** Guest OS service version (e.g. service pack number in case of Windows). */
452#define MSR_GIM_HV_GUEST_OS_ID_SERVICE_VERSION(a) (((a) >> 16) & 0xff)
453/** Guest OS build number. */
454#define MSR_GIM_HV_GUEST_OS_ID_BUILD(a) ((a) & 0xffff)
455/** @} */
456
457
458/**
459 * Hypercall parameter type.
460 */
461typedef enum GIMHVHYPERCALLPARAM
462{
463 GIMHVHYPERCALLPARAM_IN = 0,
464 GIMHVHYPERCALLPARAM_OUT
465} GIMHVHYPERCALLPARAM;
466
467
468/** @name Hyper-V hypercall op codes.
469 * @{
470 */
471/** Post message to hypervisor or VMs. */
472#define GIM_HV_HYPERCALL_OP_POST_MESSAGE 0x5C
473/** Post debug data to hypervisor. */
474#define GIM_HV_HYPERCALL_OP_POST_DEBUG_DATA 0x69
475/** Retreive debug data from hypervisor. */
476#define GIM_HV_HYPERCALL_OP_RETREIVE_DEBUG_DATA 0x6A
477/** Reset debug session. */
478#define GIM_HV_HYPERCALL_OP_RESET_DEBUG_SESSION 0x6B
479/** @} */
480
481
482/** @name Hyper-V hypercall inputs.
483 * @{
484 */
485/** The hypercall call operation code. */
486#define GIM_HV_HYPERCALL_IN_CALL_CODE(a) ((a) & UINT64_C(0xffff))
487/** Whether it's a fast (register based) hypercall or not (memory-based). */
488#define GIM_HV_HYPERCALL_IN_IS_FAST(a) RT_BOOL((a) & RT_BIT_64(16))
489/** Total number of reps for a rep hypercall. */
490#define GIM_HV_HYPERCALL_IN_REP_COUNT(a) (((a) << 32) & UINT64_C(0xfff))
491/** Rep start index for a rep hypercall. */
492#define GIM_HV_HYPERCALL_IN_REP_START_IDX(a) (((a) << 48) & UINT64_C(0xfff))
493/** Reserved bits range 1. */
494#define GIM_HV_HYPERCALL_IN_RSVD_1(a) (((a) << 17) & UINT64_C(0x7fff))
495/** Reserved bits range 2. */
496#define GIM_HV_HYPERCALL_IN_RSVD_2(a) (((a) << 44) & UINT64_C(0xf))
497/** Reserved bits range 3. */
498#define GIM_HV_HYPERCALL_IN_RSVD_3(a) (((a) << 60) & UINT64_C(0x7))
499/** @} */
500
501
502/** @name Hyper-V hypercall status codes.
503 * @{
504 */
505/** Success. */
506#define GIM_HV_STATUS_SUCCESS 0x00
507/** Unrecognized hypercall. */
508#define GIM_HV_STATUS_INVALID_HYPERCALL_CODE 0x02
509/** Invalid hypercall input (rep count, rsvd bits). */
510#define GIM_HV_STATUS_INVALID_HYPERCALL_INPUT 0x03
511/** Hypercall guest-physical address not 8-byte aligned or crosses page boundary. */
512#define GIM_HV_STATUS_INVALID_ALIGNMENT 0x04
513/** Invalid hypercall parameters. */
514#define GIM_HV_STATUS_INVALID_PARAMETER 0x05
515/** Access denied. */
516#define GIM_HV_STATUS_ACCESS_DENIED 0x06
517/** The partition state not valid for specified op. */
518#define GIM_HV_STATUS_INVALID_PARTITION_STATE 0x07
519/** The hypercall operation could not be performed. */
520#define GIM_HV_STATUS_OPERATION_DENIED 0x08
521/** Specified partition property ID not recognized. */
522#define GIM_HV_STATUS_UNKNOWN_PROPERTY 0x09
523/** Specified partition property value not within range. */
524#define GIM_HV_STATUS_PROPERTY_VALUE_OUT_OF_RANGE 0x0a
525/** Insufficient memory for performing the hypercall. */
526#define GIM_HV_STATUS_INSUFFICIENT_MEMORY 0x0b
527/** Maximum partition depth has been exceeded for the partition hierarchy. */
528#define GIM_HV_STATUS_PARTITION_TOO_DEEP 0x0c
529/** The specified partition ID is not valid. */
530#define GIM_HV_STATUS_INVALID_PARTITION_ID 0x0d
531/** The specified virtual processor index in invalid. */
532#define GIM_HV_STATUS_INVALID_VP_INDEX 0x0e
533/** The specified port ID is not unique or doesn't exist. */
534#define GIM_HV_STATUS_INVALID_PORT_ID 0x11
535/** The specified connection ID is not unique or doesn't exist. */
536#define GIM_HV_STATUS_INVALID_CONNECTION_ID 0x12
537/** The target port doesn't have sufficient buffers for the caller to post a message. */
538#define GIM_HV_STATUS_INSUFFICIENT_BUFFERS 0x13
539/** External interrupt not acknowledged.*/
540#define GIM_HV_STATUS_NOT_ACKNOWLEDGED 0x14
541/** External interrupt acknowledged. */
542#define GIM_HV_STATUS_ACKNOWLEDGED 0x16
543/** Invalid state due to misordering Hv[Save|Restore]PartitionState. */
544#define GIM_HV_STATUS_INVALID_SAVE_RESTORE_STATE 0x17
545/** Operation not perform due to a required feature of SynIc was disabled. */
546#define GIM_HV_STATUS_INVALID_SYNIC_STATE 0x18
547/** Object or value already in use. */
548#define GIM_HV_STATUS_OBJECT_IN_USE 0x19
549/** Invalid proximity domain information. */
550#define GIM_HV_STATUS_INVALID_PROXIMITY_DOMAIN_INFO 0x1A
551/** Attempt to retrieve data failed. */
552#define GIM_HV_STATUS_NO_DATA 0x1B
553/** Debug connection has not recieved any new data since the last time. */
554#define GIM_HV_STATUS_INACTIVE 0x1C
555/** A resource is unavailable for allocation. */
556#define GIM_HV_STATUS_NO_RESOURCES 0x1D
557/** A hypervisor feature is not available to the caller. */
558#define GIM_HV_STATUS_FEATURE_UNAVAILABLE 0x1E
559/** The debug packet returned is partial due to an I/O error. */
560#define GIM_HV_STATUS_PARTIAL_PACKET 0x1F
561/** Processor feature SSE3 unsupported. */
562#define GIM_HV_STATUS_PROC_FEAT_SSE3_NOT_SUPPORTED 0x20
563/** Processor feature LAHSAHF unsupported. */
564#define GIM_HV_STATUS_PROC_FEAT_LAHSAHF_NOT_SUPPORTED 0x21
565/** Processor feature SSSE3 unsupported. */
566#define GIM_HV_STATUS_PROC_FEAT_SSSE3_NOT_SUPPORTED 0x22
567/** Processor feature SSE4.1 unsupported. */
568#define GIM_HV_STATUS_PROC_FEAT_SSE4_1_NOT_SUPPORTED 0x23
569/** Processor feature SSE4.2 unsupported. */
570#define GIM_HV_STATUS_PROC_FEAT_SSE4_2_NOT_SUPPORTED 0x24
571/** Processor feature SSE4A unsupported. */
572#define GIM_HV_STATUS_PROC_FEAT_SSE4A_NOT_SUPPORTED 0x25
573/** Processor feature XOP unsupported. */
574#define GIM_HV_STATUS_PROC_FEAT_XOP_NOT_SUPPORTED 0x26
575/** Processor feature POPCNT unsupported. */
576#define GIM_HV_STATUS_PROC_FEAT_POPCNT_NOT_SUPPORTED 0x27
577/** Processor feature CMPXCHG16B unsupported. */
578#define GIM_HV_STATUS_PROC_FEAT_CMPXCHG16B_NOT_SUPPORTED 0x28
579/** Processor feature ALTMOVCR8 unsupported. */
580#define GIM_HV_STATUS_PROC_FEAT_ALTMOVCR8_NOT_SUPPORTED 0x29
581/** Processor feature LZCNT unsupported. */
582#define GIM_HV_STATUS_PROC_FEAT_LZCNT_NOT_SUPPORTED 0x2A
583/** Processor feature misaligned SSE unsupported. */
584#define GIM_HV_STATUS_PROC_FEAT_MISALIGNED_SSE_NOT_SUPPORTED 0x2B
585/** Processor feature MMX extensions unsupported. */
586#define GIM_HV_STATUS_PROC_FEAT_MMX_EXT_NOT_SUPPORTED 0x2C
587/** Processor feature 3DNow! unsupported. */
588#define GIM_HV_STATUS_PROC_FEAT_3DNOW_NOT_SUPPORTED 0x2D
589/** Processor feature Extended 3DNow! unsupported. */
590#define GIM_HV_STATUS_PROC_FEAT_EXTENDED_3DNOW_NOT_SUPPORTED 0x2E
591/** Processor feature 1GB large page unsupported. */
592#define GIM_HV_STATUS_PROC_FEAT_PAGE_1GB_NOT_SUPPORTED 0x2F
593/** Processor cache line flush size incompatible. */
594#define GIM_HV_STATUS_PROC_CACHE_LINE_FLUSH_SIZE_INCOMPATIBLE 0x30
595/** Processor feature XSAVE unsupported. */
596#define GIM_HV_STATUS_PROC_FEAT_XSAVE_NOT_SUPPORTED 0x31
597/** Processor feature XSAVEOPT unsupported. */
598#define GIM_HV_STATUS_PROC_FEAT_XSAVEOPT_NOT_SUPPORTED 0x32
599/** The specified buffer was too small for all requested data. */
600#define GIM_HV_STATUS_INSUFFICIENT_BUFFER 0x33
601/** Processor feature XSAVEOPT unsupported. */
602#define GIM_HV_STATUS_PROC_FEAT_XSAVE_AVX_NOT_SUPPORTED 0x34
603/** Processor feature XSAVEOPT unsupported. */
604#define GIM_HV_STATUS_PROC_FEAT_XSAVE_FEAT_NOT_SUPPORTED 0x35 /** Huh, isn't this same as 0x31? */
605/** Processor feature XSAVEOPT unsupported. */
606#define GIM_HV_STATUS_PROC_FEAT_PAGE_XSAVE_SAVE_AREA_INCOMPATIBLE 0x36
607/** Processor architecture unsupoorted. */
608#define GIM_HV_STATUS_INCOMPATIBLE_PROCESSOR 0x37
609/** Max. domains for platform I/O remapping reached. */
610#define GIM_HV_STATUS_INSUFFICIENT_DEVICE_DOMAINS 0x38
611/** Processor feature AES unsupported. */
612#define GIM_HV_STATUS_PROC_FEAT_AES_NOT_SUPPORTED 0x39
613/** Processor feature PCMULQDQ unsupported. */
614#define GIM_HV_STATUS_PROC_FEAT_PCMULQDQ_NOT_SUPPORTED 0x3A
615/** Processor feature XSAVE features unsupported. */
616#define GIM_HV_STATUS_PROC_FEAT_XSAVE_FEATURES_INCOMPATIBLE 0x3B
617/** Generic CPUID validation error. */
618#define GIM_HV_STATUS_CPUID_FEAT_VALIDATION_ERROR 0x3C
619/** XSAVE CPUID validation error. */
620#define GIM_HV_STATUS_CPUID_XSAVE_FEAT_VALIDATION_ERROR 0x3D
621/** Processor startup timed out. */
622#define GIM_HV_STATUS_PROCESSOR_STARTUP_TIMEOUT 0x3E
623/** SMX enabled by the BIOS. */
624#define GIM_HV_STATUS_SMX_ENABLED 0x3F
625/** Processor feature PCID unsupported. */
626#define GIM_HV_STATUS_PROC_FEAT_PCID_NOT_SUPPORTED 0x40
627/** Invalid LP index. */
628#define GIM_HV_STATUS_INVALID_LP_INDEX 0x41
629/** Processor feature PCID unsupported. */
630#define GIM_HV_STATUS_FEAT_FMA4_NOT_SUPPORTED 0x42
631/** Processor feature PCID unsupported. */
632#define GIM_HV_STATUS_FEAT_F16C_NOT_SUPPORTED 0x43
633/** Processor feature PCID unsupported. */
634#define GIM_HV_STATUS_PROC_FEAT_RDRAND_NOT_SUPPORTED 0x44
635/** Processor feature RDWRFSGS unsupported. */
636#define GIM_HV_STATUS_PROC_FEAT_RDWRFSGS_NOT_SUPPORTED 0x45
637/** Processor feature SMEP unsupported. */
638#define GIM_HV_STATUS_PROC_FEAT_SMEP_NOT_SUPPORTED 0x46
639/** Processor feature enhanced fast string unsupported. */
640#define GIM_HV_STATUS_PROC_FEAT_ENHANCED_FAST_STRING_NOT_SUPPORTED 0x47
641/** Processor feature MOVBE unsupported. */
642#define GIM_HV_STATUS_PROC_FEAT_MOVBE_NOT_SUPPORTED 0x48
643/** Processor feature BMI1 unsupported. */
644#define GIM_HV_STATUS_PROC_FEAT_BMI1_NOT_SUPPORTED 0x49
645/** Processor feature BMI2 unsupported. */
646#define GIM_HV_STATUS_PROC_FEAT_BMI2_NOT_SUPPORTED 0x4A
647/** Processor feature HLE unsupported. */
648#define GIM_HV_STATUS_PROC_FEAT_HLE_NOT_SUPPORTED 0x4B
649/** Processor feature RTM unsupported. */
650#define GIM_HV_STATUS_PROC_FEAT_RTM_NOT_SUPPORTED 0x4C
651/** Processor feature XSAVE FMA unsupported. */
652#define GIM_HV_STATUS_PROC_FEAT_XSAVE_FMA_NOT_SUPPORTED 0x4D
653/** Processor feature XSAVE AVX2 unsupported. */
654#define GIM_HV_STATUS_PROC_FEAT_XSAVE_AVX2_NOT_SUPPORTED 0x4E
655/** Processor feature NPIEP1 unsupported. */
656#define GIM_HV_STATUS_PROC_FEAT_NPIEP1_NOT_SUPPORTED 0x4F
657/** @} */
658
659
660/** @name Hyper-V MSR - Debug control (MSR_GIM_HV_SYNTH_DEBUG_CONTROL).
661 * @{
662 */
663/** Perform debug write. */
664#define MSR_GIM_HV_SYNTH_DEBUG_CONTROL_IS_WRITE(a) RT_BOOL((a) & RT_BIT_64(0))
665/** Perform debug read. */
666#define MSR_GIM_HV_SYNTH_DEBUG_CONTROL_IS_READ(a) RT_BOOL((a) & RT_BIT_64(1))
667/** Returns length of the debug write buffer. */
668#define MSR_GIM_HV_SYNTH_DEBUG_CONTROL_W_LEN(a) (((a) & UINT64_C(0xffff0000)) >> 16)
669/** @} */
670
671
672/** @name Hyper-V MSR - Debug status (MSR_GIM_HV_SYNTH_DEBUG_STATUS).
673 * @{
674 */
675/** Debug send buffer operation success. */
676#define MSR_GIM_HV_SYNTH_DEBUG_STATUS_W_SUCCESS_BIT RT_BIT_64(0)
677/** Debug receive buffer operation success. */
678#define MSR_GIM_HV_SYNTH_DEBUG_STATUS_R_SUCCESS_BIT RT_BIT_64(2)
679/** Debug connection was reset. */
680#define MSR_GIM_HV_SYNTH_DEBUG_STATUS_CONN_RESET_BIT RT_BIT_64(3)
681/** @} */
682
683
684/** @name Hyper-V MSR - synthetic interrupt (MSR_GIM_HV_SINTx).
685 * @{
686 */
687/** The interrupt masked bit. */
688#define MSR_GIM_HV_SINT_MASKED_BIT RT_BIT_64(16)
689/** Whether the interrupt source is masked. */
690#define MSR_GIM_HV_SINT_IS_MASKED(a) RT_BOOL((a) & MSR_GIM_HV_SINT_MASKED_BIT)
691/** Interrupt vector. */
692#define MSR_GIM_HV_SINT_VECTOR(a) ((a) & UINT64_C(0xff))
693/** @} */
694
695
696/** @name Hyper-V MSR - synthetic interrupt message page (MSR_GIM_HV_SIMP).
697 * @{
698 */
699/** The SIMP enabled bit. */
700#define MSR_GIM_HV_SIMP_ENABLED_BIT RT_BIT_64(0)
701/** Whether the SIMP is enabled. */
702#define MSR_GIM_HV_SIMP_IS_ENABLED(a) RT_BOOL((a) & MSR_GIM_HV_SIMP_ENABLED_BIT)
703/** The SIMP guest-physical address. */
704#define MSR_GIM_HV_SIMP_GPA(a) ((a) & UINT64_C(0xfffffffffffff000))
705/** @} */
706
707
708/** @name Hyper-V hypercall debug options.
709 * @{ */
710/** Maximum debug data payload size in bytes. */
711#define GIM_HV_DEBUG_MAX_DATA_SIZE 4088
712
713/** The undocumented bit for MSR_GIM_HV_DEBUG_OPTIONS_MSR that makes it all
714 * work. */
715#define GIM_HV_DEBUG_OPTIONS_USE_HYPERCALLS RT_BIT(2)
716
717/** Guest will perform the HvPostDebugData hypercall until completion. */
718#define GIM_HV_DEBUG_POST_LOOP RT_BIT_32(0)
719/** Mask of valid HvPostDebugData options. */
720#define GIM_HV_DEBUG_POST_OPTIONS_MASK RT_BIT_32(0)
721
722/** Guest will perform the HvRetrieveDebugData hypercall until completion. */
723#define GIM_HV_DEBUG_RETREIVE_LOOP RT_BIT_32(0)
724/** Guest checks if any global debug session is active. */
725#define GIM_HV_DEBUG_RETREIVE_TEST_ACTIVITY RT_BIT_32(1)
726/** Mask of valid HvRetrieveDebugData options. */
727#define GIM_HV_DEBUG_RETREIVE_OPTIONS_MASK RT_BIT_32(0) | RT_BIT_32(1)
728
729/** Guest requests purging of incoming debug data. */
730#define GIM_HV_DEBUG_PURGE_INCOMING_DATA RT_BIT_32(0)
731/** Guest requests purging of outgoing debug data. */
732#define GIM_HV_DEBUG_PURGE_OUTGOING_DATA RT_BIT_32(1)
733/** @}*/
734
735
736/** @name VMBus.
737 * These are just arbitrary definitions made up by Microsoft without
738 * any publicly available specification behind it.
739 * @{ */
740/** VMBus connection ID. */
741#define GIM_HV_VMBUS_MSG_CONNECTION_ID 1
742/** VMBus synthetic interrupt source. */
743#define GIM_HV_VMBUS_MSG_SINT 2
744/** @} */
745
746
747/** @name Hyper-V synthetic interrupt message type.
748 * @{
749 */
750typedef enum GIMHVMSGTYPE
751{
752 GIMHVMSGTYPE_NONE = 0, /* Common messages */
753 GIMHVMSGTYPE_VMBUS = 1, /* Guest messages */
754 GIMHVMSGTYPE_UNMAPPEDGPA = 0x80000000, /* Hypervisor messages */
755 GIMHVMSGTYPE_GPAINTERCEPT = 0x80000001,
756 GIMHVMSGTYPE_TIMEREXPIRED = 0x80000010,
757 GIMHVMSGTYPE_INVALIDVPREGVAL = 0x80000020,
758 GIMHVMSGTYPE_UNRECOVERABLEXCPT = 0x80000021,
759 GIMHVMSGTYPE_UNSUPPORTEDFEAT = 0x80000022,
760 GIMHVMSGTYPE_APICEOI = 0x80000030,
761 GIMHVMSGTYPE_X64LEGACYFPERROR = 0x80000031,
762 GIMHVMSGTYPE_EVENTLOGBUFSCOMPLETE = 0x80000040,
763 GIMHVMSGTYPE_X64IOPORTINTERCEPT = 0x80010000,
764 GIMHVMSGTYPE_X64MSRINTERCEPT = 0x80010001,
765 GIMHVMSGTYPE_X64CPUIDINTERCEPT = 0x80010002,
766 GIMHVMSGTYPE_X64XCPTINTERCEPT = 0x80010003
767} GIMHVMSGTYPE;
768AssertCompileSize(GIMHVMSGTYPE, 4);
769/** @} */
770
771
772/** @name Hyper-V synthetic interrupt message format.
773 * @{ */
774#define GIM_HV_MSG_SIZE 256
775#define GIM_HV_MSG_MAX_PAYLOAD_SIZE 240
776#define GIM_HV_MSG_MAX_PAYLOAD_UNITS 30
777
778/**
779 * Synthetic interrupt message flags.
780 */
781typedef union GIMHVMSGFLAGS
782{
783 struct
784 {
785 uint8_t u1Pending : 1;
786 uint8_t u7Reserved : 7;
787 } n;
788 uint8_t u;
789} GIMHVMSGFLAGS;
790AssertCompileSize(GIMHVMSGFLAGS, sizeof(uint8_t));
791
792/**
793 * Synthetic interrupt message header.
794 *
795 * @remarks The layout of this structure differs from
796 * the Hyper-V spec. Aug 8, 2013 v4.0a. Layout
797 * in accordance w/ VMBus client expectations.
798 */
799typedef struct GIMHVMSGHDR
800{
801 GIMHVMSGTYPE enmMessageType;
802 uint8_t cbPayload;
803 GIMHVMSGFLAGS MessageFlags;
804 uint16_t uRsvd;
805 union
806 {
807 uint64_t uOriginatorId;
808 uint64_t uPartitionId;
809 uint64_t uPortId;
810 } msgid;
811} GIMHVMSGHDR;
812/** Pointer to a synthetic interrupt message header. */
813typedef GIMHVMSGHDR *PGIMHVMSGHDR;
814AssertCompileMemberOffset(GIMHVMSGHDR, cbPayload, 4);
815AssertCompileMemberOffset(GIMHVMSGHDR, MessageFlags, 5);
816AssertCompileMemberOffset(GIMHVMSGHDR, msgid, 8);
817AssertCompileSize(GIMHVMSGHDR, GIM_HV_MSG_SIZE - GIM_HV_MSG_MAX_PAYLOAD_SIZE);
818
819/**
820 * Synthetic interrupt message.
821 */
822typedef struct GIMHVMSG
823{
824 GIMHVMSGHDR MsgHdr;
825 uint64_t aPayload[GIM_HV_MSG_MAX_PAYLOAD_UNITS];
826} GIMHVMSG;
827/** Pointer to a synthetic interrupt message. */
828typedef GIMHVMSG *PGIMHVMSG;
829AssertCompileSize(GIMHVMSG, GIM_HV_MSG_SIZE);
830/** @} */
831
832
833/** @name Hyper-V hypercall parameters.
834 * @{ */
835/**
836 * HvPostMessage hypercall input.
837 */
838typedef struct GIMHVPOSTMESSAGEIN
839{
840 uint32_t uConnectionId;
841 uint32_t uPadding;
842 GIMHVMSGTYPE enmMessageType;
843 uint32_t cbPayload;
844} GIMHVPOSTMESSAGEIN;
845/** Pointer to a HvPostMessage input struct. */
846typedef GIMHVPOSTMESSAGEIN *PGIMHVPOSTMESSAGEIN;
847AssertCompileSize(GIMHVPOSTMESSAGEIN, 16);
848
849/**
850 * HvResetDebugData hypercall input.
851 */
852typedef struct GIMHVDEBUGRESETIN
853{
854 uint32_t fFlags;
855 uint32_t uPadding;
856} GIMHVDEBUGRESETIN;
857/** Pointer to a HvResetDebugData input struct. */
858typedef GIMHVDEBUGRESETIN *PGIMHVDEBUGRESETIN;
859AssertCompileSize(GIMHVDEBUGRESETIN, 8);
860
861/**
862 * HvPostDebugData hypercall input.
863 */
864typedef struct GIMHVDEBUGPOSTIN
865{
866 uint32_t cbWrite;
867 uint32_t fFlags;
868} GIMHVDEBUGPOSTIN;
869/** Pointer to a HvPostDebugData input struct. */
870typedef GIMHVDEBUGPOSTIN *PGIMHVDEBUGPOSTIN;
871AssertCompileSize(GIMHVDEBUGPOSTIN, 8);
872
873/**
874 * HvPostDebugData hypercall output.
875 */
876typedef struct GIMHVDEBUGPOSTOUT
877{
878 uint32_t cbPending;
879 uint32_t uPadding;
880} GIMHVDEBUGPOSTOUT;
881/** Pointer to a HvPostDebugData output struct. */
882typedef GIMHVDEBUGPOSTOUT *PGIMHVDEBUGPOSTOUT;
883AssertCompileSize(GIMHVDEBUGPOSTOUT, 8);
884
885/**
886 * HvRetrieveDebugData hypercall input.
887 */
888typedef struct GIMHVDEBUGRETRIEVEIN
889{
890 uint32_t cbRead;
891 uint32_t fFlags;
892 uint64_t u64Timeout;
893} GIMHVDEBUGRETRIEVEIN;
894/** Pointer to a HvRetrieveDebugData input struct. */
895typedef GIMHVDEBUGRETRIEVEIN *PGIMHVDEBUGRETRIEVEIN;
896AssertCompileSize(GIMHVDEBUGRETRIEVEIN, 16);
897
898/**
899 * HvRetriveDebugData hypercall output.
900 */
901typedef struct GIMHVDEBUGRETRIEVEOUT
902{
903 uint32_t cbRead;
904 uint32_t cbRemaining;
905} GIMHVDEBUGRETRIEVEOUT;
906/** Pointer to a HvRetrieveDebugData output struct. */
907typedef GIMHVDEBUGRETRIEVEOUT *PGIMHVDEBUGRETRIEVEOUT;
908AssertCompileSize(GIMHVDEBUGRETRIEVEOUT, 8);
909/** @} */
910
911
912/** Hyper-V page size. */
913#define GIM_HV_PAGE_SIZE 4096
914
915/** Microsoft Hyper-V vendor signature. */
916#define GIM_HV_VENDOR_MICROSOFT "Microsoft Hv"
917
918/**
919 * MMIO2 region indices.
920 */
921/** The hypercall page region. */
922#define GIM_HV_HYPERCALL_PAGE_REGION_IDX UINT8_C(0)
923/** The TSC page region. */
924#define GIM_HV_REF_TSC_PAGE_REGION_IDX UINT8_C(1)
925/** The maximum region index (must be <= UINT8_MAX). */
926#define GIM_HV_REGION_IDX_MAX GIM_HV_REF_TSC_PAGE_REGION_IDX
927
928/**
929 * Hyper-V TSC (HV_REFERENCE_TSC_PAGE) structure placed in the TSC reference
930 * page.
931 */
932typedef struct GIMHVREFTSC
933{
934 uint32_t u32TscSequence;
935 uint32_t uReserved0;
936 uint64_t u64TscScale;
937 int64_t i64TscOffset;
938} GIMHVTSCPAGE;
939/** Pointer to Hyper-V reference TSC. */
940typedef GIMHVREFTSC *PGIMHVREFTSC;
941/** Pointer to a const Hyper-V reference TSC. */
942typedef GIMHVREFTSC const *PCGIMHVREFTSC;
943
944/**
945 * Type of the next reply to be sent to the debug connection of the guest.
946 *
947 * @remarks This is saved as part of saved-state, so don't re-order or
948 * alter the size!
949 */
950typedef enum GIMHVDEBUGREPLY
951{
952 /** Send UDP packet. */
953 GIMHVDEBUGREPLY_UDP = 0,
954 /** Send DHCP offer for DHCP discover. */
955 GIMHVDEBUGREPLY_DHCP_OFFER,
956 /** DHCP offer sent. */
957 GIMHVDEBUGREPLY_DHCP_OFFER_SENT,
958 /** Send DHCP acknowledgement for DHCP request. */
959 GIMHVDEBUGREPLY_DHCP_ACK,
960 /** DHCP acknowledgement sent. */
961 GIMHVDEBUGREPLY_DHCP_ACK_SENT,
962 /** Sent ARP reply. */
963 GIMHVDEBUGREPLY_ARP_REPLY,
964 /** ARP reply sent. */
965 GIMHVDEBUGREPLY_ARP_REPLY_SENT,
966 /** Customary 32-bit type hack. */
967 GIMHVDEBUGREPLY_32BIT_HACK = 0x7fffffff
968} GIMHVDEBUGREPLY;
969AssertCompileSize(GIMHVDEBUGREPLY, sizeof(uint32_t));
970
971/**
972 * GIM Hyper-V VM instance data.
973 * Changes to this must checked against the padding of the gim union in VM!
974 */
975typedef struct GIMHV
976{
977 /** @name Primary MSRs.
978 * @{ */
979 /** Guest OS identity MSR. */
980 uint64_t u64GuestOsIdMsr;
981 /** Hypercall MSR. */
982 uint64_t u64HypercallMsr;
983 /** Reference TSC page MSR. */
984 uint64_t u64TscPageMsr;
985 /** @} */
986
987 /** @name CPUID features.
988 * @{ */
989 /** Basic features. */
990 uint32_t uBaseFeat;
991 /** Partition flags. */
992 uint32_t uPartFlags;
993 /** Power management. */
994 uint32_t uPowMgmtFeat;
995 /** Miscellaneous. */
996 uint32_t uMiscFeat;
997 /** Hypervisor hints to the guest. */
998 uint32_t uHyperHints;
999 /** Hypervisor capabilities. */
1000 uint32_t uHyperCaps;
1001 /** @} */
1002
1003 /** @name Guest Crash MSRs.
1004 * @{
1005 */
1006 /** Guest crash control MSR. */
1007 uint64_t uCrashCtlMsr;
1008 /** Guest crash parameter 0 MSR. */
1009 uint64_t uCrashP0Msr;
1010 /** Guest crash parameter 1 MSR. */
1011 uint64_t uCrashP1Msr;
1012 /** Guest crash parameter 2 MSR. */
1013 uint64_t uCrashP2Msr;
1014 /** Guest crash parameter 3 MSR. */
1015 uint64_t uCrashP3Msr;
1016 /** Guest crash parameter 4 MSR. */
1017 uint64_t uCrashP4Msr;
1018 /** @} */
1019
1020 /** @name Time management.
1021 * @{ */
1022 /** Per-VM R0 Spinlock for protecting EMT writes to the TSC page. */
1023 RTSPINLOCK hSpinlockR0;
1024#if HC_ARCH_BITS == 32
1025 uint32_t u32Alignment1;
1026#endif
1027 /** The TSC frequency (in HZ) reported to the guest. */
1028 uint64_t cTscTicksPerSecond;
1029 /** @} */
1030
1031 /** @name Hypercalls. */
1032 /* @{ */
1033 /** Guest address of the hypercall input parameter page. */
1034 RTGCPHYS GCPhysHypercallIn;
1035 /** Guest address of the hypercall output parameter page. */
1036 RTGCPHYS GCPhysHypercallOut;
1037 /** Pointer to the hypercall input parameter page - R3. */
1038 R3PTRTYPE(uint8_t *) pbHypercallIn;
1039 /** Pointer to the hypercall output parameter page - R3. */
1040 R3PTRTYPE(uint8_t *) pbHypercallOut;
1041 /** @} */
1042
1043 /** @name Guest debugging.
1044 * @{ */
1045 /** Whether we're posing as the Microsoft vendor. */
1046 bool fIsVendorMsHv;
1047 /** Whether we're posing as the Microsoft virtualization service. */
1048 bool fIsInterfaceVs;
1049 /** Whether debugging support is enabled. */
1050 bool fDbgEnabled;
1051 /** Whether we should suggest a hypercall-based debug interface to the guest. */
1052 bool fDbgHypercallInterface;
1053 bool afAlignment0[4];
1054 /** The action to take while sending replies. */
1055 GIMHVDEBUGREPLY enmDbgReply;
1056 /** The IP address chosen by/assigned to the guest. */
1057 RTNETADDRIPV4 DbgGuestIp4Addr;
1058 /** Transaction ID for the BOOTP+DHCP sequence. */
1059 uint32_t uDbgBootpXId;
1060 /** The source UDP port used by the guest while sending debug packets. */
1061 uint16_t uUdpGuestSrcPort;
1062 /** The destination UDP port used by the guest while sending debug packets. */
1063 uint16_t uUdpGuestDstPort;
1064 /** Debug send buffer MSR. */
1065 uint64_t uDbgSendBufferMsr;
1066 /** Debug receive buffer MSR. */
1067 uint64_t uDbgRecvBufferMsr;
1068 /** Debug pending buffer MSR. */
1069 uint64_t uDbgPendingBufferMsr;
1070 /** Debug status MSR. */
1071 uint64_t uDbgStatusMsr;
1072 /** Intermediate debug I/O buffer. */
1073 R3PTRTYPE(void *) pvDbgBuffer;
1074 R3PTRTYPE(void *) pvAlignment0;
1075 /** @} */
1076
1077 /** Array of MMIO2 regions. */
1078 GIMMMIO2REGION aMmio2Regions[GIM_HV_REGION_IDX_MAX + 1];
1079} GIMHV;
1080/** Pointer to per-VM GIM Hyper-V instance data. */
1081typedef GIMHV *PGIMHV;
1082/** Pointer to const per-VM GIM Hyper-V instance data. */
1083typedef GIMHV const *PCGIMHV;
1084AssertCompileMemberAlignment(GIMHV, aMmio2Regions, 8);
1085AssertCompileMemberAlignment(GIMHV, hSpinlockR0, sizeof(uintptr_t));
1086
1087/**
1088 * GIM Hyper-V VCPU instance data.
1089 * Changes to this must checked against the padding of the gim union in VMCPU!
1090 */
1091typedef struct GIMHVCPU
1092{
1093 /** @name Synthetic interrupt MSRs.
1094 * @{ */
1095 /** Synthetic interrupt message page MSR. */
1096 uint64_t uSimpMsr;
1097 /** Interrupt source 2 MSR. */
1098 uint64_t uSint2Msr;
1099 /** @} */
1100} GIMHVCPU;
1101/** Pointer to per-VCPU GIM Hyper-V instance data. */
1102typedef GIMHVCPU *PGIMHVCPU;
1103/** Pointer to const per-VCPU GIM Hyper-V instance data. */
1104typedef GIMHVCPU const *PCGIMHVCPU;
1105
1106
1107RT_C_DECLS_BEGIN
1108
1109#ifdef IN_RING0
1110VMMR0_INT_DECL(int) gimR0HvInitVM(PVM pVM);
1111VMMR0_INT_DECL(int) gimR0HvTermVM(PVM pVM);
1112VMMR0_INT_DECL(int) gimR0HvUpdateParavirtTsc(PVM pVM, uint64_t u64Offset);
1113#endif /* IN_RING0 */
1114
1115#ifdef IN_RING3
1116VMMR3_INT_DECL(int) gimR3HvInit(PVM pVM, PCFGMNODE pGimCfg);
1117VMMR3_INT_DECL(int) gimR3HvInitCompleted(PVM pVM);
1118VMMR3_INT_DECL(int) gimR3HvTerm(PVM pVM);
1119VMMR3_INT_DECL(void) gimR3HvRelocate(PVM pVM, RTGCINTPTR offDelta);
1120VMMR3_INT_DECL(void) gimR3HvReset(PVM pVM);
1121VMMR3_INT_DECL(PGIMMMIO2REGION) gimR3HvGetMmio2Regions(PVM pVM, uint32_t *pcRegions);
1122VMMR3_INT_DECL(int) gimR3HvSave(PVM pVM, PSSMHANDLE pSSM);
1123VMMR3_INT_DECL(int) gimR3HvLoad(PVM pVM, PSSMHANDLE pSSM, uint32_t uSSMVersion);
1124VMMR3_INT_DECL(int) gimR3HvGetDebugSetup(PVM pVM, PGIMDEBUGSETUP pDbgSetup);
1125
1126VMMR3_INT_DECL(int) gimR3HvDisableTscPage(PVM pVM);
1127VMMR3_INT_DECL(int) gimR3HvEnableTscPage(PVM pVM, RTGCPHYS GCPhysTscPage, bool fUseThisTscSeq, uint32_t uTscSeq);
1128VMMR3_INT_DECL(int) gimR3HvDisableHypercallPage(PVM pVM);
1129VMMR3_INT_DECL(int) gimR3HvEnableHypercallPage(PVM pVM, RTGCPHYS GCPhysHypercallPage);
1130
1131VMMR3_INT_DECL(int) gimR3HvHypercallPostDebugData(PVM pVM, int *prcHv);
1132VMMR3_INT_DECL(int) gimR3HvHypercallRetrieveDebugData(PVM pVM, int *prcHv);
1133VMMR3_INT_DECL(int) gimR3HvDebugWrite(PVM pVM, void *pvData, uint32_t cbWrite, uint32_t *pcbWritten, bool fUdpPkt);
1134VMMR3_INT_DECL(int) gimR3HvDebugRead(PVM pVM, void *pvBuf, uint32_t cbBuf, uint32_t cbRead, uint32_t *pcbRead,
1135 uint32_t cMsTimeout, bool fUdpPkt);
1136#endif /* IN_RING3 */
1137
1138VMM_INT_DECL(bool) gimHvIsParavirtTscEnabled(PVM pVM);
1139VMM_INT_DECL(bool) gimHvAreHypercallsEnabled(PVMCPU pVCpu);
1140VMM_INT_DECL(bool) gimHvShouldTrapXcptUD(PVMCPU pVCpu);
1141VMM_INT_DECL(int) gimHvXcptUD(PVMCPU pVCpu, PCPUMCTX pCtx, PDISCPUSTATE pDis);
1142VMM_INT_DECL(int) gimHvHypercall(PVMCPU pVCpu, PCPUMCTX pCtx);
1143VMM_INT_DECL(VBOXSTRICTRC) gimHvReadMsr(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue);
1144VMM_INT_DECL(VBOXSTRICTRC) gimHvWriteMsr(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uRawValue);
1145
1146RT_C_DECLS_END
1147
1148#endif
1149
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