VirtualBox

source: vbox/trunk/src/VBox/VMM/include/GIMHvInternal.h@ 72126

Last change on this file since 72126 was 71265, checked in by vboxsync, 7 years ago

VMM/GIMHv: Added some newer Hyper-V paravirt. CPUID feature bits.
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1/* $Id: GIMHvInternal.h 71265 2018-03-08 05:31:35Z vboxsync $ */
2/** @file
3 * GIM - Hyper-V, Internal header file.
4 */
5
6/*
7 * Copyright (C) 2014-2017 Oracle Corporation
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 */
17
18#ifndef ___GIMHvInternal_h
19#define ___GIMHvInternal_h
20
21#include <VBox/vmm/gim.h>
22#include <VBox/vmm/cpum.h>
23
24#include <iprt/net.h>
25
26/** @name Hyper-V base feature identification.
27 * Features based on current partition privileges (per-VM).
28 * @{
29 */
30/** Virtual processor runtime MSR available. */
31#define GIM_HV_BASE_FEAT_VP_RUNTIME_MSR RT_BIT(0)
32/** Partition reference counter MSR available. */
33#define GIM_HV_BASE_FEAT_PART_TIME_REF_COUNT_MSR RT_BIT(1)
34/** Basic Synthetic Interrupt Controller MSRs available. */
35#define GIM_HV_BASE_FEAT_BASIC_SYNIC_MSRS RT_BIT(2)
36/** Synthetic Timer MSRs available. */
37#define GIM_HV_BASE_FEAT_STIMER_MSRS RT_BIT(3)
38/** APIC access MSRs (EOI, ICR, TPR) available. */
39#define GIM_HV_BASE_FEAT_APIC_ACCESS_MSRS RT_BIT(4)
40/** Hypercall MSRs available. */
41#define GIM_HV_BASE_FEAT_HYPERCALL_MSRS RT_BIT(5)
42/** Access to VCPU index MSR available. */
43#define GIM_HV_BASE_FEAT_VP_ID_MSR RT_BIT(6)
44/** Virtual system reset MSR available. */
45#define GIM_HV_BASE_FEAT_VIRT_SYS_RESET_MSR RT_BIT(7)
46/** Statistic pages MSRs available. */
47#define GIM_HV_BASE_FEAT_STAT_PAGES_MSR RT_BIT(8)
48/** Paritition reference TSC MSR available. */
49#define GIM_HV_BASE_FEAT_PART_REF_TSC_MSR RT_BIT(9)
50/** Virtual guest idle state MSR available. */
51#define GIM_HV_BASE_FEAT_GUEST_IDLE_STATE_MSR RT_BIT(10)
52/** Timer frequency MSRs (TSC and APIC) available. */
53#define GIM_HV_BASE_FEAT_TIMER_FREQ_MSRS RT_BIT(11)
54/** Debug MSRs available. */
55#define GIM_HV_BASE_FEAT_DEBUG_MSRS RT_BIT(12)
56/** @} */
57
58/** @name Hyper-V partition-creation feature identification.
59 * Indicates flags specified during partition creation.
60 * @{
61 */
62/** Create partitions. */
63#define GIM_HV_PART_FLAGS_CREATE_PART RT_BIT(0)
64/** Access partition Id. */
65#define GIM_HV_PART_FLAGS_ACCESS_PART_ID RT_BIT(1)
66/** Access memory pool. */
67#define GIM_HV_PART_FLAGS_ACCESS_MEMORY_POOL RT_BIT(2)
68/** Adjust message buffers. */
69#define GIM_HV_PART_FLAGS_ADJUST_MSG_BUFFERS RT_BIT(3)
70/** Post messages. */
71#define GIM_HV_PART_FLAGS_POST_MSGS RT_BIT(4)
72/** Signal events. */
73#define GIM_HV_PART_FLAGS_SIGNAL_EVENTS RT_BIT(5)
74/** Create port. */
75#define GIM_HV_PART_FLAGS_CREATE_PORT RT_BIT(6)
76/** Connect port. */
77#define GIM_HV_PART_FLAGS_CONNECT_PORT RT_BIT(7)
78/** Access statistics. */
79#define GIM_HV_PART_FLAGS_ACCESS_STATS RT_BIT(8)
80/** Debugging.*/
81#define GIM_HV_PART_FLAGS_DEBUGGING RT_BIT(11)
82/** CPU management. */
83#define GIM_HV_PART_FLAGS_CPU_MGMT RT_BIT(12)
84/** CPU profiler. */
85#define GIM_HV_PART_FLAGS_CPU_PROFILER RT_BIT(13)
86/** Enable expanded stack walking. */
87#define GIM_HV_PART_FLAGS_EXPANDED_STACK_WALK RT_BIT(14)
88/** Access VSM. */
89#define GIM_HV_PART_FLAGS_ACCESS_VSM RT_BIT(16)
90/** Access VP registers. */
91#define GIM_HV_PART_FLAGS_ACCESS_VP_REGS RT_BIT(17)
92/** Enable extended hypercalls. */
93#define GIM_HV_PART_FLAGS_EXTENDED_HYPERCALLS RT_BIT(20)
94/** Start virtual processor. */
95#define GIM_HV_PART_FLAGS_START_VP RT_BIT(21)
96/** @} */
97
98/** @name Hyper-V power management feature identification.
99 * @{
100 */
101/** Maximum CPU power state C0. */
102#define GIM_HV_PM_MAX_CPU_POWER_STATE_C0 RT_BIT(0)
103/** Maximum CPU power state C1. */
104#define GIM_HV_PM_MAX_CPU_POWER_STATE_C1 RT_BIT(1)
105/** Maximum CPU power state C2. */
106#define GIM_HV_PM_MAX_CPU_POWER_STATE_C2 RT_BIT(2)
107/** Maximum CPU power state C3. */
108#define GIM_HV_PM_MAX_CPU_POWER_STATE_C3 RT_BIT(3)
109/** HPET is required to enter C3 power state. */
110#define GIM_HV_PM_HPET_REQD_FOR_C3 RT_BIT(4)
111/** @} */
112
113/** @name Hyper-V miscellaneous feature identification.
114 * Miscellaneous features available for the current partition.
115 * @{
116 */
117/** MWAIT instruction available. */
118#define GIM_HV_MISC_FEAT_MWAIT RT_BIT(0)
119/** Guest debugging support available. */
120#define GIM_HV_MISC_FEAT_GUEST_DEBUGGING RT_BIT(1)
121/** Performance monitor support is available. */
122#define GIM_HV_MISC_FEAT_PERF_MON RT_BIT(2)
123/** Support for physical CPU dynamic partitioning events. */
124#define GIM_HV_MISC_FEAT_PCPU_DYN_PART_EVENT RT_BIT(3)
125/** Support for passing hypercall input parameter block via XMM registers. */
126#define GIM_HV_MISC_FEAT_XMM_HYPERCALL_INPUT RT_BIT(4)
127/** Support for virtual guest idle state. */
128#define GIM_HV_MISC_FEAT_GUEST_IDLE_STATE RT_BIT(5)
129/** Support for hypervisor sleep state. */
130#define GIM_HV_MISC_FEAT_HYPERVISOR_SLEEP_STATE RT_BIT(6)
131/** Support for querying NUMA distances. */
132#define GIM_HV_MISC_FEAT_QUERY_NUMA_DISTANCE RT_BIT(7)
133/** Support for determining timer frequencies. */
134#define GIM_HV_MISC_FEAT_TIMER_FREQ RT_BIT(8)
135/** Support for injecting synthetic machine checks. */
136#define GIM_HV_MISC_FEAT_INJECT_SYNMC_XCPT RT_BIT(9)
137/** Support for guest crash MSRs. */
138#define GIM_HV_MISC_FEAT_GUEST_CRASH_MSRS RT_BIT(10)
139/** Support for debug MSRs. */
140#define GIM_HV_MISC_FEAT_DEBUG_MSRS RT_BIT(11)
141/** Npiep1 Available */ /** @todo What the heck is this? */
142#define GIM_HV_MISC_FEAT_NPIEP1 RT_BIT(12)
143/** Disable hypervisor available. */
144#define GIM_HV_MISC_FEAT_DISABLE_HYPERVISOR RT_BIT(13)
145/** Extended GVA ranges for FlushVirtualAddressList available. */
146#define GIM_HV_MISC_FEAT_EXT_GVA_RANGE_FOR_FLUSH_VA_LIST RT_BIT(14)
147/** Support for returning hypercall output via XMM registers. */
148#define GIM_HV_MISC_FEAT_HYPERCALL_OUTPUT_XMM RT_BIT(15)
149/** Synthetic interrupt source polling mode available. */
150#define GIM_HV_MISC_FEAT_SINT_POLLING_MODE RT_BIT(17)
151/** Hypercall MSR lock available. */
152#define GIM_HV_MISC_FEAT_HYPERCALL_MSR_LOCK RT_BIT(18)
153/** Use direct synthetic MSRs. */
154#define GIM_HV_MISC_FEAT_USE_DIRECT_SYNTH_MSRS RT_BIT(19)
155/** @} */
156
157/** @name Hyper-V implementation recommendations.
158 * Recommendations from the hypervisor for the guest for optimal performance.
159 * @{
160 */
161/** Use hypercall for address space switches rather than MOV CR3. */
162#define GIM_HV_HINT_HYPERCALL_FOR_PROCESS_SWITCH RT_BIT(0)
163/** Use hypercall for local TLB flushes rather than INVLPG/MOV CR3. */
164#define GIM_HV_HINT_HYPERCALL_FOR_TLB_FLUSH RT_BIT(1)
165/** Use hypercall for inter-CPU TLB flushes rather than IPIs. */
166#define GIM_HV_HINT_HYPERCALL_FOR_TLB_SHOOTDOWN RT_BIT(2)
167/** Use MSRs for APIC access (EOI, ICR, TPR) rather than MMIO. */
168#define GIM_HV_HINT_MSR_FOR_APIC_ACCESS RT_BIT(3)
169/** Use hypervisor provided MSR for a system reset. */
170#define GIM_HV_HINT_MSR_FOR_SYS_RESET RT_BIT(4)
171/** Relax timer-related checks (watchdogs/deadman timeouts) that rely on
172 * timely deliver of external interrupts. */
173#define GIM_HV_HINT_RELAX_TIME_CHECKS RT_BIT(5)
174/** Recommend using DMA remapping. */
175#define GIM_HV_HINT_DMA_REMAPPING RT_BIT(6)
176/** Recommend using interrupt remapping. */
177#define GIM_HV_HINT_INTERRUPT_REMAPPING RT_BIT(7)
178/** Recommend using X2APIC MSRs rather than MMIO. */
179#define GIM_HV_HINT_X2APIC_MSRS RT_BIT(8)
180/** Recommend deprecating Auto EOI (end of interrupt). */
181#define GIM_HV_HINT_DEPRECATE_AUTO_EOI RT_BIT(9)
182/** Recommend using SyntheticClusterIpi hypercall. */
183#define GIM_HV_HINT_SYNTH_CLUSTER_IPI_HYPERCALL RT_BIT(10)
184/** Recommend using newer ExProcessMasks interface. */
185#define GIM_HV_HINT_EX_PROC_MASKS_INTERFACE RT_BIT(11)
186/** Indicate that Hyper-V is nested within a Hyper-V partition. */
187#define GIM_HV_HINT_NESTED_HYPERV RT_BIT(12)
188/** Recommend using INT for MBEC system calls. */
189#define GIM_HV_HINT_INT_FOR_MBEC_SYSCALLS RT_BIT(13)
190/** Recommend using enlightened VMCS interfacea and nested enlightenments. */
191#define GIM_HV_HINT_NESTED_ENLIGHTENED_VMCS_INTERFACE RT_BIT(14)
192/** @} */
193
194
195/** @name Hyper-V implementation hardware features.
196 * Which hardware features are in use by the hypervisor.
197 * @{
198 */
199/** APIC overlay is used. */
200#define GIM_HV_HOST_FEAT_AVIC RT_BIT(0)
201/** MSR bitmaps is used. */
202#define GIM_HV_HOST_FEAT_MSR_BITMAP RT_BIT(1)
203/** Architectural performance counter supported. */
204#define GIM_HV_HOST_FEAT_PERF_COUNTER RT_BIT(2)
205/** Nested paging is used. */
206#define GIM_HV_HOST_FEAT_NESTED_PAGING RT_BIT(3)
207/** DMA remapping is used. */
208#define GIM_HV_HOST_FEAT_DMA_REMAPPING RT_BIT(4)
209/** Interrupt remapping is used. */
210#define GIM_HV_HOST_FEAT_INTERRUPT_REMAPPING RT_BIT(5)
211/** Memory patrol scrubber is present. */
212#define GIM_HV_HOST_FEAT_MEM_PATROL_SCRUBBER RT_BIT(6)
213/** DMA protection is in use. */
214#define GIM_HV_HOST_FEAT_DMA_PROT_IN_USE RT_BIT(7)
215/** HPET is requested. */
216#define GIM_HV_HOST_FEAT_HPET_REQUESTED RT_BIT(8)
217/** Synthetic timers are volatile. */
218#define GIM_HV_HOST_FEAT_STIMER_VOLATILE RT_BIT(9)
219/** @} */
220
221
222/** @name Hyper-V MSRs.
223 * @{
224 */
225/** Start of range 0. */
226#define MSR_GIM_HV_RANGE0_START UINT32_C(0x40000000)
227/** Guest OS identification (R/W) */
228#define MSR_GIM_HV_GUEST_OS_ID UINT32_C(0x40000000)
229/** Enable hypercall interface (R/W) */
230#define MSR_GIM_HV_HYPERCALL UINT32_C(0x40000001)
231/** Virtual processor's (VCPU) index (R) */
232#define MSR_GIM_HV_VP_INDEX UINT32_C(0x40000002)
233/** Reset operation (R/W) */
234#define MSR_GIM_HV_RESET UINT32_C(0x40000003)
235/** End of range 0. */
236#define MSR_GIM_HV_RANGE0_END MSR_GIM_HV_RESET
237
238/** Start of range 1. */
239#define MSR_GIM_HV_RANGE1_START UINT32_C(0x40000010)
240/** Virtual processor's (VCPU) runtime (R) */
241#define MSR_GIM_HV_VP_RUNTIME UINT32_C(0x40000010)
242/** End of range 1. */
243#define MSR_GIM_HV_RANGE1_END MSR_GIM_HV_VP_RUNTIME
244
245/** Start of range 2. */
246#define MSR_GIM_HV_RANGE2_START UINT32_C(0x40000020)
247/** Per-VM reference counter (R) */
248#define MSR_GIM_HV_TIME_REF_COUNT UINT32_C(0x40000020)
249/** Per-VM TSC page (R/W) */
250#define MSR_GIM_HV_REF_TSC UINT32_C(0x40000021)
251/** Frequency of TSC in Hz as reported by the hypervisor (R) */
252#define MSR_GIM_HV_TSC_FREQ UINT32_C(0x40000022)
253/** Frequency of LAPIC in Hz as reported by the hypervisor (R) */
254#define MSR_GIM_HV_APIC_FREQ UINT32_C(0x40000023)
255/** End of range 2. */
256#define MSR_GIM_HV_RANGE2_END MSR_GIM_HV_APIC_FREQ
257
258/** Start of range 3. */
259#define MSR_GIM_HV_RANGE3_START UINT32_C(0x40000070)
260/** Access to APIC EOI (End-Of-Interrupt) register (W) */
261#define MSR_GIM_HV_EOI UINT32_C(0x40000070)
262/** Access to APIC ICR (Interrupt Command) register (R/W) */
263#define MSR_GIM_HV_ICR UINT32_C(0x40000071)
264/** Access to APIC TPR (Task Priority) register (R/W) */
265#define MSR_GIM_HV_TPR UINT32_C(0x40000072)
266/** Enables lazy EOI processing (R/W) */
267#define MSR_GIM_HV_APIC_ASSIST_PAGE UINT32_C(0x40000073)
268/** End of range 3. */
269#define MSR_GIM_HV_RANGE3_END MSR_GIM_HV_APIC_ASSIST_PAGE
270
271/** Start of range 4. */
272#define MSR_GIM_HV_RANGE4_START UINT32_C(0x40000080)
273/** Control behaviour of synthetic interrupt controller (R/W) */
274#define MSR_GIM_HV_SCONTROL UINT32_C(0x40000080)
275/** Synthetic interrupt controller version (R) */
276#define MSR_GIM_HV_SVERSION UINT32_C(0x40000081)
277/** Base address of synthetic interrupt event flag (R/W) */
278#define MSR_GIM_HV_SIEFP UINT32_C(0x40000082)
279/** Base address of synthetic interrupt message page (R/W) */
280#define MSR_GIM_HV_SIMP UINT32_C(0x40000083)
281/** End-Of-Message in synthetic interrupt parameter page (W) */
282#define MSR_GIM_HV_EOM UINT32_C(0x40000084)
283/** End of range 4. */
284#define MSR_GIM_HV_RANGE4_END MSR_GIM_HV_EOM
285
286/** Start of range 5. */
287#define MSR_GIM_HV_RANGE5_START UINT32_C(0x40000090)
288/** Configures synthetic interrupt source 0 (R/W) */
289#define MSR_GIM_HV_SINT0 UINT32_C(0x40000090)
290/** Configures synthetic interrupt source 1 (R/W) */
291#define MSR_GIM_HV_SINT1 UINT32_C(0x40000091)
292/** Configures synthetic interrupt source 2 (R/W) */
293#define MSR_GIM_HV_SINT2 UINT32_C(0x40000092)
294/** Configures synthetic interrupt source 3 (R/W) */
295#define MSR_GIM_HV_SINT3 UINT32_C(0x40000093)
296/** Configures synthetic interrupt source 4 (R/W) */
297#define MSR_GIM_HV_SINT4 UINT32_C(0x40000094)
298/** Configures synthetic interrupt source 5 (R/W) */
299#define MSR_GIM_HV_SINT5 UINT32_C(0x40000095)
300/** Configures synthetic interrupt source 6 (R/W) */
301#define MSR_GIM_HV_SINT6 UINT32_C(0x40000096)
302/** Configures synthetic interrupt source 7 (R/W) */
303#define MSR_GIM_HV_SINT7 UINT32_C(0x40000097)
304/** Configures synthetic interrupt source 8 (R/W) */
305#define MSR_GIM_HV_SINT8 UINT32_C(0x40000098)
306/** Configures synthetic interrupt source 9 (R/W) */
307#define MSR_GIM_HV_SINT9 UINT32_C(0x40000099)
308/** Configures synthetic interrupt source 10 (R/W) */
309#define MSR_GIM_HV_SINT10 UINT32_C(0x4000009A)
310/** Configures synthetic interrupt source 11 (R/W) */
311#define MSR_GIM_HV_SINT11 UINT32_C(0x4000009B)
312/** Configures synthetic interrupt source 12 (R/W) */
313#define MSR_GIM_HV_SINT12 UINT32_C(0x4000009C)
314/** Configures synthetic interrupt source 13 (R/W) */
315#define MSR_GIM_HV_SINT13 UINT32_C(0x4000009D)
316/** Configures synthetic interrupt source 14 (R/W) */
317#define MSR_GIM_HV_SINT14 UINT32_C(0x4000009E)
318/** Configures synthetic interrupt source 15 (R/W) */
319#define MSR_GIM_HV_SINT15 UINT32_C(0x4000009F)
320/** End of range 5. */
321#define MSR_GIM_HV_RANGE5_END MSR_GIM_HV_SINT15
322
323/** Start of range 6. */
324#define MSR_GIM_HV_RANGE6_START UINT32_C(0x400000B0)
325/** Configures register for synthetic timer 0 (R/W) */
326#define MSR_GIM_HV_STIMER0_CONFIG UINT32_C(0x400000B0)
327/** Expiration time or period for synthetic timer 0 (R/W) */
328#define MSR_GIM_HV_STIMER0_COUNT UINT32_C(0x400000B1)
329/** Configures register for synthetic timer 1 (R/W) */
330#define MSR_GIM_HV_STIMER1_CONFIG UINT32_C(0x400000B2)
331/** Expiration time or period for synthetic timer 1 (R/W) */
332#define MSR_GIM_HV_STIMER1_COUNT UINT32_C(0x400000B3)
333/** Configures register for synthetic timer 2 (R/W) */
334#define MSR_GIM_HV_STIMER2_CONFIG UINT32_C(0x400000B4)
335/** Expiration time or period for synthetic timer 2 (R/W) */
336#define MSR_GIM_HV_STIMER2_COUNT UINT32_C(0x400000B5)
337/** Configures register for synthetic timer 3 (R/W) */
338#define MSR_GIM_HV_STIMER3_CONFIG UINT32_C(0x400000B6)
339/** Expiration time or period for synthetic timer 3 (R/W) */
340#define MSR_GIM_HV_STIMER3_COUNT UINT32_C(0x400000B7)
341/** End of range 6. */
342#define MSR_GIM_HV_RANGE6_END MSR_GIM_HV_STIMER3_COUNT
343
344/** Start of range 7. */
345#define MSR_GIM_HV_RANGE7_START UINT32_C(0x400000C1)
346/** Trigger to transition to power state C1 (R) */
347#define MSR_GIM_HV_POWER_STATE_TRIGGER_C1 UINT32_C(0x400000C1)
348/** Trigger to transition to power state C2 (R) */
349#define MSR_GIM_HV_POWER_STATE_TRIGGER_C2 UINT32_C(0x400000C2)
350/** Trigger to transition to power state C3 (R) */
351#define MSR_GIM_HV_POWER_STATE_TRIGGER_C3 UINT32_C(0x400000C3)
352/** End of range 7. */
353#define MSR_GIM_HV_RANGE7_END MSR_GIM_HV_POWER_STATE_TRIGGER_C3
354
355/** Start of range 8. */
356#define MSR_GIM_HV_RANGE8_START UINT32_C(0x400000D1)
357/** Configure the recipe for power state transitions to C1 (R/W) */
358#define MSR_GIM_HV_POWER_STATE_CONFIG_C1 UINT32_C(0x400000D1)
359/** Configure the recipe for power state transitions to C2 (R/W) */
360#define MSR_GIM_HV_POWER_STATE_CONFIG_C2 UINT32_C(0x400000D2)
361/** Configure the recipe for power state transitions to C3 (R/W) */
362#define MSR_GIM_HV_POWER_STATE_CONFIG_C3 UINT32_C(0x400000D3)
363/** End of range 8. */
364#define MSR_GIM_HV_RANGE8_END MSR_GIM_HV_POWER_STATE_CONFIG_C3
365
366/** Start of range 9. */
367#define MSR_GIM_HV_RANGE9_START UINT32_C(0x400000E0)
368/** Map the guest's retail partition stats page (R/W) */
369#define MSR_GIM_HV_STATS_PART_RETAIL_PAGE UINT32_C(0x400000E0)
370/** Map the guest's internal partition stats page (R/W) */
371#define MSR_GIM_HV_STATS_PART_INTERNAL_PAGE UINT32_C(0x400000E1)
372/** Map the guest's retail VP stats page (R/W) */
373#define MSR_GIM_HV_STATS_VP_RETAIL_PAGE UINT32_C(0x400000E2)
374/** Map the guest's internal VP stats page (R/W) */
375#define MSR_GIM_HV_STATS_VP_INTERNAL_PAGE UINT32_C(0x400000E3)
376/** End of range 9. */
377#define MSR_GIM_HV_RANGE9_END MSR_GIM_HV_STATS_VP_INTERNAL_PAGE
378
379/** Start of range 10. */
380#define MSR_GIM_HV_RANGE10_START UINT32_C(0x400000F0)
381/** Trigger the guest's transition to idle power state (R) */
382#define MSR_GIM_HV_GUEST_IDLE UINT32_C(0x400000F0)
383/** Synthetic debug control. */
384#define MSR_GIM_HV_SYNTH_DEBUG_CONTROL UINT32_C(0x400000F1)
385/** Synthetic debug status. */
386#define MSR_GIM_HV_SYNTH_DEBUG_STATUS UINT32_C(0x400000F2)
387/** Synthetic debug send buffer. */
388#define MSR_GIM_HV_SYNTH_DEBUG_SEND_BUFFER UINT32_C(0x400000F3)
389/** Synthetic debug receive buffer. */
390#define MSR_GIM_HV_SYNTH_DEBUG_RECEIVE_BUFFER UINT32_C(0x400000F4)
391/** Synthetic debug pending buffer. */
392#define MSR_GIM_HV_SYNTH_DEBUG_PENDING_BUFFER UINT32_C(0x400000F5)
393/** End of range 10. */
394#define MSR_GIM_HV_RANGE10_END MSR_GIM_HV_SYNTH_DEBUG_PENDING_BUFFER
395
396/** Start of range 11. */
397#define MSR_GIM_HV_RANGE11_START UINT32_C(0x400000FF)
398/** Undocumented debug options MSR. */
399#define MSR_GIM_HV_DEBUG_OPTIONS_MSR UINT32_C(0x400000FF)
400/** End of range 11. */
401#define MSR_GIM_HV_RANGE11_END MSR_GIM_HV_DEBUG_OPTIONS_MSR
402
403/** Start of range 12. */
404#define MSR_GIM_HV_RANGE12_START UINT32_C(0x40000100)
405/** Guest crash MSR 0. */
406#define MSR_GIM_HV_CRASH_P0 UINT32_C(0x40000100)
407/** Guest crash MSR 1. */
408#define MSR_GIM_HV_CRASH_P1 UINT32_C(0x40000101)
409/** Guest crash MSR 2. */
410#define MSR_GIM_HV_CRASH_P2 UINT32_C(0x40000102)
411/** Guest crash MSR 3. */
412#define MSR_GIM_HV_CRASH_P3 UINT32_C(0x40000103)
413/** Guest crash MSR 4. */
414#define MSR_GIM_HV_CRASH_P4 UINT32_C(0x40000104)
415/** Guest crash control. */
416#define MSR_GIM_HV_CRASH_CTL UINT32_C(0x40000105)
417/** End of range 12. */
418#define MSR_GIM_HV_RANGE12_END MSR_GIM_HV_CRASH_CTL
419/** @} */
420
421AssertCompile(MSR_GIM_HV_RANGE0_START <= MSR_GIM_HV_RANGE0_END);
422AssertCompile(MSR_GIM_HV_RANGE1_START <= MSR_GIM_HV_RANGE1_END);
423AssertCompile(MSR_GIM_HV_RANGE2_START <= MSR_GIM_HV_RANGE2_END);
424AssertCompile(MSR_GIM_HV_RANGE3_START <= MSR_GIM_HV_RANGE3_END);
425AssertCompile(MSR_GIM_HV_RANGE4_START <= MSR_GIM_HV_RANGE4_END);
426AssertCompile(MSR_GIM_HV_RANGE5_START <= MSR_GIM_HV_RANGE5_END);
427AssertCompile(MSR_GIM_HV_RANGE6_START <= MSR_GIM_HV_RANGE6_END);
428AssertCompile(MSR_GIM_HV_RANGE7_START <= MSR_GIM_HV_RANGE7_END);
429AssertCompile(MSR_GIM_HV_RANGE8_START <= MSR_GIM_HV_RANGE8_END);
430AssertCompile(MSR_GIM_HV_RANGE9_START <= MSR_GIM_HV_RANGE9_END);
431AssertCompile(MSR_GIM_HV_RANGE10_START <= MSR_GIM_HV_RANGE10_END);
432AssertCompile(MSR_GIM_HV_RANGE11_START <= MSR_GIM_HV_RANGE11_END);
433
434/** @name Hyper-V MSR - Reset (MSR_GIM_HV_RESET).
435 * @{
436 */
437/** The reset enable mask. */
438#define MSR_GIM_HV_RESET_ENABLE RT_BIT_64(0)
439/** Whether the reset MSR is enabled. */
440#define MSR_GIM_HV_RESET_IS_ENABLED(a) RT_BOOL((a) & MSR_GIM_HV_RESET_ENABLE)
441/** @} */
442
443/** @name Hyper-V MSR - Hypercall (MSR_GIM_HV_HYPERCALL).
444 * @{
445 */
446/** Guest-physical page frame number of the hypercall-page. */
447#define MSR_GIM_HV_HYPERCALL_GUEST_PFN(a) ((a) >> 12)
448/** The hypercall enable mask. */
449#define MSR_GIM_HV_HYPERCALL_PAGE_ENABLE RT_BIT_64(0)
450/** Whether the hypercall-page is enabled or not. */
451#define MSR_GIM_HV_HYPERCALL_PAGE_IS_ENABLED(a) RT_BOOL((a) & MSR_GIM_HV_HYPERCALL_PAGE_ENABLE)
452/** @} */
453
454/** @name Hyper-V MSR - Reference TSC (MSR_GIM_HV_REF_TSC).
455 * @{
456 */
457/** Guest-physical page frame number of the TSC-page. */
458#define MSR_GIM_HV_REF_TSC_GUEST_PFN(a) ((a) >> 12)
459/** The TSC-page enable mask. */
460#define MSR_GIM_HV_REF_TSC_ENABLE RT_BIT_64(0)
461/** Whether the TSC-page is enabled or not. */
462#define MSR_GIM_HV_REF_TSC_IS_ENABLED(a) RT_BOOL((a) & MSR_GIM_HV_REF_TSC_ENABLE)
463/** @} */
464
465/** @name Hyper-V MSR - Guest crash control (MSR_GIM_HV_CRASH_CTL).
466 * @{
467 */
468/** The Crash Control notify mask. */
469#define MSR_GIM_HV_CRASH_CTL_NOTIFY RT_BIT_64(63)
470/** @} */
471
472/** @name Hyper-V MSR - Guest OS ID (MSR_GIM_HV_GUEST_OS_ID).
473 * @{
474 */
475/** An open-source operating system. */
476#define MSR_GIM_HV_GUEST_OS_ID_IS_OPENSOURCE(a) RT_BOOL((a) & RT_BIT_64(63))
477/** Vendor ID. */
478#define MSR_GIM_HV_GUEST_OS_ID_VENDOR(a) (uint32_t)(((a) >> 48) & 0xfff)
479/** Guest OS variant, depending on the vendor ID. */
480#define MSR_GIM_HV_GUEST_OS_ID_OS_VARIANT(a) (uint32_t)(((a) >> 40) & 0xff)
481/** Guest OS major version. */
482#define MSR_GIM_HV_GUEST_OS_ID_MAJOR_VERSION(a) (uint32_t)(((a) >> 32) & 0xff)
483/** Guest OS minor version. */
484#define MSR_GIM_HV_GUEST_OS_ID_MINOR_VERSION(a) (uint32_t)(((a) >> 24) & 0xff)
485/** Guest OS service version (e.g. service pack number in case of Windows). */
486#define MSR_GIM_HV_GUEST_OS_ID_SERVICE_VERSION(a) (uint32_t)(((a) >> 16) & 0xff)
487/** Guest OS build number. */
488#define MSR_GIM_HV_GUEST_OS_ID_BUILD(a) (uint32_t)((a) & 0xffff)
489/** @} */
490
491/** @name Hyper-V MSR - APIC-assist page (MSR_GIM_HV_APIC_ASSIST_PAGE).
492 * @{
493 */
494/** Guest-physical page frame number of the APIC-assist page. */
495#define MSR_GIM_HV_APICASSIST_GUEST_PFN(a) ((a) >> 12)
496/** The APIC-assist page enable mask. */
497#define MSR_GIM_HV_APICASSIST_PAGE_ENABLE RT_BIT_64(0)
498/** Whether the APIC-assist page is enabled or not. */
499#define MSR_GIM_HV_APICASSIST_PAGE_IS_ENABLED(a) RT_BOOL((a) & MSR_GIM_HV_APICASSIST_PAGE_ENABLE)
500/** @} */
501
502/** @name Hyper-V MSR - Synthetic Interrupt Event Flags page
503 * (MSR_GIM_HV_SIEFP).
504 * @{
505 */
506/** Guest-physical page frame number of the APIC-assist page. */
507#define MSR_GIM_HV_SIEF_GUEST_PFN(a) ((a) >> 12)
508/** The SIEF enable mask. */
509#define MSR_GIM_HV_SIEF_PAGE_ENABLE RT_BIT_64(0)
510/** Whether the SIEF page is enabled or not. */
511#define MSR_GIM_HV_SIEF_PAGE_IS_ENABLED(a) RT_BOOL((a) & MSR_GIM_HV_SIEF_PAGE_ENABLE)
512/** @} */
513
514/** @name Hyper-V MSR - Synthetic Interrupt Control (MSR_GIM_HV_CONTROL).
515 * @{
516 */
517/** The SControl enable mask. */
518#define MSR_GIM_HV_SCONTROL_ENABLE RT_BIT_64(0)
519/** Whether SControl is enabled or not. */
520#define MSR_GIM_HV_SCONTROL_IS_ENABLED(a) RT_BOOL((a) & MSR_GIM_HV_SCONTROL_ENABLE)
521/** @} */
522
523/** @name Hyper-V MSR - Synthetic Timer Config (MSR_GIM_HV_STIMER_CONFIG).
524 * @{
525 */
526/** The Stimer enable mask. */
527#define MSR_GIM_HV_STIMER_ENABLE RT_BIT_64(0)
528/** Whether Stimer is enabled or not. */
529#define MSR_GIM_HV_STIMER_IS_ENABLED(a) RT_BOOL((a) & MSR_GIM_HV_STIMER_ENABLE)
530/** The Stimer periodic mask. */
531#define MSR_GIM_HV_STIMER_PERIODIC RT_BIT_64(1)
532/** Whether Stimer is enabled or not. */
533#define MSR_GIM_HV_STIMER_IS_PERIODIC(a) RT_BOOL((a) & MSR_GIM_HV_STIMER_PERIODIC)
534/** The Stimer lazy mask. */
535#define MSR_GIM_HV_STIMER_LAZY RT_BIT_64(2)
536/** Whether Stimer is enabled or not. */
537#define MSR_GIM_HV_STIMER_IS_LAZY(a) RT_BOOL((a) & MSR_GIM_HV_STIMER_LAZY)
538/** The Stimer auto-enable mask. */
539#define MSR_GIM_HV_STIMER_AUTO_ENABLE RT_BIT_64(3)
540/** Whether Stimer is enabled or not. */
541#define MSR_GIM_HV_STIMER_IS_AUTO_ENABLED(a) RT_BOOL((a) & MSR_GIM_HV_STIMER_AUTO_ENABLE)
542/** The Stimer SINTx mask (bits 16:19). */
543#define MSR_GIM_HV_STIMER_SINTX UINT64_C(0xf0000)
544/** Gets the Stimer synthetic interrupt source. */
545#define MSR_GIM_HV_STIMER_GET_SINTX(a) (((a) >> 16) & 0xf)
546/** The Stimer valid read/write mask. */
547#define MSR_GIM_HV_STIMER_RW_VALID ( MSR_GIM_HV_STIMER_ENABLE | MSR_GIM_HV_STIMER_PERIODIC \
548 | MSR_GIM_HV_STIMER_LAZY | MSR_GIM_HV_STIMER_AUTO_ENABLE \
549 | MSR_GIM_HV_STIMER_SINTX)
550/** @} */
551
552/**
553 * Hyper-V APIC-assist (HV_REFERENCE_TSC_PAGE) structure placed in the TSC
554 * reference page.
555 */
556typedef struct GIMHVAPICASSIST
557{
558 uint32_t fNoEoiRequired : 1;
559 uint32_t u31Reserved0 : 31;
560} GIMHVAPICASSIST;
561/** Pointer to Hyper-V reference TSC. */
562typedef GIMHVAPICASSIST *PGIMHVAPICASSIST;
563/** Pointer to a const Hyper-V reference TSC. */
564typedef GIMHVAPICASSIST const *PCGIMHVAPICASSIST;
565AssertCompileSize(GIMHVAPICASSIST, 4);
566
567/**
568 * Hypercall parameter type.
569 */
570typedef enum GIMHVHYPERCALLPARAM
571{
572 GIMHVHYPERCALLPARAM_IN = 0,
573 GIMHVHYPERCALLPARAM_OUT
574} GIMHVHYPERCALLPARAM;
575
576
577/** @name Hyper-V hypercall op codes.
578 * @{
579 */
580/** Post message to hypervisor or VMs. */
581#define GIM_HV_HYPERCALL_OP_POST_MESSAGE 0x5C
582/** Post debug data to hypervisor. */
583#define GIM_HV_HYPERCALL_OP_POST_DEBUG_DATA 0x69
584/** Retreive debug data from hypervisor. */
585#define GIM_HV_HYPERCALL_OP_RETREIVE_DEBUG_DATA 0x6A
586/** Reset debug session. */
587#define GIM_HV_HYPERCALL_OP_RESET_DEBUG_SESSION 0x6B
588/** @} */
589
590
591/** @name Hyper-V hypercall inputs.
592 * @{
593 */
594/** The hypercall call operation code. */
595#define GIM_HV_HYPERCALL_IN_CALL_CODE(a) ((a) & UINT64_C(0xffff))
596/** Whether it's a fast (register based) hypercall or not (memory-based). */
597#define GIM_HV_HYPERCALL_IN_IS_FAST(a) RT_BOOL((a) & RT_BIT_64(16))
598/** Total number of reps for a rep hypercall. */
599#define GIM_HV_HYPERCALL_IN_REP_COUNT(a) (((a) << 32) & UINT64_C(0xfff))
600/** Rep start index for a rep hypercall. */
601#define GIM_HV_HYPERCALL_IN_REP_START_IDX(a) (((a) << 48) & UINT64_C(0xfff))
602/** Reserved bits range 1. */
603#define GIM_HV_HYPERCALL_IN_RSVD_1(a) (((a) << 17) & UINT64_C(0x7fff))
604/** Reserved bits range 2. */
605#define GIM_HV_HYPERCALL_IN_RSVD_2(a) (((a) << 44) & UINT64_C(0xf))
606/** Reserved bits range 3. */
607#define GIM_HV_HYPERCALL_IN_RSVD_3(a) (((a) << 60) & UINT64_C(0x7))
608/** @} */
609
610
611/** @name Hyper-V hypercall status codes.
612 * @{
613 */
614/** Success. */
615#define GIM_HV_STATUS_SUCCESS 0x00
616/** Unrecognized hypercall. */
617#define GIM_HV_STATUS_INVALID_HYPERCALL_CODE 0x02
618/** Invalid hypercall input (rep count, rsvd bits). */
619#define GIM_HV_STATUS_INVALID_HYPERCALL_INPUT 0x03
620/** Hypercall guest-physical address not 8-byte aligned or crosses page boundary. */
621#define GIM_HV_STATUS_INVALID_ALIGNMENT 0x04
622/** Invalid hypercall parameters. */
623#define GIM_HV_STATUS_INVALID_PARAMETER 0x05
624/** Access denied. */
625#define GIM_HV_STATUS_ACCESS_DENIED 0x06
626/** The partition state not valid for specified op. */
627#define GIM_HV_STATUS_INVALID_PARTITION_STATE 0x07
628/** The hypercall operation could not be performed. */
629#define GIM_HV_STATUS_OPERATION_DENIED 0x08
630/** Specified partition property ID not recognized. */
631#define GIM_HV_STATUS_UNKNOWN_PROPERTY 0x09
632/** Specified partition property value not within range. */
633#define GIM_HV_STATUS_PROPERTY_VALUE_OUT_OF_RANGE 0x0a
634/** Insufficient memory for performing the hypercall. */
635#define GIM_HV_STATUS_INSUFFICIENT_MEMORY 0x0b
636/** Maximum partition depth has been exceeded for the partition hierarchy. */
637#define GIM_HV_STATUS_PARTITION_TOO_DEEP 0x0c
638/** The specified partition ID is not valid. */
639#define GIM_HV_STATUS_INVALID_PARTITION_ID 0x0d
640/** The specified virtual processor index in invalid. */
641#define GIM_HV_STATUS_INVALID_VP_INDEX 0x0e
642/** The specified port ID is not unique or doesn't exist. */
643#define GIM_HV_STATUS_INVALID_PORT_ID 0x11
644/** The specified connection ID is not unique or doesn't exist. */
645#define GIM_HV_STATUS_INVALID_CONNECTION_ID 0x12
646/** The target port doesn't have sufficient buffers for the caller to post a message. */
647#define GIM_HV_STATUS_INSUFFICIENT_BUFFERS 0x13
648/** External interrupt not acknowledged.*/
649#define GIM_HV_STATUS_NOT_ACKNOWLEDGED 0x14
650/** External interrupt acknowledged. */
651#define GIM_HV_STATUS_ACKNOWLEDGED 0x16
652/** Invalid state due to misordering Hv[Save|Restore]PartitionState. */
653#define GIM_HV_STATUS_INVALID_SAVE_RESTORE_STATE 0x17
654/** Operation not perform due to a required feature of SynIc was disabled. */
655#define GIM_HV_STATUS_INVALID_SYNIC_STATE 0x18
656/** Object or value already in use. */
657#define GIM_HV_STATUS_OBJECT_IN_USE 0x19
658/** Invalid proximity domain information. */
659#define GIM_HV_STATUS_INVALID_PROXIMITY_DOMAIN_INFO 0x1A
660/** Attempt to retrieve data failed. */
661#define GIM_HV_STATUS_NO_DATA 0x1B
662/** Debug connection has not recieved any new data since the last time. */
663#define GIM_HV_STATUS_INACTIVE 0x1C
664/** A resource is unavailable for allocation. */
665#define GIM_HV_STATUS_NO_RESOURCES 0x1D
666/** A hypervisor feature is not available to the caller. */
667#define GIM_HV_STATUS_FEATURE_UNAVAILABLE 0x1E
668/** The debug packet returned is partial due to an I/O error. */
669#define GIM_HV_STATUS_PARTIAL_PACKET 0x1F
670/** Processor feature SSE3 unsupported. */
671#define GIM_HV_STATUS_PROC_FEAT_SSE3_NOT_SUPPORTED 0x20
672/** Processor feature LAHSAHF unsupported. */
673#define GIM_HV_STATUS_PROC_FEAT_LAHSAHF_NOT_SUPPORTED 0x21
674/** Processor feature SSSE3 unsupported. */
675#define GIM_HV_STATUS_PROC_FEAT_SSSE3_NOT_SUPPORTED 0x22
676/** Processor feature SSE4.1 unsupported. */
677#define GIM_HV_STATUS_PROC_FEAT_SSE4_1_NOT_SUPPORTED 0x23
678/** Processor feature SSE4.2 unsupported. */
679#define GIM_HV_STATUS_PROC_FEAT_SSE4_2_NOT_SUPPORTED 0x24
680/** Processor feature SSE4A unsupported. */
681#define GIM_HV_STATUS_PROC_FEAT_SSE4A_NOT_SUPPORTED 0x25
682/** Processor feature XOP unsupported. */
683#define GIM_HV_STATUS_PROC_FEAT_XOP_NOT_SUPPORTED 0x26
684/** Processor feature POPCNT unsupported. */
685#define GIM_HV_STATUS_PROC_FEAT_POPCNT_NOT_SUPPORTED 0x27
686/** Processor feature CMPXCHG16B unsupported. */
687#define GIM_HV_STATUS_PROC_FEAT_CMPXCHG16B_NOT_SUPPORTED 0x28
688/** Processor feature ALTMOVCR8 unsupported. */
689#define GIM_HV_STATUS_PROC_FEAT_ALTMOVCR8_NOT_SUPPORTED 0x29
690/** Processor feature LZCNT unsupported. */
691#define GIM_HV_STATUS_PROC_FEAT_LZCNT_NOT_SUPPORTED 0x2A
692/** Processor feature misaligned SSE unsupported. */
693#define GIM_HV_STATUS_PROC_FEAT_MISALIGNED_SSE_NOT_SUPPORTED 0x2B
694/** Processor feature MMX extensions unsupported. */
695#define GIM_HV_STATUS_PROC_FEAT_MMX_EXT_NOT_SUPPORTED 0x2C
696/** Processor feature 3DNow! unsupported. */
697#define GIM_HV_STATUS_PROC_FEAT_3DNOW_NOT_SUPPORTED 0x2D
698/** Processor feature Extended 3DNow! unsupported. */
699#define GIM_HV_STATUS_PROC_FEAT_EXTENDED_3DNOW_NOT_SUPPORTED 0x2E
700/** Processor feature 1GB large page unsupported. */
701#define GIM_HV_STATUS_PROC_FEAT_PAGE_1GB_NOT_SUPPORTED 0x2F
702/** Processor cache line flush size incompatible. */
703#define GIM_HV_STATUS_PROC_CACHE_LINE_FLUSH_SIZE_INCOMPATIBLE 0x30
704/** Processor feature XSAVE unsupported. */
705#define GIM_HV_STATUS_PROC_FEAT_XSAVE_NOT_SUPPORTED 0x31
706/** Processor feature XSAVEOPT unsupported. */
707#define GIM_HV_STATUS_PROC_FEAT_XSAVEOPT_NOT_SUPPORTED 0x32
708/** The specified buffer was too small for all requested data. */
709#define GIM_HV_STATUS_INSUFFICIENT_BUFFER 0x33
710/** Processor feature XSAVEOPT unsupported. */
711#define GIM_HV_STATUS_PROC_FEAT_XSAVE_AVX_NOT_SUPPORTED 0x34
712/** Processor feature XSAVEOPT unsupported. */
713#define GIM_HV_STATUS_PROC_FEAT_XSAVE_FEAT_NOT_SUPPORTED 0x35 /** Huh, isn't this same as 0x31? */
714/** Processor feature XSAVEOPT unsupported. */
715#define GIM_HV_STATUS_PROC_FEAT_PAGE_XSAVE_SAVE_AREA_INCOMPATIBLE 0x36
716/** Processor architecture unsupoorted. */
717#define GIM_HV_STATUS_INCOMPATIBLE_PROCESSOR 0x37
718/** Max. domains for platform I/O remapping reached. */
719#define GIM_HV_STATUS_INSUFFICIENT_DEVICE_DOMAINS 0x38
720/** Processor feature AES unsupported. */
721#define GIM_HV_STATUS_PROC_FEAT_AES_NOT_SUPPORTED 0x39
722/** Processor feature PCMULQDQ unsupported. */
723#define GIM_HV_STATUS_PROC_FEAT_PCMULQDQ_NOT_SUPPORTED 0x3A
724/** Processor feature XSAVE features unsupported. */
725#define GIM_HV_STATUS_PROC_FEAT_XSAVE_FEATURES_INCOMPATIBLE 0x3B
726/** Generic CPUID validation error. */
727#define GIM_HV_STATUS_CPUID_FEAT_VALIDATION_ERROR 0x3C
728/** XSAVE CPUID validation error. */
729#define GIM_HV_STATUS_CPUID_XSAVE_FEAT_VALIDATION_ERROR 0x3D
730/** Processor startup timed out. */
731#define GIM_HV_STATUS_PROCESSOR_STARTUP_TIMEOUT 0x3E
732/** SMX enabled by the BIOS. */
733#define GIM_HV_STATUS_SMX_ENABLED 0x3F
734/** Processor feature PCID unsupported. */
735#define GIM_HV_STATUS_PROC_FEAT_PCID_NOT_SUPPORTED 0x40
736/** Invalid LP index. */
737#define GIM_HV_STATUS_INVALID_LP_INDEX 0x41
738/** Processor feature PCID unsupported. */
739#define GIM_HV_STATUS_FEAT_FMA4_NOT_SUPPORTED 0x42
740/** Processor feature PCID unsupported. */
741#define GIM_HV_STATUS_FEAT_F16C_NOT_SUPPORTED 0x43
742/** Processor feature PCID unsupported. */
743#define GIM_HV_STATUS_PROC_FEAT_RDRAND_NOT_SUPPORTED 0x44
744/** Processor feature RDWRFSGS unsupported. */
745#define GIM_HV_STATUS_PROC_FEAT_RDWRFSGS_NOT_SUPPORTED 0x45
746/** Processor feature SMEP unsupported. */
747#define GIM_HV_STATUS_PROC_FEAT_SMEP_NOT_SUPPORTED 0x46
748/** Processor feature enhanced fast string unsupported. */
749#define GIM_HV_STATUS_PROC_FEAT_ENHANCED_FAST_STRING_NOT_SUPPORTED 0x47
750/** Processor feature MOVBE unsupported. */
751#define GIM_HV_STATUS_PROC_FEAT_MOVBE_NOT_SUPPORTED 0x48
752/** Processor feature BMI1 unsupported. */
753#define GIM_HV_STATUS_PROC_FEAT_BMI1_NOT_SUPPORTED 0x49
754/** Processor feature BMI2 unsupported. */
755#define GIM_HV_STATUS_PROC_FEAT_BMI2_NOT_SUPPORTED 0x4A
756/** Processor feature HLE unsupported. */
757#define GIM_HV_STATUS_PROC_FEAT_HLE_NOT_SUPPORTED 0x4B
758/** Processor feature RTM unsupported. */
759#define GIM_HV_STATUS_PROC_FEAT_RTM_NOT_SUPPORTED 0x4C
760/** Processor feature XSAVE FMA unsupported. */
761#define GIM_HV_STATUS_PROC_FEAT_XSAVE_FMA_NOT_SUPPORTED 0x4D
762/** Processor feature XSAVE AVX2 unsupported. */
763#define GIM_HV_STATUS_PROC_FEAT_XSAVE_AVX2_NOT_SUPPORTED 0x4E
764/** Processor feature NPIEP1 unsupported. */
765#define GIM_HV_STATUS_PROC_FEAT_NPIEP1_NOT_SUPPORTED 0x4F
766/** @} */
767
768
769/** @name Hyper-V MSR - Debug control (MSR_GIM_HV_SYNTH_DEBUG_CONTROL).
770 * @{
771 */
772/** Perform debug write. */
773#define MSR_GIM_HV_SYNTH_DEBUG_CONTROL_IS_WRITE(a) RT_BOOL((a) & RT_BIT_64(0))
774/** Perform debug read. */
775#define MSR_GIM_HV_SYNTH_DEBUG_CONTROL_IS_READ(a) RT_BOOL((a) & RT_BIT_64(1))
776/** Returns length of the debug write buffer. */
777#define MSR_GIM_HV_SYNTH_DEBUG_CONTROL_W_LEN(a) (((a) & UINT64_C(0xffff0000)) >> 16)
778/** @} */
779
780
781/** @name Hyper-V MSR - Debug status (MSR_GIM_HV_SYNTH_DEBUG_STATUS).
782 * @{
783 */
784/** Debug send buffer operation success. */
785#define MSR_GIM_HV_SYNTH_DEBUG_STATUS_W_SUCCESS RT_BIT_64(0)
786/** Debug receive buffer operation success. */
787#define MSR_GIM_HV_SYNTH_DEBUG_STATUS_R_SUCCESS RT_BIT_64(2)
788/** Debug connection was reset. */
789#define MSR_GIM_HV_SYNTH_DEBUG_STATUS_CONN_RESET RT_BIT_64(3)
790/** @} */
791
792
793/** @name Hyper-V MSR - synthetic interrupt (MSR_GIM_HV_SINTx).
794 * @{
795 */
796/** The interrupt masked mask. */
797#define MSR_GIM_HV_SINT_MASKED RT_BIT_64(16)
798/** Whether the interrupt source is masked. */
799#define MSR_GIM_HV_SINT_IS_MASKED(a) RT_BOOL((a) & MSR_GIM_HV_SINT_MASKED)
800/** Gets the interrupt vector. */
801#define MSR_GIM_HV_SINT_GET_VECTOR(a) ((a) & UINT64_C(0xff))
802/** The AutoEoi mask. */
803#define MSR_GIM_HV_SINT_AUTOEOI RT_BIT_64(17)
804/** Gets whether AutoEoi is enabled for the synthetic interrupt. */
805#define MSR_GIM_HV_SINT_IS_AUTOEOI(a) RT_BOOL((a) & MSR_GIM_HV_SINT_AUTOEOI)
806/** @} */
807
808
809/** @name Hyper-V MSR - synthetic interrupt message page (MSR_GIM_HV_SIMP).
810 * @{
811 */
812/** The SIMP enable mask. */
813#define MSR_GIM_HV_SIMP_ENABLE RT_BIT_64(0)
814/** Whether the SIMP is enabled. */
815#define MSR_GIM_HV_SIMP_IS_ENABLED(a) RT_BOOL((a) & MSR_GIM_HV_SIMP_ENABLE)
816/** The SIMP guest-physical address. */
817#define MSR_GIM_HV_SIMP_GPA(a) ((a) & UINT64_C(0xfffffffffffff000))
818/** @} */
819
820
821/** @name Hyper-V hypercall debug options.
822 * @{ */
823/** Maximum debug data payload size in bytes. */
824#define GIM_HV_DEBUG_MAX_DATA_SIZE 4088
825
826/** The undocumented bit for MSR_GIM_HV_DEBUG_OPTIONS_MSR that makes it all
827 * work. */
828#define GIM_HV_DEBUG_OPTIONS_USE_HYPERCALLS RT_BIT(2)
829
830/** Guest will perform the HvPostDebugData hypercall until completion. */
831#define GIM_HV_DEBUG_POST_LOOP RT_BIT_32(0)
832/** Mask of valid HvPostDebugData options. */
833#define GIM_HV_DEBUG_POST_OPTIONS_MASK RT_BIT_32(0)
834
835/** Guest will perform the HvRetrieveDebugData hypercall until completion. */
836#define GIM_HV_DEBUG_RETREIVE_LOOP RT_BIT_32(0)
837/** Guest checks if any global debug session is active. */
838#define GIM_HV_DEBUG_RETREIVE_TEST_ACTIVITY RT_BIT_32(1)
839/** Mask of valid HvRetrieveDebugData options. */
840#define GIM_HV_DEBUG_RETREIVE_OPTIONS_MASK RT_BIT_32(0) | RT_BIT_32(1)
841
842/** Guest requests purging of incoming debug data. */
843#define GIM_HV_DEBUG_PURGE_INCOMING_DATA RT_BIT_32(0)
844/** Guest requests purging of outgoing debug data. */
845#define GIM_HV_DEBUG_PURGE_OUTGOING_DATA RT_BIT_32(1)
846/** @}*/
847
848
849/** @name VMBus.
850 * These are just arbitrary definitions made up by Microsoft without
851 * any publicly available specification behind it.
852 * @{ */
853/** VMBus connection ID. */
854#define GIM_HV_VMBUS_MSG_CONNECTION_ID 1
855/** VMBus synthetic interrupt source (see VMBUS_MESSAGE_SINT in linux
856 * sources). */
857#define GIM_HV_VMBUS_MSG_SINT 2
858/** @} */
859
860/** @name SynIC.
861 * Synthetic Interrupt Controller definitions.
862 */
863/** SynIC version register. */
864#define GIM_HV_SVERSION 1
865/** Number of synthetic interrupt sources (warning, fixed in saved-states!). */
866#define GIM_HV_SINT_COUNT 16
867/** Lowest valid vector for synthetic interrupt. */
868#define GIM_HV_SINT_VECTOR_VALID_MIN 16
869/** Highest valid vector for synthetic interrupt. */
870#define GIM_HV_SINT_VECTOR_VALID_MAX 255
871/** Number of synthetic timers. */
872#define GIM_HV_STIMER_COUNT 4
873/** @} */
874
875/** @name Hyper-V synthetic interrupt message type.
876 * See 14.8.2 "SynIC Message Types"
877 * @{
878 */
879typedef enum GIMHVMSGTYPE
880{
881 GIMHVMSGTYPE_NONE = 0, /* Common messages */
882 GIMHVMSGTYPE_VMBUS = 1, /* Guest messages */
883 GIMHVMSGTYPE_UNMAPPEDGPA = 0x80000000, /* Hypervisor messages */
884 GIMHVMSGTYPE_GPAINTERCEPT = 0x80000001,
885 GIMHVMSGTYPE_TIMEREXPIRED = 0x80000010,
886 GIMHVMSGTYPE_INVALIDVPREGVAL = 0x80000020,
887 GIMHVMSGTYPE_UNRECOVERABLEXCPT = 0x80000021,
888 GIMHVMSGTYPE_UNSUPPORTEDFEAT = 0x80000022,
889 GIMHVMSGTYPE_APICEOI = 0x80000030,
890 GIMHVMSGTYPE_X64LEGACYFPERROR = 0x80000031,
891 GIMHVMSGTYPE_EVENTLOGBUFSCOMPLETE = 0x80000040,
892 GIMHVMSGTYPE_X64IOPORTINTERCEPT = 0x80010000,
893 GIMHVMSGTYPE_X64MSRINTERCEPT = 0x80010001,
894 GIMHVMSGTYPE_X64CPUIDINTERCEPT = 0x80010002,
895 GIMHVMSGTYPE_X64XCPTINTERCEPT = 0x80010003
896} GIMHVMSGTYPE;
897AssertCompileSize(GIMHVMSGTYPE, 4);
898/** @} */
899
900
901/** @name Hyper-V synthetic interrupt message format.
902 * @{ */
903#define GIM_HV_MSG_SIZE 256
904#define GIM_HV_MSG_MAX_PAYLOAD_SIZE 240
905#define GIM_HV_MSG_MAX_PAYLOAD_UNITS 30
906
907/**
908 * Synthetic interrupt message flags.
909 */
910typedef union GIMHVMSGFLAGS
911{
912 struct
913 {
914 uint8_t u1Pending : 1;
915 uint8_t u7Reserved : 7;
916 } n;
917 uint8_t u;
918} GIMHVMSGFLAGS;
919AssertCompileSize(GIMHVMSGFLAGS, sizeof(uint8_t));
920
921/**
922 * Synthetic interrupt message header.
923 *
924 * @remarks The layout of this structure differs from
925 * the Hyper-V spec. Aug 8, 2013 v4.0a. Layout
926 * in accordance w/ VMBus client expectations.
927 */
928typedef struct GIMHVMSGHDR
929{
930 GIMHVMSGTYPE enmMessageType;
931 uint8_t cbPayload;
932 GIMHVMSGFLAGS MessageFlags;
933 uint16_t uRsvd;
934 union
935 {
936 uint64_t uOriginatorId;
937 uint64_t uPartitionId;
938 uint64_t uPortId;
939 } msgid;
940} GIMHVMSGHDR;
941/** Pointer to a synthetic interrupt message header. */
942typedef GIMHVMSGHDR *PGIMHVMSGHDR;
943AssertCompileMemberOffset(GIMHVMSGHDR, cbPayload, 4);
944AssertCompileMemberOffset(GIMHVMSGHDR, MessageFlags, 5);
945AssertCompileMemberOffset(GIMHVMSGHDR, msgid, 8);
946AssertCompileSize(GIMHVMSGHDR, GIM_HV_MSG_SIZE - GIM_HV_MSG_MAX_PAYLOAD_SIZE);
947
948/**
949 * Synthetic interrupt message.
950 */
951typedef struct GIMHVMSG
952{
953 GIMHVMSGHDR MsgHdr;
954 uint64_t aPayload[GIM_HV_MSG_MAX_PAYLOAD_UNITS];
955} GIMHVMSG;
956/** Pointer to a synthetic interrupt message. */
957typedef GIMHVMSG *PGIMHVMSG;
958AssertCompileSize(GIMHVMSG, GIM_HV_MSG_SIZE);
959/** @} */
960
961
962/** @name Hyper-V hypercall parameters.
963 * @{ */
964/**
965 * HvPostMessage hypercall input.
966 */
967typedef struct GIMHVPOSTMESSAGEIN
968{
969 uint32_t uConnectionId;
970 uint32_t uPadding;
971 GIMHVMSGTYPE enmMessageType;
972 uint32_t cbPayload;
973} GIMHVPOSTMESSAGEIN;
974/** Pointer to a HvPostMessage input struct. */
975typedef GIMHVPOSTMESSAGEIN *PGIMHVPOSTMESSAGEIN;
976AssertCompileSize(GIMHVPOSTMESSAGEIN, 16);
977
978/**
979 * HvResetDebugData hypercall input.
980 */
981typedef struct GIMHVDEBUGRESETIN
982{
983 uint32_t fFlags;
984 uint32_t uPadding;
985} GIMHVDEBUGRESETIN;
986/** Pointer to a HvResetDebugData input struct. */
987typedef GIMHVDEBUGRESETIN *PGIMHVDEBUGRESETIN;
988AssertCompileSize(GIMHVDEBUGRESETIN, 8);
989
990/**
991 * HvPostDebugData hypercall input.
992 */
993typedef struct GIMHVDEBUGPOSTIN
994{
995 uint32_t cbWrite;
996 uint32_t fFlags;
997} GIMHVDEBUGPOSTIN;
998/** Pointer to a HvPostDebugData input struct. */
999typedef GIMHVDEBUGPOSTIN *PGIMHVDEBUGPOSTIN;
1000AssertCompileSize(GIMHVDEBUGPOSTIN, 8);
1001
1002/**
1003 * HvPostDebugData hypercall output.
1004 */
1005typedef struct GIMHVDEBUGPOSTOUT
1006{
1007 uint32_t cbPending;
1008 uint32_t uPadding;
1009} GIMHVDEBUGPOSTOUT;
1010/** Pointer to a HvPostDebugData output struct. */
1011typedef GIMHVDEBUGPOSTOUT *PGIMHVDEBUGPOSTOUT;
1012AssertCompileSize(GIMHVDEBUGPOSTOUT, 8);
1013
1014/**
1015 * HvRetrieveDebugData hypercall input.
1016 */
1017typedef struct GIMHVDEBUGRETRIEVEIN
1018{
1019 uint32_t cbRead;
1020 uint32_t fFlags;
1021 uint64_t u64Timeout;
1022} GIMHVDEBUGRETRIEVEIN;
1023/** Pointer to a HvRetrieveDebugData input struct. */
1024typedef GIMHVDEBUGRETRIEVEIN *PGIMHVDEBUGRETRIEVEIN;
1025AssertCompileSize(GIMHVDEBUGRETRIEVEIN, 16);
1026
1027/**
1028 * HvRetriveDebugData hypercall output.
1029 */
1030typedef struct GIMHVDEBUGRETRIEVEOUT
1031{
1032 uint32_t cbRead;
1033 uint32_t cbRemaining;
1034} GIMHVDEBUGRETRIEVEOUT;
1035/** Pointer to a HvRetrieveDebugData output struct. */
1036typedef GIMHVDEBUGRETRIEVEOUT *PGIMHVDEBUGRETRIEVEOUT;
1037AssertCompileSize(GIMHVDEBUGRETRIEVEOUT, 8);
1038/** @} */
1039
1040
1041/** Hyper-V page size. */
1042#define GIM_HV_PAGE_SIZE 4096
1043
1044/** Microsoft Hyper-V vendor signature. */
1045#define GIM_HV_VENDOR_MICROSOFT "Microsoft Hv"
1046
1047/**
1048 * MMIO2 region indices.
1049 */
1050/** The hypercall page region. */
1051#define GIM_HV_HYPERCALL_PAGE_REGION_IDX UINT8_C(0)
1052/** The TSC page region. */
1053#define GIM_HV_REF_TSC_PAGE_REGION_IDX UINT8_C(1)
1054/** The maximum region index (must be <= UINT8_MAX). */
1055#define GIM_HV_REGION_IDX_MAX GIM_HV_REF_TSC_PAGE_REGION_IDX
1056
1057/**
1058 * Hyper-V TSC (HV_REFERENCE_TSC_PAGE) structure placed in the TSC reference
1059 * page.
1060 */
1061typedef struct GIMHVREFTSC
1062{
1063 uint32_t u32TscSequence;
1064 uint32_t uReserved0;
1065 uint64_t u64TscScale;
1066 int64_t i64TscOffset;
1067} GIMHVTSCPAGE;
1068/** Pointer to Hyper-V reference TSC. */
1069typedef GIMHVREFTSC *PGIMHVREFTSC;
1070/** Pointer to a const Hyper-V reference TSC. */
1071typedef GIMHVREFTSC const *PCGIMHVREFTSC;
1072
1073/**
1074 * Type of the next reply to be sent to the debug connection of the guest.
1075 *
1076 * @remarks This is saved as part of saved-state, so don't re-order or
1077 * alter the size!
1078 */
1079typedef enum GIMHVDEBUGREPLY
1080{
1081 /** Send UDP packet. */
1082 GIMHVDEBUGREPLY_UDP = 0,
1083 /** Send DHCP offer for DHCP discover. */
1084 GIMHVDEBUGREPLY_DHCP_OFFER,
1085 /** DHCP offer sent. */
1086 GIMHVDEBUGREPLY_DHCP_OFFER_SENT,
1087 /** Send DHCP acknowledgement for DHCP request. */
1088 GIMHVDEBUGREPLY_DHCP_ACK,
1089 /** DHCP acknowledgement sent. */
1090 GIMHVDEBUGREPLY_DHCP_ACK_SENT,
1091 /** Sent ARP reply. */
1092 GIMHVDEBUGREPLY_ARP_REPLY,
1093 /** ARP reply sent. */
1094 GIMHVDEBUGREPLY_ARP_REPLY_SENT,
1095 /** Customary 32-bit type hack. */
1096 GIMHVDEBUGREPLY_32BIT_HACK = 0x7fffffff
1097} GIMHVDEBUGREPLY;
1098AssertCompileSize(GIMHVDEBUGREPLY, sizeof(uint32_t));
1099
1100/**
1101 * GIM Hyper-V VM instance data.
1102 * Changes to this must checked against the padding of the gim union in VM!
1103 */
1104typedef struct GIMHV
1105{
1106 /** @name Primary MSRs.
1107 * @{ */
1108 /** Guest OS identity MSR. */
1109 uint64_t u64GuestOsIdMsr;
1110 /** Hypercall MSR. */
1111 uint64_t u64HypercallMsr;
1112 /** Reference TSC page MSR. */
1113 uint64_t u64TscPageMsr;
1114 /** @} */
1115
1116 /** @name CPUID features.
1117 * @{ */
1118 /** Basic features. */
1119 uint32_t uBaseFeat;
1120 /** Partition flags. */
1121 uint32_t uPartFlags;
1122 /** Power management. */
1123 uint32_t uPowMgmtFeat;
1124 /** Miscellaneous. */
1125 uint32_t uMiscFeat;
1126 /** Hypervisor hints to the guest. */
1127 uint32_t uHyperHints;
1128 /** Hypervisor capabilities. */
1129 uint32_t uHyperCaps;
1130 /** @} */
1131
1132 /** @name Guest Crash MSRs.
1133 * @{
1134 */
1135 /** Guest crash control MSR. */
1136 uint64_t uCrashCtlMsr;
1137 /** Guest crash parameter 0 MSR. */
1138 uint64_t uCrashP0Msr;
1139 /** Guest crash parameter 1 MSR. */
1140 uint64_t uCrashP1Msr;
1141 /** Guest crash parameter 2 MSR. */
1142 uint64_t uCrashP2Msr;
1143 /** Guest crash parameter 3 MSR. */
1144 uint64_t uCrashP3Msr;
1145 /** Guest crash parameter 4 MSR. */
1146 uint64_t uCrashP4Msr;
1147 /** @} */
1148
1149 /** @name Time management.
1150 * @{ */
1151 /** Per-VM R0 Spinlock for protecting EMT writes to the TSC page. */
1152 RTSPINLOCK hSpinlockR0;
1153#if HC_ARCH_BITS == 32
1154 uint32_t u32Alignment1;
1155#endif
1156 /** The TSC frequency (in HZ) reported to the guest. */
1157 uint64_t cTscTicksPerSecond;
1158 /** @} */
1159
1160 /** @name Hypercalls. */
1161 /* @{ */
1162 /** Guest address of the hypercall input parameter page. */
1163 RTGCPHYS GCPhysHypercallIn;
1164 /** Guest address of the hypercall output parameter page. */
1165 RTGCPHYS GCPhysHypercallOut;
1166 /** Pointer to the hypercall input parameter page - R3. */
1167 R3PTRTYPE(uint8_t *) pbHypercallIn;
1168 /** Pointer to the hypercall output parameter page - R3. */
1169 R3PTRTYPE(uint8_t *) pbHypercallOut;
1170 /** @} */
1171
1172 /** @name Guest debugging.
1173 * @{ */
1174 /** Whether we're posing as the Microsoft vendor. */
1175 bool fIsVendorMsHv;
1176 /** Whether we're posing as the Microsoft virtualization service. */
1177 bool fIsInterfaceVs;
1178 /** Whether debugging support is enabled. */
1179 bool fDbgEnabled;
1180 /** Whether we should suggest a hypercall-based debug interface to the guest. */
1181 bool fDbgHypercallInterface;
1182 bool afAlignment0[4];
1183 /** The action to take while sending replies. */
1184 GIMHVDEBUGREPLY enmDbgReply;
1185 /** The IP address chosen by/assigned to the guest. */
1186 RTNETADDRIPV4 DbgGuestIp4Addr;
1187 /** Transaction ID for the BOOTP+DHCP sequence. */
1188 uint32_t uDbgBootpXId;
1189 /** The source UDP port used by the guest while sending debug packets. */
1190 uint16_t uUdpGuestSrcPort;
1191 /** The destination UDP port used by the guest while sending debug packets. */
1192 uint16_t uUdpGuestDstPort;
1193 /** Debug send buffer MSR. */
1194 uint64_t uDbgSendBufferMsr;
1195 /** Debug receive buffer MSR. */
1196 uint64_t uDbgRecvBufferMsr;
1197 /** Debug pending buffer MSR. */
1198 uint64_t uDbgPendingBufferMsr;
1199 /** Debug status MSR. */
1200 uint64_t uDbgStatusMsr;
1201 /** Intermediate debug I/O buffer. */
1202 R3PTRTYPE(void *) pvDbgBuffer;
1203 R3PTRTYPE(void *) pvAlignment0;
1204 /** @} */
1205
1206 /** Array of MMIO2 regions. */
1207 GIMMMIO2REGION aMmio2Regions[GIM_HV_REGION_IDX_MAX + 1];
1208} GIMHV;
1209/** Pointer to per-VM GIM Hyper-V instance data. */
1210typedef GIMHV *PGIMHV;
1211/** Pointer to const per-VM GIM Hyper-V instance data. */
1212typedef GIMHV const *PCGIMHV;
1213AssertCompileMemberAlignment(GIMHV, aMmio2Regions, 8);
1214AssertCompileMemberAlignment(GIMHV, hSpinlockR0, sizeof(uintptr_t));
1215
1216/**
1217 * Hyper-V per-VCPU synthetic timer.
1218 */
1219typedef struct GIMHVSTIMER
1220{
1221 /** Synthetic timer object - R0 ptr. */
1222 PTMTIMERR0 pTimerR0;
1223 /** Synthetic timer object - R3 ptr. */
1224 PTMTIMERR3 pTimerR3;
1225 /** Synthetic timer object - RC ptr. */
1226 PTMTIMERRC pTimerRC;
1227 /** RC alignment padding. */
1228 RTRCPTR uAlignment0;
1229 /** Virtual CPU ID this timer belongs to (for reverse mapping). */
1230 VMCPUID idCpu;
1231 /** The index of this timer in the auStimers array (for reverse mapping). */
1232 uint32_t idxStimer;
1233 /** Synthetic timer config MSR. */
1234 uint64_t uStimerConfigMsr;
1235 /** Synthetic timer count MSR. */
1236 uint64_t uStimerCountMsr;
1237 /** Timer description. */
1238 char szTimerDesc[24];
1239
1240} GIMHVSTIMER;
1241/** Pointer to per-VCPU Hyper-V synthetic timer. */
1242typedef GIMHVSTIMER *PGIMHVSTIMER;
1243/** Pointer to a const per-VCPU Hyper-V synthetic timer. */
1244typedef GIMHVSTIMER const *PCGIMHVSTIMER;
1245AssertCompileSizeAlignment(GIMHVSTIMER, 8);
1246
1247/**
1248 * Hyper-V VCPU instance data.
1249 * Changes to this must checked against the padding of the gim union in VMCPU!
1250 */
1251typedef struct GIMHVCPU
1252{
1253 /** @name Synthetic interrupt MSRs.
1254 * @{ */
1255 /** Synthetic interrupt message page MSR. */
1256 uint64_t uSimpMsr;
1257 /** Interrupt source MSRs. */
1258 uint64_t auSintMsrs[GIM_HV_SINT_COUNT];
1259 /** Synethtic interrupt events flag page MSR. */
1260 uint64_t uSiefpMsr;
1261 /** APIC-assist page MSR. */
1262 uint64_t uApicAssistPageMsr;
1263 /** Synthetic interrupt control MSR. */
1264 uint64_t uSControlMsr;
1265 /** Synthetic timers. */
1266 GIMHVSTIMER aStimers[GIM_HV_STIMER_COUNT];
1267 /** @} */
1268
1269 /** @name Statistics.
1270 * @{ */
1271 STAMCOUNTER aStatStimerFired[GIM_HV_STIMER_COUNT];
1272 /** @} */
1273} GIMHVCPU;
1274/** Pointer to per-VCPU GIM Hyper-V instance data. */
1275typedef GIMHVCPU *PGIMHVCPU;
1276/** Pointer to const per-VCPU GIM Hyper-V instance data. */
1277typedef GIMHVCPU const *PCGIMHVCPU;
1278
1279
1280RT_C_DECLS_BEGIN
1281
1282#ifdef IN_RING0
1283VMMR0_INT_DECL(int) gimR0HvInitVM(PVM pVM);
1284VMMR0_INT_DECL(int) gimR0HvTermVM(PVM pVM);
1285VMMR0_INT_DECL(int) gimR0HvUpdateParavirtTsc(PVM pVM, uint64_t u64Offset);
1286#endif /* IN_RING0 */
1287
1288#ifdef IN_RING3
1289VMMR3_INT_DECL(int) gimR3HvInit(PVM pVM, PCFGMNODE pGimCfg);
1290VMMR3_INT_DECL(int) gimR3HvInitCompleted(PVM pVM);
1291VMMR3_INT_DECL(int) gimR3HvTerm(PVM pVM);
1292VMMR3_INT_DECL(void) gimR3HvRelocate(PVM pVM, RTGCINTPTR offDelta);
1293VMMR3_INT_DECL(void) gimR3HvReset(PVM pVM);
1294VMMR3_INT_DECL(PGIMMMIO2REGION) gimR3HvGetMmio2Regions(PVM pVM, uint32_t *pcRegions);
1295VMMR3_INT_DECL(int) gimR3HvSave(PVM pVM, PSSMHANDLE pSSM);
1296VMMR3_INT_DECL(int) gimR3HvLoad(PVM pVM, PSSMHANDLE pSSM);
1297VMMR3_INT_DECL(int) gimR3HvGetDebugSetup(PVM pVM, PGIMDEBUGSETUP pDbgSetup);
1298
1299VMMR3_INT_DECL(int) gimR3HvDisableSiefPage(PVMCPU pVCpu);
1300VMMR3_INT_DECL(int) gimR3HvEnableSiefPage(PVMCPU pVCpu, RTGCPHYS GCPhysSiefPage);
1301VMMR3_INT_DECL(int) gimR3HvEnableSimPage(PVMCPU pVCpu, RTGCPHYS GCPhysSimPage);
1302VMMR3_INT_DECL(int) gimR3HvDisableSimPage(PVMCPU pVCpu);
1303VMMR3_INT_DECL(int) gimR3HvDisableApicAssistPage(PVMCPU pVCpu);
1304VMMR3_INT_DECL(int) gimR3HvEnableApicAssistPage(PVMCPU pVCpu, RTGCPHYS GCPhysTscPage);
1305VMMR3_INT_DECL(int) gimR3HvDisableTscPage(PVM pVM);
1306VMMR3_INT_DECL(int) gimR3HvEnableTscPage(PVM pVM, RTGCPHYS GCPhysTscPage, bool fUseThisTscSeq, uint32_t uTscSeq);
1307VMMR3_INT_DECL(int) gimR3HvDisableHypercallPage(PVM pVM);
1308VMMR3_INT_DECL(int) gimR3HvEnableHypercallPage(PVM pVM, RTGCPHYS GCPhysHypercallPage);
1309
1310VMMR3_INT_DECL(int) gimR3HvHypercallPostDebugData(PVM pVM, int *prcHv);
1311VMMR3_INT_DECL(int) gimR3HvHypercallRetrieveDebugData(PVM pVM, int *prcHv);
1312VMMR3_INT_DECL(int) gimR3HvDebugWrite(PVM pVM, void *pvData, uint32_t cbWrite, uint32_t *pcbWritten, bool fUdpPkt);
1313VMMR3_INT_DECL(int) gimR3HvDebugRead(PVM pVM, void *pvBuf, uint32_t cbBuf, uint32_t cbRead, uint32_t *pcbRead,
1314 uint32_t cMsTimeout, bool fUdpPkt);
1315#endif /* IN_RING3 */
1316
1317VMM_INT_DECL(bool) gimHvIsParavirtTscEnabled(PVM pVM);
1318VMM_INT_DECL(bool) gimHvAreHypercallsEnabled(PVMCPU pVCpu);
1319VMM_INT_DECL(bool) gimHvShouldTrapXcptUD(PVMCPU pVCpu);
1320VMM_INT_DECL(VBOXSTRICTRC) gimHvXcptUD(PVMCPU pVCpu, PCPUMCTX pCtx, PDISCPUSTATE pDis, uint8_t *pcbInstr);
1321VMM_INT_DECL(VBOXSTRICTRC) gimHvHypercall(PVMCPU pVCpu, PCPUMCTX pCtx);
1322VMM_INT_DECL(VBOXSTRICTRC) gimHvExecHypercallInstr(PVMCPU pVCpu, PCPUMCTX pCtx, PDISCPUSTATE pDis);
1323VMM_INT_DECL(VBOXSTRICTRC) gimHvReadMsr(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue);
1324VMM_INT_DECL(VBOXSTRICTRC) gimHvWriteMsr(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uRawValue);
1325
1326VMM_INT_DECL(void) gimHvStartStimer(PVMCPU pVCpu, PCGIMHVSTIMER pHvStimer);
1327
1328RT_C_DECLS_END
1329
1330#endif
1331
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