HMInternal.h@ 43413

Last change on this file since 43413 was 43387, checked in by vboxsync, 13 years ago
VMM: HM cleanup.
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1	/* $Id: HMInternal.h 43387 2012-09-21 09:40:25Z vboxsync $ */
2	/** @file
3	* HM - Internal header file.
4	*/
5
6	/*
7	* Copyright (C) 2006-2012 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*/
17
18	#ifndef ___HMInternal_h
19	#define ___HMInternal_h
20
21	#include <VBox/cdefs.h>
22	#include <VBox/types.h>
23	#include <VBox/vmm/em.h>
24	#include <VBox/vmm/stam.h>
25	#include <VBox/dis.h>
26	#include <VBox/vmm/hm.h>
27	#include <VBox/vmm/hm_vmx.h>
28	#include <VBox/vmm/pgm.h>
29	#include <VBox/vmm/cpum.h>
30	#include <iprt/memobj.h>
31	#include <iprt/cpuset.h>
32	#include <iprt/mp.h>
33	#include <iprt/avl.h>
34
35	#if HC_ARCH_BITS == 64 \|\| defined(VBOX_WITH_HYBRID_32BIT_KERNEL) \|\| defined (VBOX_WITH_64_BITS_GUESTS)
36	/* Enable 64 bits guest support. */
37	# define VBOX_ENABLE_64_BITS_GUESTS
38	#endif
39
40	#define VMX_USE_CACHED_VMCS_ACCESSES
41	#define HM_VMX_EMULATE_REALMODE
42
43	/* The MSR auto load/store does not work for KERNEL_GS_BASE MSR, thus we
44	* handle this MSR manually. See @bugref{6208}. This is clearly visible while
45	* booting Solaris 11 (11.1 b19) VMs with 2 Cpus.
46	*
47	* Note: don't forget to update the assembly files while modifying this!
48	*/
49	# define VBOX_WITH_AUTO_MSR_LOAD_RESTORE
50
51	RT_C_DECLS_BEGIN
52
53
54	/** @defgroup grp_hm_int Internal
55	* @ingroup grp_hm
56	* @internal
57	* @{
58	*/
59
60
61	/** Maximum number of exit reason statistics counters. */
62	#define MAX_EXITREASON_STAT 0x100
63	#define MASK_EXITREASON_STAT 0xff
64	#define MASK_INJECT_IRQ_STAT 0xff
65
66	/** @name Changed flags
67	* These flags are used to keep track of which important registers that
68	* have been changed since last they were reset.
69	* @{
70	*/
71	#define HM_CHANGED_GUEST_FPU RT_BIT(0)
72	#define HM_CHANGED_GUEST_CR0 RT_BIT(1)
73	#define HM_CHANGED_GUEST_CR3 RT_BIT(2)
74	#define HM_CHANGED_GUEST_CR4 RT_BIT(3)
75	#define HM_CHANGED_GUEST_GDTR RT_BIT(4)
76	#define HM_CHANGED_GUEST_IDTR RT_BIT(5)
77	#define HM_CHANGED_GUEST_LDTR RT_BIT(6)
78	#define HM_CHANGED_GUEST_TR RT_BIT(7)
79	#define HM_CHANGED_GUEST_MSR RT_BIT(8)
80	#define HM_CHANGED_GUEST_SEGMENT_REGS RT_BIT(9)
81	#define HM_CHANGED_GUEST_DEBUG RT_BIT(10)
82	#define HM_CHANGED_HOST_CONTEXT RT_BIT(11)
83
84	#define HM_CHANGED_ALL ( HM_CHANGED_GUEST_SEGMENT_REGS \
85	\| HM_CHANGED_GUEST_CR0 \
86	\| HM_CHANGED_GUEST_CR3 \
87	\| HM_CHANGED_GUEST_CR4 \
88	\| HM_CHANGED_GUEST_GDTR \
89	\| HM_CHANGED_GUEST_IDTR \
90	\| HM_CHANGED_GUEST_LDTR \
91	\| HM_CHANGED_GUEST_TR \
92	\| HM_CHANGED_GUEST_MSR \
93	\| HM_CHANGED_GUEST_FPU \
94	\| HM_CHANGED_GUEST_DEBUG \
95	\| HM_CHANGED_HOST_CONTEXT)
96
97	#define HM_CHANGED_ALL_GUEST ( HM_CHANGED_GUEST_SEGMENT_REGS \
98	\| HM_CHANGED_GUEST_CR0 \
99	\| HM_CHANGED_GUEST_CR3 \
100	\| HM_CHANGED_GUEST_CR4 \
101	\| HM_CHANGED_GUEST_GDTR \
102	\| HM_CHANGED_GUEST_IDTR \
103	\| HM_CHANGED_GUEST_LDTR \
104	\| HM_CHANGED_GUEST_TR \
105	\| HM_CHANGED_GUEST_MSR \
106	\| HM_CHANGED_GUEST_DEBUG \
107	\| HM_CHANGED_GUEST_FPU)
108
109	/** @} */
110
111	/** Maximum number of page flushes we are willing to remember before considering a full TLB flush. */
112	#define HM_MAX_TLB_SHOOTDOWN_PAGES 8
113
114	/** Size for the EPT identity page table (1024 4 MB pages to cover the entire address space). */
115	#define HM_EPT_IDENTITY_PG_TABLE_SIZE PAGE_SIZE
116	/** Size of the TSS structure + 2 pages for the IO bitmap + end byte. */
117	#define HM_VTX_TSS_SIZE (sizeof(VBOXTSS) + 2*PAGE_SIZE + 1)
118	/** Total guest mapped memory needed. */
119	#define HM_VTX_TOTAL_DEVHEAP_MEM (HM_EPT_IDENTITY_PG_TABLE_SIZE + HM_VTX_TSS_SIZE)
120
121	/** Enable for TPR guest patching. */
122	#define VBOX_HM_WITH_GUEST_PATCHING
123
124	/** HM SSM version
125	*/
126	#ifdef VBOX_HM_WITH_GUEST_PATCHING
127	# define HM_SSM_VERSION 5
128	# define HM_SSM_VERSION_NO_PATCHING 4
129	#else
130	# define HM_SSM_VERSION 4
131	# define HM_SSM_VERSION_NO_PATCHING 4
132	#endif
133	#define HM_SSM_VERSION_2_0_X 3
134
135	/**
136	* Global per-cpu information. (host)
137	*/
138	typedef struct HMGLOBLCPUINFO
139	{
140	/** The CPU ID. */
141	RTCPUID idCpu;
142	/** The memory object */
143	RTR0MEMOBJ hMemObj;
144	/** Current ASID (AMD-V) / VPID (Intel). */
145	uint32_t uCurrentASID;
146	/** TLB flush count. */
147	uint32_t cTLBFlushes;
148	/** Whether to flush each new ASID/VPID before use. */
149	bool fFlushASIDBeforeUse;
150	/** Configured for VT-x or AMD-V. */
151	bool fConfigured;
152	/** Set if the VBOX_HWVIRTEX_IGNORE_SVM_IN_USE hack is active. */
153	bool fIgnoreAMDVInUseError;
154	/** In use by our code. (for power suspend) */
155	volatile bool fInUse;
156	} HMGLOBLCPUINFO;
157	/** Pointer to the per-cpu global information. */
158	typedef HMGLOBLCPUINFO *PHMGLOBLCPUINFO;
159
160	typedef enum
161	{
162	HMPENDINGIO_INVALID = 0,
163	HMPENDINGIO_PORT_READ,
164	HMPENDINGIO_PORT_WRITE,
165	HMPENDINGIO_STRING_READ,
166	HMPENDINGIO_STRING_WRITE,
167	/** The usual 32-bit paranoia. */
168	HMPENDINGIO_32BIT_HACK = 0x7fffffff
169	} HMPENDINGIO;
170
171
172	typedef enum
173	{
174	HMTPRINSTR_INVALID,
175	HMTPRINSTR_READ,
176	HMTPRINSTR_READ_SHR4,
177	HMTPRINSTR_WRITE_REG,
178	HMTPRINSTR_WRITE_IMM,
179	HMTPRINSTR_JUMP_REPLACEMENT,
180	/** The usual 32-bit paranoia. */
181	HMTPRINSTR_32BIT_HACK = 0x7fffffff
182	} HMTPRINSTR;
183
184	typedef struct
185	{
186	/** The key is the address of patched instruction. (32 bits GC ptr) */
187	AVLOU32NODECORE Core;
188	/** Original opcode. */
189	uint8_t aOpcode[16];
190	/** Instruction size. */
191	uint32_t cbOp;
192	/** Replacement opcode. */
193	uint8_t aNewOpcode[16];
194	/** Replacement instruction size. */
195	uint32_t cbNewOp;
196	/** Instruction type. */
197	HMTPRINSTR enmType;
198	/** Source operand. */
199	uint32_t uSrcOperand;
200	/** Destination operand. */
201	uint32_t uDstOperand;
202	/** Number of times the instruction caused a fault. */
203	uint32_t cFaults;
204	/** Patch address of the jump replacement. */
205	RTGCPTR32 pJumpTarget;
206	} HMTPRPATCH;
207	/** Pointer to HMTPRPATCH. */
208	typedef HMTPRPATCH *PHMTPRPATCH;
209
210	/**
211	* Switcher function, HC to RC.
212	*
213	* @param pVM Pointer to the VM.
214	* @param uOffsetVMCPU VMCPU offset from pVM
215	* @returns Return code indicating the action to take.
216	*/
217	typedef DECLCALLBACK (int) FNHMSWITCHERHC(PVM pVM, uint32_t uOffsetVMCPU);
218	/** Pointer to switcher function. */
219	typedef FNHMSWITCHERHC *PFNHMSWITCHERHC;
220
221	/**
222	* HM VM Instance data.
223	* Changes to this must checked against the padding of the hm union in VM!
224	*/
225	typedef struct HM
226	{
227	/** Set when we've initialized VMX or SVM. */
228	bool fInitialized;
229
230	/** Set when hardware acceleration is allowed. */
231	bool fAllowed;
232
233	/** Set if nested paging is enabled. */
234	bool fNestedPaging;
235
236	/** Set if nested paging is allowed. */
237	bool fAllowNestedPaging;
238
239	/** Set if large pages are enabled (requires nested paging). */
240	bool fLargePages;
241
242	/** Set if we can support 64-bit guests or not. */
243	bool fAllow64BitGuests;
244
245	/** Set if an IO-APIC is configured for this VM. */
246	bool fHasIoApic;
247
248	/** Set when TPR patching is allowed. */
249	bool fTRPPatchingAllowed;
250
251	/** Set when we initialize VT-x or AMD-V once for all CPUs. */
252	bool fGlobalInit;
253
254	/** Set when TPR patching is active. */
255	bool fTPRPatchingActive;
256	bool u8Alignment[6];
257
258	/** And mask for copying register contents. */
259	uint64_t u64RegisterMask;
260
261	/** Maximum ASID allowed. */
262	uint32_t uMaxASID;
263
264	/** The maximum number of resumes loops allowed in ring-0 (safety precaution).
265	* This number is set much higher when RTThreadPreemptIsPending is reliable. */
266	uint32_t cMaxResumeLoops;
267
268	/** Guest allocated memory for patching purposes. */
269	RTGCPTR pGuestPatchMem;
270	/** Current free pointer inside the patch block. */
271	RTGCPTR pFreeGuestPatchMem;
272	/** Size of the guest patch memory block. */
273	uint32_t cbGuestPatchMem;
274	uint32_t uPadding1;
275
276	#if HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS) && !defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
277	/** 32 to 64 bits switcher entrypoint. */
278	R0PTRTYPE(PFNHMSWITCHERHC) pfnHost32ToGuest64R0;
279
280	/* AMD-V 64 bits vmrun handler */
281	RTRCPTR pfnSVMGCVMRun64;
282
283	/* VT-x 64 bits vmlaunch handler */
284	RTRCPTR pfnVMXGCStartVM64;
285
286	/* RC handler to setup the 64 bits FPU state. */
287	RTRCPTR pfnSaveGuestFPU64;
288
289	/* RC handler to setup the 64 bits debug state. */
290	RTRCPTR pfnSaveGuestDebug64;
291
292	/* Test handler */
293	RTRCPTR pfnTest64;
294
295	RTRCPTR uAlignment[2];
296	/*#elif defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
297	uint32_t u32Alignment[1]; */
298	#endif
299
300	struct
301	{
302	/** Set by the ring-0 side of HM to indicate VMX is supported by the
303	* CPU. */
304	bool fSupported;
305
306	/** Set when we've enabled VMX. */
307	bool fEnabled;
308
309	/** Set if VPID is supported. */
310	bool fVPID;
311
312	/** Set if VT-x VPID is allowed. */
313	bool fAllowVPID;
314
315	/** Set if unrestricted guest execution is allowed (real and protected mode without paging). */
316	bool fUnrestrictedGuest;
317
318	/** Whether we're using the preemption timer or not. */
319	bool fUsePreemptTimer;
320	/** The shift mask employed by the VMX-Preemption timer. */
321	uint8_t cPreemptTimerShift;
322
323	bool uAlignment[1];
324
325	/** Virtual address of the TSS page used for real mode emulation. */
326	R3PTRTYPE(PVBOXTSS) pRealModeTSS;
327
328	/** Virtual address of the identity page table used for real mode and protected mode without paging emulation in EPT mode. */
329	R3PTRTYPE(PX86PD) pNonPagingModeEPTPageTable;
330
331	/** R0 memory object for the APIC physical page (serves for filtering accesses). */
332	RTR0MEMOBJ pMemObjAPIC;
333	/** Physical address of the APIC physical page (serves for filtering accesses). */
334	RTHCPHYS pAPICPhys;
335	/** Virtual address of the APIC physical page (serves for filtering accesses). */
336	R0PTRTYPE(uint8_t *) pAPIC;
337
338	/** R0 memory object for the MSR entry load page (guest MSRs). */
339	RTR0MEMOBJ pMemObjMSREntryLoad;
340	/** Physical address of the MSR entry load page (guest MSRs). */
341	RTHCPHYS pMSREntryLoadPhys;
342	/** Virtual address of the MSR entry load page (guest MSRs). */
343	R0PTRTYPE(uint8_t *) pMSREntryLoad;
344
345	#ifdef VBOX_WITH_CRASHDUMP_MAGIC
346	RTR0MEMOBJ pMemObjScratch;
347	RTHCPHYS pScratchPhys;
348	R0PTRTYPE(uint8_t *) pScratch;
349	#endif
350	/** R0 memory object for the MSR exit store page (guest MSRs). */
351	RTR0MEMOBJ pMemObjMSRExitStore;
352	/** Physical address of the MSR exit store page (guest MSRs). */
353	RTHCPHYS pMSRExitStorePhys;
354	/** Virtual address of the MSR exit store page (guest MSRs). */
355	R0PTRTYPE(uint8_t *) pMSRExitStore;
356
357	/** R0 memory object for the MSR exit load page (host MSRs). */
358	RTR0MEMOBJ pMemObjMSRExitLoad;
359	/** Physical address of the MSR exit load page (host MSRs). */
360	RTHCPHYS pMSRExitLoadPhys;
361	/** Virtual address of the MSR exit load page (host MSRs). */
362	R0PTRTYPE(uint8_t *) pMSRExitLoad;
363
364	/** Ring 0 handlers for VT-x. */
365	DECLR0CALLBACKMEMBER(void, pfnSetupTaggedTLB, (PVM pVM, PVMCPU pVCpu));
366
367	#if HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS)
368	uint32_t u32Alignment;
369	#endif
370	/** Host CR4 value (set by ring-0 VMX init) */
371	uint64_t hostCR4;
372
373	/** Host EFER value (set by ring-0 VMX init) */
374	uint64_t hostEFER;
375
376	/** VMX MSR values */
377	struct
378	{
379	uint64_t feature_ctrl;
380	uint64_t vmx_basic_info;
381	VMX_CAPABILITY vmx_pin_ctls;
382	VMX_CAPABILITY vmx_proc_ctls;
383	VMX_CAPABILITY vmx_proc_ctls2;
384	VMX_CAPABILITY vmx_exit;
385	VMX_CAPABILITY vmx_entry;
386	uint64_t vmx_misc;
387	uint64_t vmx_cr0_fixed0;
388	uint64_t vmx_cr0_fixed1;
389	uint64_t vmx_cr4_fixed0;
390	uint64_t vmx_cr4_fixed1;
391	uint64_t vmx_vmcs_enum;
392	uint64_t vmx_eptcaps;
393	} msr;
394
395	/** Flush types for invept & invvpid; they depend on capabilities. */
396	VMX_FLUSH_EPT enmFlushEPT;
397	VMX_FLUSH_VPID enmFlushVPID;
398	} vmx;
399
400	struct
401	{
402	/** Set by the ring-0 side of HM to indicate SVM is supported by the
403	* CPU. */
404	bool fSupported;
405	/** Set when we've enabled SVM. */
406	bool fEnabled;
407	/** Set if erratum 170 affects the AMD cpu. */
408	bool fAlwaysFlushTLB;
409	/** Set when the hack to ignore VERR_SVM_IN_USE is active. */
410	bool fIgnoreInUseError;
411
412	/** R0 memory object for the IO bitmap (12kb). */
413	RTR0MEMOBJ pMemObjIOBitmap;
414	/** Physical address of the IO bitmap (12kb). */
415	RTHCPHYS pIOBitmapPhys;
416	/** Virtual address of the IO bitmap. */
417	R0PTRTYPE(void *) pIOBitmap;
418
419	/* HWCR msr (for diagnostics) */
420	uint64_t msrHWCR;
421
422	/** SVM revision. */
423	uint32_t u32Rev;
424
425	/** SVM feature bits from cpuid 0x8000000a */
426	uint32_t u32Features;
427	} svm;
428
429	/**
430	* AVL tree with all patches (active or disabled) sorted by guest instruction address
431	*/
432	AVLOU32TREE PatchTree;
433	uint32_t cPatches;
434	HMTPRPATCH aPatches[64];
435
436	struct
437	{
438	uint32_t u32AMDFeatureECX;
439	uint32_t u32AMDFeatureEDX;
440	} cpuid;
441
442	/** Saved error from detection */
443	int32_t lLastError;
444
445	/** HMR0Init was run */
446	bool fHMR0Init;
447	bool u8Alignment1[7];
448
449	STAMCOUNTER StatTPRPatchSuccess;
450	STAMCOUNTER StatTPRPatchFailure;
451	STAMCOUNTER StatTPRReplaceSuccess;
452	STAMCOUNTER StatTPRReplaceFailure;
453	} HM;
454	/** Pointer to HM VM instance data. */
455	typedef HM *PHM;
456
457	/* Maximum number of cached entries. */
458	#define VMCSCACHE_MAX_ENTRY 128
459
460	/* Structure for storing read and write VMCS actions. */
461	typedef struct VMCSCACHE
462	{
463	#ifdef VBOX_WITH_CRASHDUMP_MAGIC
464	/* Magic marker for searching in crash dumps. */
465	uint8_t aMagic[16];
466	uint64_t uMagic;
467	uint64_t u64TimeEntry;
468	uint64_t u64TimeSwitch;
469	uint64_t cResume;
470	uint64_t interPD;
471	uint64_t pSwitcher;
472	uint32_t uPos;
473	uint32_t idCpu;
474	#endif
475	/* CR2 is saved here for EPT syncing. */
476	uint64_t cr2;
477	struct
478	{
479	uint32_t cValidEntries;
480	uint32_t uAlignment;
481	uint32_t aField[VMCSCACHE_MAX_ENTRY];
482	uint64_t aFieldVal[VMCSCACHE_MAX_ENTRY];
483	} Write;
484	struct
485	{
486	uint32_t cValidEntries;
487	uint32_t uAlignment;
488	uint32_t aField[VMCSCACHE_MAX_ENTRY];
489	uint64_t aFieldVal[VMCSCACHE_MAX_ENTRY];
490	} Read;
491	#ifdef DEBUG
492	struct
493	{
494	RTHCPHYS HCPhysCpuPage;
495	RTHCPHYS HCPhysVMCS;
496	RTGCPTR pCache;
497	RTGCPTR pCtx;
498	} TestIn;
499	struct
500	{
501	RTHCPHYS HCPhysVMCS;
502	RTGCPTR pCache;
503	RTGCPTR pCtx;
504	uint64_t eflags;
505	uint64_t cr8;
506	} TestOut;
507	struct
508	{
509	uint64_t param1;
510	uint64_t param2;
511	uint64_t param3;
512	uint64_t param4;
513	} ScratchPad;
514	#endif
515	} VMCSCACHE;
516	/** Pointer to VMCSCACHE. */
517	typedef VMCSCACHE *PVMCSCACHE;
518
519	/** VMX StartVM function. */
520	typedef DECLCALLBACK(int) FNHMVMXSTARTVM(RTHCUINT fResume, PCPUMCTX pCtx, PVMCSCACHE pCache, PVM pVM, PVMCPU pVCpu);
521	/** Pointer to a VMX StartVM function. */
522	typedef R0PTRTYPE(FNHMVMXSTARTVM *) PFNHMVMXSTARTVM;
523
524	/** SVM VMRun function. */
525	typedef DECLCALLBACK(int) FNHMSVMVMRUN(RTHCPHYS pVMCBHostPhys, RTHCPHYS pVMCBPhys, PCPUMCTX pCtx, PVM pVM, PVMCPU pVCpu);
526	/** Pointer to a SVM VMRun function. */
527	typedef R0PTRTYPE(FNHMSVMVMRUN *) PFNHMSVMVMRUN;
528
529	/**
530	* HM VMCPU Instance data.
531	*/
532	typedef struct HMCPU
533	{
534	/** Old style FPU reporting trap mask override performed (optimization) */
535	bool fFPUOldStyleOverride;
536
537	/** Set if we don't have to flush the TLB on VM entry. */
538	bool fResumeVM;
539
540	/** Set if we need to flush the TLB during the world switch. */
541	bool fForceTLBFlush;
542
543	/** Set when we're using VT-x or AMD-V at that moment. */
544	bool fActive;
545
546	/** Set when the TLB has been checked until we return from the world switch. */
547	volatile bool fCheckedTLBFlush;
548	uint8_t bAlignment[3];
549
550	/** World switch exit counter. */
551	volatile uint32_t cWorldSwitchExits;
552
553	/** HM_CHANGED_* flags. */
554	uint32_t fContextUseFlags;
555
556	/** Id of the last cpu we were executing code on (NIL_RTCPUID for the first time) */
557	RTCPUID idLastCpu;
558
559	/** TLB flush count */
560	uint32_t cTLBFlushes;
561
562	/** Current ASID in use by the VM */
563	uint32_t uCurrentASID;
564
565	uint32_t u32Alignment;
566
567	/* Host's TSC_AUX MSR (used when RDTSCP doesn't cause VM-exits). */
568	uint64_t u64HostTSCAux;
569
570	struct
571	{
572	/** Physical address of the VM control structure (VMCS). */
573	RTHCPHYS HCPhysVMCS;
574	/** R0 memory object for the VM control structure (VMCS). */
575	RTR0MEMOBJ hMemObjVMCS;
576	/** Virtual address of the VM control structure (VMCS). */
577	R0PTRTYPE(void *) pvVMCS;
578
579	/** Ring 0 handlers for VT-x. */
580	PFNHMVMXSTARTVM pfnStartVM;
581
582	#if HC_ARCH_BITS == 32
583	uint32_t u32Alignment;
584	#endif
585
586	/** Current VMX_VMCS_CTRL_PROC_EXEC_CONTROLS. */
587	uint64_t proc_ctls;
588
589	/** Current VMX_VMCS_CTRL_PROC_EXEC2_CONTROLS. */
590	uint64_t proc_ctls2;
591
592	/** Physical address of the virtual APIC page for TPR caching. */
593	RTHCPHYS HCPhysVAPIC;
594	/** R0 memory object for the virtual APIC page for TPR caching. */
595	RTR0MEMOBJ hMemObjVAPIC;
596	/** Virtual address of the virtual APIC page for TPR caching. */
597	R0PTRTYPE(uint8_t *) pbVAPIC;
598
599	/** Current CR0 mask. */
600	uint64_t cr0_mask;
601	/** Current CR4 mask. */
602	uint64_t cr4_mask;
603
604	/** Current EPTP. */
605	RTHCPHYS GCPhysEPTP;
606
607	/** Physical address of the MSR bitmap (1 page). */
608	RTHCPHYS pMSRBitmapPhys;
609	/** R0 memory object for the MSR bitmap (1 page). */
610	RTR0MEMOBJ pMemObjMSRBitmap;
611	/** Virtual address of the MSR bitmap (1 page). */
612	R0PTRTYPE(uint8_t *) pMSRBitmap;
613
614	#ifdef VBOX_WITH_AUTO_MSR_LOAD_RESTORE
615	/** Physical address of the guest MSR load area (1 page). */
616	RTHCPHYS pGuestMSRPhys;
617	/** R0 memory object for the guest MSR load area (1 page). */
618	RTR0MEMOBJ pMemObjGuestMSR;
619	/** Virtual address of the guest MSR load area (1 page). */
620	R0PTRTYPE(uint8_t *) pGuestMSR;
621
622	/** Physical address of the MSR load area (1 page). */
623	RTHCPHYS pHostMSRPhys;
624	/** R0 memory object for the MSR load area (1 page). */
625	RTR0MEMOBJ pMemObjHostMSR;
626	/** Virtual address of the MSR load area (1 page). */
627	R0PTRTYPE(uint8_t *) pHostMSR;
628
629	/* Number of automatically loaded/restored guest MSRs during the world switch. */
630	uint32_t cCachedMSRs;
631	uint32_t uAlignment;
632	#endif /* VBOX_WITH_AUTO_MSR_LOAD_RESTORE */
633
634	/* Last use TSC offset value. (cached) */
635	uint64_t u64TSCOffset;
636
637	/** VMCS cache. */
638	VMCSCACHE VMCSCache;
639
640	/** Real-mode emulation state. */
641	struct
642	{
643	X86EFLAGS eflags;
644	uint32_t fValid;
645	} RealMode;
646
647	struct
648	{
649	uint64_t u64VMCSPhys;
650	uint32_t ulVMCSRevision;
651	uint32_t ulInstrError;
652	uint32_t ulExitReason;
653	RTCPUID idEnteredCpu;
654	RTCPUID idCurrentCpu;
655	uint32_t padding;
656	} lasterror;
657
658	/** The last seen guest paging mode (by VT-x). */
659	PGMMODE enmLastSeenGuestMode;
660	/** Current guest paging mode (as seen by HMR3PagingModeChanged). */
661	PGMMODE enmCurrGuestMode;
662	/** Previous guest paging mode (as seen by HMR3PagingModeChanged). */
663	PGMMODE enmPrevGuestMode;
664	} vmx;
665
666	struct
667	{
668	/** R0 memory object for the host VM control block (VMCB). */
669	RTR0MEMOBJ pMemObjVMCBHost;
670	/** Physical address of the host VM control block (VMCB). */
671	RTHCPHYS pVMCBHostPhys;
672	/** Virtual address of the host VM control block (VMCB). */
673	R0PTRTYPE(void *) pVMCBHost;
674
675	/** R0 memory object for the VM control block (VMCB). */
676	RTR0MEMOBJ pMemObjVMCB;
677	/** Physical address of the VM control block (VMCB). */
678	RTHCPHYS pVMCBPhys;
679	/** Virtual address of the VM control block (VMCB). */
680	R0PTRTYPE(void *) pVMCB;
681
682	/** Ring 0 handlers for VT-x. */
683	PFNHMSVMVMRUN pfnVMRun;
684
685	/** R0 memory object for the MSR bitmap (8kb). */
686	RTR0MEMOBJ pMemObjMSRBitmap;
687	/** Physical address of the MSR bitmap (8kb). */
688	RTHCPHYS pMSRBitmapPhys;
689	/** Virtual address of the MSR bitmap. */
690	R0PTRTYPE(void *) pMSRBitmap;
691	} svm;
692
693	/** Event injection state. */
694	struct
695	{
696	uint32_t fPending;
697	uint32_t errCode;
698	uint64_t intInfo;
699	} Event;
700
701	/** IO Block emulation state. */
702	struct
703	{
704	bool fEnabled;
705	uint8_t u8Align[7];
706
707	/** RIP at the start of the io code we wish to emulate in the recompiler. */
708	RTGCPTR GCPtrFunctionEip;
709
710	uint64_t cr0;
711	} EmulateIoBlock;
712
713	struct
714	{
715	/* Pending IO operation type. */
716	HMPENDINGIO enmType;
717	uint32_t uPadding;
718	RTGCPTR GCPtrRip;
719	RTGCPTR GCPtrRipNext;
720	union
721	{
722	struct
723	{
724	unsigned uPort;
725	unsigned uAndVal;
726	unsigned cbSize;
727	} Port;
728	uint64_t aRaw[2];
729	} s;
730	} PendingIO;
731
732	/** Currently shadow paging mode. */
733	PGMMODE enmShadowMode;
734
735	/** The CPU ID of the CPU currently owning the VMCS. Set in
736	* HMR0Enter and cleared in HMR0Leave. */
737	RTCPUID idEnteredCpu;
738
739	/** To keep track of pending TLB shootdown pages. (SMP guest only) */
740	struct
741	{
742	RTGCPTR aPages[HM_MAX_TLB_SHOOTDOWN_PAGES];
743	unsigned cPages;
744	} TlbShootdown;
745
746	/** For saving stack space, the disassembler state is allocated here instead of
747	* on the stack. */
748	DISCPUSTATE DisState;
749
750	uint32_t padding2[1];
751
752	STAMPROFILEADV StatEntry;
753	STAMPROFILEADV StatExit1;
754	STAMPROFILEADV StatExit2;
755	#if 1 /* temporary for tracking down darwin issues. */
756	STAMPROFILEADV StatExit2Sub1;
757	STAMPROFILEADV StatExit2Sub2;
758	STAMPROFILEADV StatExit2Sub3;
759	#endif
760	STAMPROFILEADV StatInGC;
761
762	#if HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS) && !defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
763	STAMPROFILEADV StatWorldSwitch3264;
764	#endif
765	STAMPROFILEADV StatPoke;
766	STAMPROFILEADV StatSpinPoke;
767	STAMPROFILEADV StatSpinPokeFailed;
768
769	STAMCOUNTER StatIntInject;
770
771	STAMCOUNTER StatExitShadowNM;
772	STAMCOUNTER StatExitGuestNM;
773	STAMCOUNTER StatExitShadowPF;
774	STAMCOUNTER StatExitShadowPFEM;
775	STAMCOUNTER StatExitGuestPF;
776	STAMCOUNTER StatExitGuestUD;
777	STAMCOUNTER StatExitGuestSS;
778	STAMCOUNTER StatExitGuestNP;
779	STAMCOUNTER StatExitGuestGP;
780	STAMCOUNTER StatExitGuestDE;
781	STAMCOUNTER StatExitGuestDB;
782	STAMCOUNTER StatExitGuestMF;
783	STAMCOUNTER StatExitGuestBP;
784	STAMCOUNTER StatExitGuestXF;
785	STAMCOUNTER StatExitGuestXcpUnk;
786	STAMCOUNTER StatExitInvlpg;
787	STAMCOUNTER StatExitInvd;
788	STAMCOUNTER StatExitCpuid;
789	STAMCOUNTER StatExitRdtsc;
790	STAMCOUNTER StatExitRdtscp;
791	STAMCOUNTER StatExitRdpmc;
792	STAMCOUNTER StatExitCli;
793	STAMCOUNTER StatExitSti;
794	STAMCOUNTER StatExitPushf;
795	STAMCOUNTER StatExitPopf;
796	STAMCOUNTER StatExitIret;
797	STAMCOUNTER StatExitInt;
798	STAMCOUNTER StatExitCRxWrite[16];
799	STAMCOUNTER StatExitCRxRead[16];
800	STAMCOUNTER StatExitDRxWrite;
801	STAMCOUNTER StatExitDRxRead;
802	STAMCOUNTER StatExitRdmsr;
803	STAMCOUNTER StatExitWrmsr;
804	STAMCOUNTER StatExitCLTS;
805	STAMCOUNTER StatExitHlt;
806	STAMCOUNTER StatExitMwait;
807	STAMCOUNTER StatExitMonitor;
808	STAMCOUNTER StatExitLMSW;
809	STAMCOUNTER StatExitIOWrite;
810	STAMCOUNTER StatExitIORead;
811	STAMCOUNTER StatExitIOStringWrite;
812	STAMCOUNTER StatExitIOStringRead;
813	STAMCOUNTER StatExitIrqWindow;
814	STAMCOUNTER StatExitMaxResume;
815	STAMCOUNTER StatExitPreemptPending;
816	STAMCOUNTER StatExitMTF;
817	STAMCOUNTER StatIntReinject;
818	STAMCOUNTER StatPendingHostIrq;
819
820	STAMCOUNTER StatFlushPage;
821	STAMCOUNTER StatFlushPageManual;
822	STAMCOUNTER StatFlushPhysPageManual;
823	STAMCOUNTER StatFlushTLB;
824	STAMCOUNTER StatFlushTLBManual;
825	STAMCOUNTER StatFlushPageInvlpg;
826	STAMCOUNTER StatFlushTLBWorldSwitch;
827	STAMCOUNTER StatNoFlushTLBWorldSwitch;
828	STAMCOUNTER StatFlushTLBCRxChange;
829	STAMCOUNTER StatFlushASID;
830	STAMCOUNTER StatFlushTLBInvlpga;
831	STAMCOUNTER StatTlbShootdown;
832	STAMCOUNTER StatTlbShootdownFlush;
833
834	STAMCOUNTER StatSwitchGuestIrq;
835	STAMCOUNTER StatSwitchToR3;
836
837	STAMCOUNTER StatTSCOffset;
838	STAMCOUNTER StatTSCIntercept;
839	STAMCOUNTER StatTSCInterceptOverFlow;
840
841	STAMCOUNTER StatExitReasonNPF;
842	STAMCOUNTER StatDRxArmed;
843	STAMCOUNTER StatDRxContextSwitch;
844	STAMCOUNTER StatDRxIOCheck;
845
846	STAMCOUNTER StatLoadMinimal;
847	STAMCOUNTER StatLoadFull;
848
849	#if HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS) && !defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
850	STAMCOUNTER StatFpu64SwitchBack;
851	STAMCOUNTER StatDebug64SwitchBack;
852	#endif
853
854	#ifdef VBOX_WITH_STATISTICS
855	R3PTRTYPE(PSTAMCOUNTER) paStatExitReason;
856	R0PTRTYPE(PSTAMCOUNTER) paStatExitReasonR0;
857	R3PTRTYPE(PSTAMCOUNTER) paStatInjectedIrqs;
858	R0PTRTYPE(PSTAMCOUNTER) paStatInjectedIrqsR0;
859	#endif
860	} HMCPU;
861	/** Pointer to HM VM instance data. */
862	typedef HMCPU *PHMCPU;
863
864
865	#ifdef IN_RING0
866
867	VMMR0DECL(PHMGLOBLCPUINFO) HMR0GetCurrentCpu(void);
868	VMMR0DECL(PHMGLOBLCPUINFO) HMR0GetCurrentCpuEx(RTCPUID idCpu);
869
870
871	#ifdef VBOX_STRICT
872	VMMR0DECL(void) HMDumpRegs(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx);
873	VMMR0DECL(void) HMR0DumpDescriptor(PCX86DESCHC pDesc, RTSEL Sel, const char *pszMsg);
874	#else
875	# define HMDumpRegs(a, b ,c) do { } while (0)
876	# define HMR0DumpDescriptor(a, b, c) do { } while (0)
877	#endif
878
879	# ifdef VBOX_WITH_KERNEL_USING_XMM
880	DECLASM(int) hmR0VMXStartVMWrapXMM(RTHCUINT fResume, PCPUMCTX pCtx, PVMCSCACHE pCache, PVM pVM, PVMCPU pVCpu, PFNHMVMXSTARTVM pfnStartVM);
881	DECLASM(int) hmR0SVMRunWrapXMM(RTHCPHYS pVMCBHostPhys, RTHCPHYS pVMCBPhys, PCPUMCTX pCtx, PVM pVM, PVMCPU pVCpu, PFNHMSVMVMRUN pfnVMRun);
882	# endif
883
884	# ifdef VBOX_WITH_HYBRID_32BIT_KERNEL
885	/**
886	* Gets 64-bit GDTR and IDTR on darwin.
887	* @param pGdtr Where to store the 64-bit GDTR.
888	* @param pIdtr Where to store the 64-bit IDTR.
889	*/
890	DECLASM(void) hmR0Get64bitGDTRandIDTR(PX86XDTR64 pGdtr, PX86XDTR64 pIdtr);
891
892	/**
893	* Gets 64-bit CR3 on darwin.
894	* @returns CR3
895	*/
896	DECLASM(uint64_t) hmR0Get64bitCR3(void);
897	# endif
898
899	#endif /* IN_RING0 */
900
901	/** @} */
902
903	RT_C_DECLS_END
904
905	#endif
906

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source: vbox/trunk/src/VBox/VMM/include/HMInternal.h@ 43413

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