VirtualBox

source: vbox/trunk/src/VBox/VMM/include/HMInternal.h@ 48358

Last change on this file since 48358 was 48284, checked in by vboxsync, 11 years ago

VMM/HMVMXR0: Avoid calling PGM twice for reading just 4 consecutive bytes.
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1/* $Id: HMInternal.h 48284 2013-09-05 00:32:23Z vboxsync $ */
2/** @file
3 * HM - Internal header file.
4 */
5
6/*
7 * Copyright (C) 2006-2013 Oracle Corporation
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 */
17
18#ifndef ___HMInternal_h
19#define ___HMInternal_h
20
21#include <VBox/cdefs.h>
22#include <VBox/types.h>
23#include <VBox/vmm/em.h>
24#include <VBox/vmm/stam.h>
25#include <VBox/dis.h>
26#include <VBox/vmm/hm.h>
27#include <VBox/vmm/hm_vmx.h>
28#include <VBox/vmm/pgm.h>
29#include <VBox/vmm/cpum.h>
30#include <iprt/memobj.h>
31#include <iprt/cpuset.h>
32#include <iprt/mp.h>
33#include <iprt/avl.h>
34
35#if HC_ARCH_BITS == 64 || defined(VBOX_WITH_HYBRID_32BIT_KERNEL) || defined (VBOX_WITH_64_BITS_GUESTS)
36/* Enable 64 bits guest support. */
37# define VBOX_ENABLE_64_BITS_GUESTS
38#endif
39
40#if HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS) && !defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
41# define VMX_USE_CACHED_VMCS_ACCESSES
42#endif
43
44/** @def HM_PROFILE_EXIT_DISPATCH
45 * Enables profiling of the VM exit handler dispatching. */
46#if 0
47# define HM_PROFILE_EXIT_DISPATCH
48#endif
49
50/* The MSR auto load/store used to not work for KERNEL_GS_BASE MSR, thus we
51 * used to handle this MSR manually. See @bugref{6208}. This was clearly visible while
52 * booting Solaris 11 (11.1 b19) VMs with 2 Cpus. This is no longer the case and we
53 * always auto load/store the KERNEL_GS_BASE MSR.
54 *
55 * Note: don't forget to update the assembly files while modifying this!
56 */
57/** @todo This define should always be in effect and the define itself removed
58 after 'sufficient' testing. */
59# define VBOX_WITH_AUTO_MSR_LOAD_RESTORE
60
61RT_C_DECLS_BEGIN
62
63
64/** @defgroup grp_hm_int Internal
65 * @ingroup grp_hm
66 * @internal
67 * @{
68 */
69
70
71/** Maximum number of exit reason statistics counters. */
72#define MAX_EXITREASON_STAT 0x100
73#define MASK_EXITREASON_STAT 0xff
74#define MASK_INJECT_IRQ_STAT 0xff
75
76/** @name HM changed flags.
77 * These flags are used to keep track of which important registers that
78 * have been changed since last they were reset.
79 * @{
80 */
81#define HM_CHANGED_GUEST_CR0 RT_BIT(0)
82#define HM_CHANGED_GUEST_CR3 RT_BIT(1)
83#define HM_CHANGED_GUEST_CR4 RT_BIT(2)
84#define HM_CHANGED_GUEST_GDTR RT_BIT(3)
85#define HM_CHANGED_GUEST_IDTR RT_BIT(4)
86#define HM_CHANGED_GUEST_LDTR RT_BIT(5)
87#define HM_CHANGED_GUEST_TR RT_BIT(6)
88#define HM_CHANGED_GUEST_SEGMENT_REGS RT_BIT(7)
89#define HM_CHANGED_GUEST_DEBUG RT_BIT(8)
90#define HM_CHANGED_GUEST_RIP RT_BIT(9)
91#define HM_CHANGED_GUEST_RSP RT_BIT(10)
92#define HM_CHANGED_GUEST_RFLAGS RT_BIT(11)
93#define HM_CHANGED_GUEST_CR2 RT_BIT(12)
94#define HM_CHANGED_GUEST_SYSENTER_CS_MSR RT_BIT(13)
95#define HM_CHANGED_GUEST_SYSENTER_EIP_MSR RT_BIT(14)
96#define HM_CHANGED_GUEST_SYSENTER_ESP_MSR RT_BIT(15)
97/* VT-x specific state. */
98#define HM_CHANGED_VMX_GUEST_AUTO_MSRS RT_BIT(16)
99#define HM_CHANGED_VMX_GUEST_ACTIVITY_STATE RT_BIT(17)
100#define HM_CHANGED_VMX_GUEST_APIC_STATE RT_BIT(18)
101#define HM_CHANGED_VMX_ENTRY_CTLS RT_BIT(19)
102#define HM_CHANGED_VMX_EXIT_CTLS RT_BIT(20)
103/* AMD-V specific state. */
104#define HM_CHANGED_SVM_GUEST_EFER_MSR RT_BIT(16)
105#define HM_CHANGED_SVM_GUEST_APIC_STATE RT_BIT(17)
106#define HM_CHANGED_SVM_RESERVED1 RT_BIT(18)
107#define HM_CHANGED_SVM_RESERVED2 RT_BIT(19)
108#define HM_CHANGED_SVM_RESERVED3 RT_BIT(20)
109
110#define HM_CHANGED_ALL_GUEST ( HM_CHANGED_GUEST_CR0 \
111 | HM_CHANGED_GUEST_CR3 \
112 | HM_CHANGED_GUEST_CR4 \
113 | HM_CHANGED_GUEST_GDTR \
114 | HM_CHANGED_GUEST_IDTR \
115 | HM_CHANGED_GUEST_LDTR \
116 | HM_CHANGED_GUEST_TR \
117 | HM_CHANGED_GUEST_SEGMENT_REGS \
118 | HM_CHANGED_GUEST_DEBUG \
119 | HM_CHANGED_GUEST_RIP \
120 | HM_CHANGED_GUEST_RSP \
121 | HM_CHANGED_GUEST_RFLAGS \
122 | HM_CHANGED_GUEST_CR2 \
123 | HM_CHANGED_GUEST_SYSENTER_CS_MSR \
124 | HM_CHANGED_GUEST_SYSENTER_EIP_MSR \
125 | HM_CHANGED_GUEST_SYSENTER_ESP_MSR \
126 | HM_CHANGED_VMX_GUEST_AUTO_MSRS \
127 | HM_CHANGED_VMX_GUEST_ACTIVITY_STATE \
128 | HM_CHANGED_VMX_GUEST_APIC_STATE \
129 | HM_CHANGED_VMX_ENTRY_CTLS \
130 | HM_CHANGED_VMX_EXIT_CTLS)
131
132#define HM_CHANGED_HOST_CONTEXT RT_BIT(21)
133
134/* Bits shared between host and guest. */
135#define HM_CHANGED_HOST_GUEST_SHARED_STATE ( HM_CHANGED_GUEST_CR0 \
136 | HM_CHANGED_GUEST_DEBUG)
137/** @} */
138
139/** Maximum number of page flushes we are willing to remember before considering a full TLB flush. */
140#define HM_MAX_TLB_SHOOTDOWN_PAGES 8
141
142/** Size for the EPT identity page table (1024 4 MB pages to cover the entire address space). */
143#define HM_EPT_IDENTITY_PG_TABLE_SIZE PAGE_SIZE
144/** Size of the TSS structure + 2 pages for the IO bitmap + end byte. */
145#define HM_VTX_TSS_SIZE (sizeof(VBOXTSS) + 2 * PAGE_SIZE + 1)
146/** Total guest mapped memory needed. */
147#define HM_VTX_TOTAL_DEVHEAP_MEM (HM_EPT_IDENTITY_PG_TABLE_SIZE + HM_VTX_TSS_SIZE)
148
149/** Enable for TPR guest patching. */
150#define VBOX_HM_WITH_GUEST_PATCHING
151
152/** HM SSM version
153 */
154#ifdef VBOX_HM_WITH_GUEST_PATCHING
155# define HM_SSM_VERSION 5
156# define HM_SSM_VERSION_NO_PATCHING 4
157#else
158# define HM_SSM_VERSION 4
159# define HM_SSM_VERSION_NO_PATCHING 4
160#endif
161#define HM_SSM_VERSION_2_0_X 3
162
163/**
164 * Global per-cpu information. (host)
165 */
166typedef struct HMGLOBALCPUINFO
167{
168 /** The CPU ID. */
169 RTCPUID idCpu;
170 /** The memory object */
171 RTR0MEMOBJ hMemObj;
172 /** Current ASID (AMD-V) / VPID (Intel). */
173 uint32_t uCurrentAsid;
174 /** TLB flush count. */
175 uint32_t cTlbFlushes;
176 /** Whether to flush each new ASID/VPID before use. */
177 bool fFlushAsidBeforeUse;
178 /** Configured for VT-x or AMD-V. */
179 bool fConfigured;
180 /** Set if the VBOX_HWVIRTEX_IGNORE_SVM_IN_USE hack is active. */
181 bool fIgnoreAMDVInUseError;
182 /** In use by our code. (for power suspend) */
183 volatile bool fInUse;
184} HMGLOBALCPUINFO;
185/** Pointer to the per-cpu global information. */
186typedef HMGLOBALCPUINFO *PHMGLOBALCPUINFO;
187
188typedef enum
189{
190 HMPENDINGIO_INVALID = 0,
191 HMPENDINGIO_PORT_READ,
192 HMPENDINGIO_PORT_WRITE,
193 HMPENDINGIO_STRING_READ,
194 HMPENDINGIO_STRING_WRITE,
195 /** The usual 32-bit paranoia. */
196 HMPENDINGIO_32BIT_HACK = 0x7fffffff
197} HMPENDINGIO;
198
199
200typedef enum
201{
202 HMTPRINSTR_INVALID,
203 HMTPRINSTR_READ,
204 HMTPRINSTR_READ_SHR4,
205 HMTPRINSTR_WRITE_REG,
206 HMTPRINSTR_WRITE_IMM,
207 HMTPRINSTR_JUMP_REPLACEMENT,
208 /** The usual 32-bit paranoia. */
209 HMTPRINSTR_32BIT_HACK = 0x7fffffff
210} HMTPRINSTR;
211
212typedef struct
213{
214 /** The key is the address of patched instruction. (32 bits GC ptr) */
215 AVLOU32NODECORE Core;
216 /** Original opcode. */
217 uint8_t aOpcode[16];
218 /** Instruction size. */
219 uint32_t cbOp;
220 /** Replacement opcode. */
221 uint8_t aNewOpcode[16];
222 /** Replacement instruction size. */
223 uint32_t cbNewOp;
224 /** Instruction type. */
225 HMTPRINSTR enmType;
226 /** Source operand. */
227 uint32_t uSrcOperand;
228 /** Destination operand. */
229 uint32_t uDstOperand;
230 /** Number of times the instruction caused a fault. */
231 uint32_t cFaults;
232 /** Patch address of the jump replacement. */
233 RTGCPTR32 pJumpTarget;
234} HMTPRPATCH;
235/** Pointer to HMTPRPATCH. */
236typedef HMTPRPATCH *PHMTPRPATCH;
237
238/**
239 * Switcher function, HC to the special 64-bit RC.
240 *
241 * @param pVM Pointer to the VM.
242 * @param offCpumVCpu Offset from pVM->cpum to pVM->aCpus[idCpu].cpum.
243 * @returns Return code indicating the action to take.
244 */
245typedef DECLCALLBACK(int) FNHMSWITCHERHC(PVM pVM, uint32_t offCpumVCpu);
246/** Pointer to switcher function. */
247typedef FNHMSWITCHERHC *PFNHMSWITCHERHC;
248
249/**
250 * HM VM Instance data.
251 * Changes to this must checked against the padding of the hm union in VM!
252 */
253typedef struct HM
254{
255 /** Set when we've initialized VMX or SVM. */
256 bool fInitialized;
257
258 /** Set if nested paging is enabled. */
259 bool fNestedPaging;
260
261 /** Set if nested paging is allowed. */
262 bool fAllowNestedPaging;
263
264 /** Set if large pages are enabled (requires nested paging). */
265 bool fLargePages;
266
267 /** Set if we can support 64-bit guests or not. */
268 bool fAllow64BitGuests;
269
270 /** Set if an IO-APIC is configured for this VM. */
271 bool fHasIoApic;
272
273 /** Set when TPR patching is allowed. */
274 bool fTRPPatchingAllowed;
275
276 /** Set when we initialize VT-x or AMD-V once for all CPUs. */
277 bool fGlobalInit;
278
279 /** Set when TPR patching is active. */
280 bool fTPRPatchingActive;
281 bool u8Alignment[7];
282
283 /** Maximum ASID allowed. */
284 uint32_t uMaxAsid;
285
286 /** The maximum number of resumes loops allowed in ring-0 (safety precaution).
287 * This number is set much higher when RTThreadPreemptIsPending is reliable. */
288 uint32_t cMaxResumeLoops;
289
290 /** Guest allocated memory for patching purposes. */
291 RTGCPTR pGuestPatchMem;
292 /** Current free pointer inside the patch block. */
293 RTGCPTR pFreeGuestPatchMem;
294 /** Size of the guest patch memory block. */
295 uint32_t cbGuestPatchMem;
296 uint32_t uPadding1;
297
298#if HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS) && !defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
299 /** 32 to 64 bits switcher entrypoint. */
300 R0PTRTYPE(PFNHMSWITCHERHC) pfnHost32ToGuest64R0;
301 RTR0PTR uPadding2;
302#endif
303
304 struct
305 {
306 /** Set by the ring-0 side of HM to indicate VMX is supported by the
307 * CPU. */
308 bool fSupported;
309
310 /** Set when we've enabled VMX. */
311 bool fEnabled;
312
313 /** Set if VPID is supported. */
314 bool fVpid;
315
316 /** Set if VT-x VPID is allowed. */
317 bool fAllowVpid;
318
319 /** Set if unrestricted guest execution is in use (real and protected mode without paging). */
320 bool fUnrestrictedGuest;
321
322 /** Set if unrestricted guest execution is allowed to be used. */
323 bool fAllowUnrestricted;
324
325 /** Whether we're using the preemption timer or not. */
326 bool fUsePreemptTimer;
327 /** The shift mask employed by the VMX-Preemption timer. */
328 uint8_t cPreemptTimerShift;
329
330 /** Virtual address of the TSS page used for real mode emulation. */
331 R3PTRTYPE(PVBOXTSS) pRealModeTSS;
332
333 /** Virtual address of the identity page table used for real mode and protected mode without paging emulation in EPT mode. */
334 R3PTRTYPE(PX86PD) pNonPagingModeEPTPageTable;
335
336 /** R0 memory object for the APIC-access page. */
337 RTR0MEMOBJ hMemObjApicAccess;
338 /** Physical address of the APIC-access page. */
339 RTHCPHYS HCPhysApicAccess;
340 /** Virtual address of the APIC-access page. */
341 R0PTRTYPE(uint8_t *) pbApicAccess;
342
343#ifdef VBOX_WITH_CRASHDUMP_MAGIC
344 RTR0MEMOBJ hMemObjScratch;
345 RTHCPHYS HCPhysScratch;
346 R0PTRTYPE(uint8_t *) pbScratch;
347#endif
348
349 /** Internal Id of which flush-handler to use for tagged-TLB entries. */
350 unsigned uFlushTaggedTlb;
351
352#if HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS)
353 uint32_t u32Alignment;
354#endif
355 /** Host CR4 value (set by ring-0 VMX init) */
356 uint64_t u64HostCr4;
357
358 /** Host EFER value (set by ring-0 VMX init) */
359 uint64_t u64HostEfer;
360
361 /** VMX MSR values */
362 VMXMSRS Msrs;
363
364 /** Flush types for invept & invvpid; they depend on capabilities. */
365 VMX_FLUSH_EPT enmFlushEpt;
366 VMX_FLUSH_VPID enmFlushVpid;
367 } vmx;
368
369 struct
370 {
371 /** Set by the ring-0 side of HM to indicate SVM is supported by the
372 * CPU. */
373 bool fSupported;
374 /** Set when we've enabled SVM. */
375 bool fEnabled;
376 /** Set if erratum 170 affects the AMD cpu. */
377 bool fAlwaysFlushTLB;
378 /** Set when the hack to ignore VERR_SVM_IN_USE is active. */
379 bool fIgnoreInUseError;
380
381 /** R0 memory object for the IO bitmap (12kb). */
382 RTR0MEMOBJ hMemObjIOBitmap;
383 /** Physical address of the IO bitmap (12kb). */
384 RTHCPHYS HCPhysIOBitmap;
385 /** Virtual address of the IO bitmap. */
386 R0PTRTYPE(void *) pvIOBitmap;
387
388 /* HWCR MSR (for diagnostics) */
389 uint64_t u64MsrHwcr;
390
391 /** SVM revision. */
392 uint32_t u32Rev;
393
394 /** SVM feature bits from cpuid 0x8000000a */
395 uint32_t u32Features;
396 } svm;
397
398 /**
399 * AVL tree with all patches (active or disabled) sorted by guest instruction address
400 */
401 AVLOU32TREE PatchTree;
402 uint32_t cPatches;
403 HMTPRPATCH aPatches[64];
404
405 struct
406 {
407 uint32_t u32AMDFeatureECX;
408 uint32_t u32AMDFeatureEDX;
409 } cpuid;
410
411 /** Saved error from detection */
412 int32_t lLastError;
413
414 /** HMR0Init was run */
415 bool fHMR0Init;
416 bool u8Alignment1[7];
417
418 STAMCOUNTER StatTprPatchSuccess;
419 STAMCOUNTER StatTprPatchFailure;
420 STAMCOUNTER StatTprReplaceSuccess;
421 STAMCOUNTER StatTprReplaceFailure;
422} HM;
423/** Pointer to HM VM instance data. */
424typedef HM *PHM;
425
426/* Maximum number of cached entries. */
427#define VMCSCACHE_MAX_ENTRY 128
428
429/* Structure for storing read and write VMCS actions. */
430typedef struct VMCSCACHE
431{
432#ifdef VBOX_WITH_CRASHDUMP_MAGIC
433 /* Magic marker for searching in crash dumps. */
434 uint8_t aMagic[16];
435 uint64_t uMagic;
436 uint64_t u64TimeEntry;
437 uint64_t u64TimeSwitch;
438 uint64_t cResume;
439 uint64_t interPD;
440 uint64_t pSwitcher;
441 uint32_t uPos;
442 uint32_t idCpu;
443#endif
444 /* CR2 is saved here for EPT syncing. */
445 uint64_t cr2;
446 struct
447 {
448 uint32_t cValidEntries;
449 uint32_t uAlignment;
450 uint32_t aField[VMCSCACHE_MAX_ENTRY];
451 uint64_t aFieldVal[VMCSCACHE_MAX_ENTRY];
452 } Write;
453 struct
454 {
455 uint32_t cValidEntries;
456 uint32_t uAlignment;
457 uint32_t aField[VMCSCACHE_MAX_ENTRY];
458 uint64_t aFieldVal[VMCSCACHE_MAX_ENTRY];
459 } Read;
460#ifdef VBOX_STRICT
461 struct
462 {
463 RTHCPHYS HCPhysCpuPage;
464 RTHCPHYS HCPhysVmcs;
465 RTGCPTR pCache;
466 RTGCPTR pCtx;
467 } TestIn;
468 struct
469 {
470 RTHCPHYS HCPhysVmcs;
471 RTGCPTR pCache;
472 RTGCPTR pCtx;
473 uint64_t eflags;
474 uint64_t cr8;
475 } TestOut;
476 struct
477 {
478 uint64_t param1;
479 uint64_t param2;
480 uint64_t param3;
481 uint64_t param4;
482 } ScratchPad;
483#endif
484} VMCSCACHE;
485/** Pointer to VMCSCACHE. */
486typedef VMCSCACHE *PVMCSCACHE;
487
488/** VMX StartVM function. */
489typedef DECLCALLBACK(int) FNHMVMXSTARTVM(RTHCUINT fResume, PCPUMCTX pCtx, PVMCSCACHE pCache, PVM pVM, PVMCPU pVCpu);
490/** Pointer to a VMX StartVM function. */
491typedef R0PTRTYPE(FNHMVMXSTARTVM *) PFNHMVMXSTARTVM;
492
493/** SVM VMRun function. */
494typedef DECLCALLBACK(int) FNHMSVMVMRUN(RTHCPHYS pVmcbHostPhys, RTHCPHYS pVmcbPhys, PCPUMCTX pCtx, PVM pVM, PVMCPU pVCpu);
495/** Pointer to a SVM VMRun function. */
496typedef R0PTRTYPE(FNHMSVMVMRUN *) PFNHMSVMVMRUN;
497
498/**
499 * HM VMCPU Instance data.
500 */
501typedef struct HMCPU
502{
503 /** Set if we need to flush the TLB during the world switch. */
504 bool fForceTLBFlush;
505 /** Set when we're using VT-x or AMD-V at that moment. */
506 bool fActive;
507 /** Set when the TLB has been checked until we return from the world switch. */
508 volatile bool fCheckedTLBFlush;
509 /** Whether we're executing a single instruction. */
510 bool fSingleInstruction;
511 /** Set if we need to clear the trap flag because of single stepping. */
512 bool fClearTrapFlag;
513 /** Whether we've completed the inner HM leave function. */
514 bool fLeaveDone;
515 uint8_t abAlignment[2];
516
517 /** World switch exit counter. */
518 volatile uint32_t cWorldSwitchExits;
519 /** HM_CHANGED_* flags. */
520 uint32_t fContextUseFlags;
521 /** Id of the last cpu we were executing code on (NIL_RTCPUID for the first
522 * time). */
523 RTCPUID idLastCpu;
524 /** TLB flush count. */
525 uint32_t cTlbFlushes;
526 /** Current ASID in use by the VM. */
527 uint32_t uCurrentAsid;
528 /** An additional error code used for some gurus. */
529 uint32_t u32HMError;
530 /** Host's TSC_AUX MSR (used when RDTSCP doesn't cause VM-exits). */
531 uint64_t u64HostTscAux;
532
533 struct
534 {
535 /** Physical address of the VM control structure (VMCS). */
536 RTHCPHYS HCPhysVmcs;
537 /** R0 memory object for the VM control structure (VMCS). */
538 RTR0MEMOBJ hMemObjVmcs;
539 /** Virtual address of the VM control structure (VMCS). */
540 R0PTRTYPE(void *) pvVmcs;
541 /** Ring 0 handlers for VT-x. */
542 PFNHMVMXSTARTVM pfnStartVM;
543#if HC_ARCH_BITS == 32
544 uint32_t u32Alignment1;
545#endif
546
547 /** Current VMX_VMCS32_CTRL_PIN_EXEC. */
548 uint32_t u32PinCtls;
549 /** Current VMX_VMCS32_CTRL_PROC_EXEC. */
550 uint32_t u32ProcCtls;
551 /** Current VMX_VMCS32_CTRL_PROC_EXEC2. */
552 uint32_t u32ProcCtls2;
553 /** Current VMX_VMCS32_CTRL_EXIT. */
554 uint32_t u32ExitCtls;
555 /** Current VMX_VMCS32_CTRL_ENTRY. */
556 uint32_t u32EntryCtls;
557
558 /** Physical address of the virtual APIC page for TPR caching. */
559 RTHCPHYS HCPhysVirtApic;
560 /** R0 memory object for the virtual APIC page for TPR caching. */
561 RTR0MEMOBJ hMemObjVirtApic;
562 /** Virtual address of the virtual APIC page for TPR caching. */
563 R0PTRTYPE(uint8_t *) pbVirtApic;
564#if HC_ARCH_BITS == 32
565 uint32_t u32Alignment2;
566#endif
567
568 /** Current CR0 mask. */
569 uint32_t u32CR0Mask;
570 /** Current CR4 mask. */
571 uint32_t u32CR4Mask;
572 /** Current exception bitmap. */
573 uint32_t u32XcptBitmap;
574 /** The updated-guest-state mask. */
575 uint32_t fUpdatedGuestState;
576 /** Current EPTP. */
577 RTHCPHYS HCPhysEPTP;
578
579 /** Physical address of the MSR bitmap. */
580 RTHCPHYS HCPhysMsrBitmap;
581 /** R0 memory object for the MSR bitmap. */
582 RTR0MEMOBJ hMemObjMsrBitmap;
583 /** Virtual address of the MSR bitmap. */
584 R0PTRTYPE(void *) pvMsrBitmap;
585
586#ifdef VBOX_WITH_AUTO_MSR_LOAD_RESTORE
587 /** Physical address of the VM-entry MSR-load and VM-exit MSR-store area (used
588 * for guest MSRs). */
589 RTHCPHYS HCPhysGuestMsr;
590 /** R0 memory object of the VM-entry MSR-load and VM-exit MSR-store area
591 * (used for guest MSRs). */
592 RTR0MEMOBJ hMemObjGuestMsr;
593 /** Virtual address of the VM-entry MSR-load and VM-exit MSR-store area (used
594 * for guest MSRs). */
595 R0PTRTYPE(void *) pvGuestMsr;
596
597 /** Physical address of the VM-exit MSR-load area (used for host MSRs). */
598 RTHCPHYS HCPhysHostMsr;
599 /** R0 memory object for the VM-exit MSR-load area (used for host MSRs). */
600 RTR0MEMOBJ hMemObjHostMsr;
601 /** Virtual address of the VM-exit MSR-load area (used for host MSRs). */
602 R0PTRTYPE(void *) pvHostMsr;
603
604 /** Number of automatically loaded/restored guest MSRs during the world switch. */
605 uint32_t cGuestMsrs;
606 uint32_t uAlignment;
607#endif /* VBOX_WITH_AUTO_MSR_LOAD_RESTORE */
608
609 /** The cached APIC-base MSR used for identifying when to map the HC physical APIC-access page. */
610 uint64_t u64MsrApicBase;
611 /** Last use TSC offset value. (cached) */
612 uint64_t u64TSCOffset;
613
614 /** VMCS cache. */
615 VMCSCACHE VMCSCache;
616
617 /** Real-mode emulation state. */
618 struct
619 {
620 X86DESCATTR AttrCS;
621 X86DESCATTR AttrDS;
622 X86DESCATTR AttrES;
623 X86DESCATTR AttrFS;
624 X86DESCATTR AttrGS;
625 X86DESCATTR AttrSS;
626 X86EFLAGS Eflags;
627 uint32_t fRealOnV86Active;
628 } RealMode;
629
630 struct
631 {
632 uint64_t u64VMCSPhys;
633 uint32_t u32VMCSRevision;
634 uint32_t u32InstrError;
635 uint32_t u32ExitReason;
636 RTCPUID idEnteredCpu;
637 RTCPUID idCurrentCpu;
638 uint32_t u32Padding;
639 } LastError;
640
641 /** State of the VMCS. */
642 uint32_t uVmcsState;
643 /** Which host-state bits to restore before being preempted. */
644 uint32_t fRestoreHostFlags;
645 /** The host-state restoration structure. */
646 VMXRESTOREHOST RestoreHost;
647 /** Set if guest was executing in real mode (extra checks). */
648 bool fWasInRealMode;
649 /** Padding. */
650 uint32_t u32Padding;
651 } vmx;
652
653 struct
654 {
655 /** R0 memory object for the host VMCB which holds additional host-state. */
656 RTR0MEMOBJ hMemObjVmcbHost;
657 /** Physical address of the host VMCB which holds additional host-state. */
658 RTHCPHYS HCPhysVmcbHost;
659 /** Virtual address of the host VMCB which holds additional host-state. */
660 R0PTRTYPE(void *) pvVmcbHost;
661
662 /** R0 memory object for the guest VMCB. */
663 RTR0MEMOBJ hMemObjVmcb;
664 /** Physical address of the guest VMCB. */
665 RTHCPHYS HCPhysVmcb;
666 /** Virtual address of the guest VMCB. */
667 R0PTRTYPE(void *) pvVmcb;
668
669 /** Ring 0 handlers for VT-x. */
670 PFNHMSVMVMRUN pfnVMRun;
671
672 /** R0 memory object for the MSR bitmap (8 KB). */
673 RTR0MEMOBJ hMemObjMsrBitmap;
674 /** Physical address of the MSR bitmap (8 KB). */
675 RTHCPHYS HCPhysMsrBitmap;
676 /** Virtual address of the MSR bitmap. */
677 R0PTRTYPE(void *) pvMsrBitmap;
678
679 /** Whether VTPR with V_INTR_MASKING set is in effect, indicating
680 * we should check if the VTPR changed on every VM-exit. */
681 bool fSyncVTpr;
682 uint8_t u8Align[7];
683
684 /** Alignment padding. */
685 uint32_t u32Padding;
686 } svm;
687
688 /** Event injection state. */
689 struct
690 {
691 uint32_t fPending;
692 uint32_t u32ErrCode;
693 uint32_t cbInstr;
694 uint32_t u32Padding; /**< Explicit alignment padding. */
695 uint64_t u64IntrInfo;
696 RTGCUINTPTR GCPtrFaultAddress;
697 } Event;
698
699 /** IO Block emulation state. */
700 struct
701 {
702 bool fEnabled;
703 uint8_t u8Align[7];
704
705 /** RIP at the start of the io code we wish to emulate in the recompiler. */
706 RTGCPTR GCPtrFunctionEip;
707
708 uint64_t cr0;
709 } EmulateIoBlock;
710
711 struct
712 {
713 /** Pending IO operation type. */
714 HMPENDINGIO enmType;
715 uint32_t uPadding;
716 RTGCPTR GCPtrRip;
717 RTGCPTR GCPtrRipNext;
718 union
719 {
720 struct
721 {
722 uint32_t uPort;
723 uint32_t uAndVal;
724 uint32_t cbSize;
725 } Port;
726 uint64_t aRaw[2];
727 } s;
728 } PendingIO;
729
730 /** The PAE PDPEs used with Nested Paging (only valid when
731 * VMCPU_FF_HM_UPDATE_PAE_PDPES is set). */
732 X86PDPE aPdpes[4];
733
734 /** Current shadow paging mode. */
735 PGMMODE enmShadowMode;
736
737 /** The CPU ID of the CPU currently owning the VMCS. Set in
738 * HMR0Enter and cleared in HMR0Leave. */
739 RTCPUID idEnteredCpu;
740
741 /** To keep track of pending TLB shootdown pages. (SMP guest only) */
742 struct
743 {
744 RTGCPTR aPages[HM_MAX_TLB_SHOOTDOWN_PAGES];
745 uint32_t cPages;
746 uint32_t u32Padding; /**< Explicit alignment padding. */
747 } TlbShootdown;
748
749 /** For saving stack space, the disassembler state is allocated here instead of
750 * on the stack. */
751 DISCPUSTATE DisState;
752
753 STAMPROFILEADV StatEntry;
754 STAMPROFILEADV StatExit1;
755 STAMPROFILEADV StatExit2;
756 STAMPROFILEADV StatExitIO;
757 STAMPROFILEADV StatExitMovCRx;
758 STAMPROFILEADV StatExitXcptNmi;
759 STAMPROFILEADV StatLoadGuestState;
760 STAMPROFILEADV StatInGC;
761
762#if HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS) && !defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
763 STAMPROFILEADV StatWorldSwitch3264;
764#endif
765 STAMPROFILEADV StatPoke;
766 STAMPROFILEADV StatSpinPoke;
767 STAMPROFILEADV StatSpinPokeFailed;
768
769 STAMCOUNTER StatInjectInterrupt;
770 STAMCOUNTER StatInjectXcpt;
771 STAMCOUNTER StatInjectPendingReflect;
772
773 STAMCOUNTER StatExitShadowNM;
774 STAMCOUNTER StatExitGuestNM;
775 STAMCOUNTER StatExitShadowPF; /* Misleading, currently used for MMIO #PFs as well. */
776 STAMCOUNTER StatExitShadowPFEM;
777 STAMCOUNTER StatExitGuestPF;
778 STAMCOUNTER StatExitGuestUD;
779 STAMCOUNTER StatExitGuestSS;
780 STAMCOUNTER StatExitGuestNP;
781 STAMCOUNTER StatExitGuestGP;
782 STAMCOUNTER StatExitGuestDE;
783 STAMCOUNTER StatExitGuestDB;
784 STAMCOUNTER StatExitGuestMF;
785 STAMCOUNTER StatExitGuestBP;
786 STAMCOUNTER StatExitGuestXF;
787 STAMCOUNTER StatExitGuestXcpUnk;
788 STAMCOUNTER StatExitInvlpg;
789 STAMCOUNTER StatExitInvd;
790 STAMCOUNTER StatExitWbinvd;
791 STAMCOUNTER StatExitPause;
792 STAMCOUNTER StatExitCpuid;
793 STAMCOUNTER StatExitRdtsc;
794 STAMCOUNTER StatExitRdtscp;
795 STAMCOUNTER StatExitRdpmc;
796 STAMCOUNTER StatExitRdrand;
797 STAMCOUNTER StatExitCli;
798 STAMCOUNTER StatExitSti;
799 STAMCOUNTER StatExitPushf;
800 STAMCOUNTER StatExitPopf;
801 STAMCOUNTER StatExitIret;
802 STAMCOUNTER StatExitInt;
803 STAMCOUNTER StatExitCRxWrite[16];
804 STAMCOUNTER StatExitCRxRead[16];
805 STAMCOUNTER StatExitDRxWrite;
806 STAMCOUNTER StatExitDRxRead;
807 STAMCOUNTER StatExitRdmsr;
808 STAMCOUNTER StatExitWrmsr;
809 STAMCOUNTER StatExitClts;
810 STAMCOUNTER StatExitXdtrAccess;
811 STAMCOUNTER StatExitHlt;
812 STAMCOUNTER StatExitMwait;
813 STAMCOUNTER StatExitMonitor;
814 STAMCOUNTER StatExitLmsw;
815 STAMCOUNTER StatExitIOWrite;
816 STAMCOUNTER StatExitIORead;
817 STAMCOUNTER StatExitIOStringWrite;
818 STAMCOUNTER StatExitIOStringRead;
819 STAMCOUNTER StatExitIntWindow;
820 STAMCOUNTER StatExitMaxResume;
821 STAMCOUNTER StatExitExtInt;
822 STAMCOUNTER StatExitHostNmiInGC;
823 STAMCOUNTER StatExitPreemptTimer;
824 STAMCOUNTER StatExitTprBelowThreshold;
825 STAMCOUNTER StatExitTaskSwitch;
826 STAMCOUNTER StatExitMtf;
827 STAMCOUNTER StatExitApicAccess;
828 STAMCOUNTER StatPendingHostIrq;
829
830 STAMCOUNTER StatPreemptPreempting;
831 STAMCOUNTER StatPreemptSaveHostState;
832
833 STAMCOUNTER StatFlushPage;
834 STAMCOUNTER StatFlushPageManual;
835 STAMCOUNTER StatFlushPhysPageManual;
836 STAMCOUNTER StatFlushTlb;
837 STAMCOUNTER StatFlushTlbManual;
838 STAMCOUNTER StatFlushTlbWorldSwitch;
839 STAMCOUNTER StatNoFlushTlbWorldSwitch;
840 STAMCOUNTER StatFlushEntire;
841 STAMCOUNTER StatFlushAsid;
842 STAMCOUNTER StatFlushNestedPaging;
843 STAMCOUNTER StatFlushTlbInvlpgVirt;
844 STAMCOUNTER StatFlushTlbInvlpgPhys;
845 STAMCOUNTER StatTlbShootdown;
846 STAMCOUNTER StatTlbShootdownFlush;
847
848 STAMCOUNTER StatSwitchGuestIrq;
849 STAMCOUNTER StatSwitchHmToR3FF;
850 STAMCOUNTER StatSwitchExitToR3;
851 STAMCOUNTER StatSwitchLongJmpToR3;
852
853 STAMCOUNTER StatTscOffset;
854 STAMCOUNTER StatTscIntercept;
855 STAMCOUNTER StatTscInterceptOverFlow;
856
857 STAMCOUNTER StatExitReasonNpf;
858 STAMCOUNTER StatDRxArmed;
859 STAMCOUNTER StatDRxContextSwitch;
860 STAMCOUNTER StatDRxIoCheck;
861
862 STAMCOUNTER StatLoadMinimal;
863 STAMCOUNTER StatLoadFull;
864
865 STAMCOUNTER StatVmxCheckBadRmSelBase;
866 STAMCOUNTER StatVmxCheckBadRmSelLimit;
867 STAMCOUNTER StatVmxCheckRmOk;
868
869 STAMCOUNTER StatVmxCheckBadSel;
870 STAMCOUNTER StatVmxCheckBadRpl;
871 STAMCOUNTER StatVmxCheckBadLdt;
872 STAMCOUNTER StatVmxCheckBadTr;
873 STAMCOUNTER StatVmxCheckPmOk;
874
875#if HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS) && !defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
876 STAMCOUNTER StatFpu64SwitchBack;
877 STAMCOUNTER StatDebug64SwitchBack;
878#endif
879
880#ifdef VBOX_WITH_STATISTICS
881 R3PTRTYPE(PSTAMCOUNTER) paStatExitReason;
882 R0PTRTYPE(PSTAMCOUNTER) paStatExitReasonR0;
883 R3PTRTYPE(PSTAMCOUNTER) paStatInjectedIrqs;
884 R0PTRTYPE(PSTAMCOUNTER) paStatInjectedIrqsR0;
885#endif
886#ifdef HM_PROFILE_EXIT_DISPATCH
887 STAMPROFILEADV StatExitDispatch;
888#endif
889} HMCPU;
890/** Pointer to HM VM instance data. */
891typedef HMCPU *PHMCPU;
892
893
894#ifdef IN_RING0
895
896VMMR0DECL(PHMGLOBALCPUINFO) HMR0GetCurrentCpu(void);
897VMMR0DECL(PHMGLOBALCPUINFO) HMR0GetCurrentCpuEx(RTCPUID idCpu);
898
899
900#ifdef VBOX_STRICT
901VMMR0DECL(void) HMDumpRegs(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx);
902VMMR0DECL(void) HMR0DumpDescriptor(PCX86DESCHC pDesc, RTSEL Sel, const char *pszMsg);
903#else
904# define HMDumpRegs(a, b ,c) do { } while (0)
905# define HMR0DumpDescriptor(a, b, c) do { } while (0)
906#endif
907
908# ifdef VBOX_WITH_KERNEL_USING_XMM
909DECLASM(int) HMR0VMXStartVMWrapXMM(RTHCUINT fResume, PCPUMCTX pCtx, PVMCSCACHE pCache, PVM pVM, PVMCPU pVCpu, PFNHMVMXSTARTVM pfnStartVM);
910DECLASM(int) HMR0SVMRunWrapXMM(RTHCPHYS pVmcbHostPhys, RTHCPHYS pVmcbPhys, PCPUMCTX pCtx, PVM pVM, PVMCPU pVCpu, PFNHMSVMVMRUN pfnVMRun);
911# endif
912
913# ifdef VBOX_WITH_HYBRID_32BIT_KERNEL
914/**
915 * Gets 64-bit GDTR and IDTR on darwin.
916 * @param pGdtr Where to store the 64-bit GDTR.
917 * @param pIdtr Where to store the 64-bit IDTR.
918 */
919DECLASM(void) HMR0Get64bitGdtrAndIdtr(PX86XDTR64 pGdtr, PX86XDTR64 pIdtr);
920
921/**
922 * Gets 64-bit CR3 on darwin.
923 * @returns CR3
924 */
925DECLASM(uint64_t) HMR0Get64bitCR3(void);
926# endif
927
928#endif /* IN_RING0 */
929
930/** @} */
931
932RT_C_DECLS_END
933
934#endif
935
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