HMInternal.h@ 48756

Last change on this file since 48756 was 48570, checked in by vboxsync, 11 years ago
VMM/HMVMXR0, HMSVMR0: Restore hyper/guest DR7 in accordance with what we load.
Property svn:eol-style set to `native` Property svn:keywords set to `Id`
File size: 34.7 KB

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1	/* $Id: HMInternal.h 48570 2013-09-19 23:41:35Z vboxsync $ */
2	/** @file
3	* HM - Internal header file.
4	*/
5
6	/*
7	* Copyright (C) 2006-2013 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*/
17
18	#ifndef ___HMInternal_h
19	#define ___HMInternal_h
20
21	#include <VBox/cdefs.h>
22	#include <VBox/types.h>
23	#include <VBox/vmm/em.h>
24	#include <VBox/vmm/stam.h>
25	#include <VBox/dis.h>
26	#include <VBox/vmm/hm.h>
27	#include <VBox/vmm/hm_vmx.h>
28	#include <VBox/vmm/pgm.h>
29	#include <VBox/vmm/cpum.h>
30	#include <iprt/memobj.h>
31	#include <iprt/cpuset.h>
32	#include <iprt/mp.h>
33	#include <iprt/avl.h>
34
35	#if HC_ARCH_BITS == 64 \|\| defined(VBOX_WITH_HYBRID_32BIT_KERNEL) \|\| defined (VBOX_WITH_64_BITS_GUESTS)
36	/* Enable 64 bits guest support. */
37	# define VBOX_ENABLE_64_BITS_GUESTS
38	#endif
39
40	#if HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS) && !defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
41	# define VMX_USE_CACHED_VMCS_ACCESSES
42	#endif
43
44	/** @def HM_PROFILE_EXIT_DISPATCH
45	* Enables profiling of the VM exit handler dispatching. */
46	#if 0
47	# define HM_PROFILE_EXIT_DISPATCH
48	#endif
49
50	/* The MSR auto load/store used to not work for KERNEL_GS_BASE MSR, thus we
51	* used to handle this MSR manually. See @bugref{6208}. This was clearly visible while
52	* booting Solaris 11 (11.1 b19) VMs with 2 Cpus. This is no longer the case and we
53	* always auto load/store the KERNEL_GS_BASE MSR.
54	*
55	* Note: don't forget to update the assembly files while modifying this!
56	*/
57	/** @todo This define should always be in effect and the define itself removed
58	after 'sufficient' testing. */
59	# define VBOX_WITH_AUTO_MSR_LOAD_RESTORE
60
61	RT_C_DECLS_BEGIN
62
63
64	/** @defgroup grp_hm_int Internal
65	* @ingroup grp_hm
66	* @internal
67	* @{
68	*/
69
70
71	/** Maximum number of exit reason statistics counters. */
72	#define MAX_EXITREASON_STAT 0x100
73	#define MASK_EXITREASON_STAT 0xff
74	#define MASK_INJECT_IRQ_STAT 0xff
75
76	/** @name HM changed flags.
77	* These flags are used to keep track of which important registers that
78	* have been changed since last they were reset.
79	* @{
80	*/
81	#define HM_CHANGED_GUEST_CR0 RT_BIT(0)
82	#define HM_CHANGED_GUEST_CR3 RT_BIT(1)
83	#define HM_CHANGED_GUEST_CR4 RT_BIT(2)
84	#define HM_CHANGED_GUEST_GDTR RT_BIT(3)
85	#define HM_CHANGED_GUEST_IDTR RT_BIT(4)
86	#define HM_CHANGED_GUEST_LDTR RT_BIT(5)
87	#define HM_CHANGED_GUEST_TR RT_BIT(6)
88	#define HM_CHANGED_GUEST_SEGMENT_REGS RT_BIT(7)
89	#define HM_CHANGED_GUEST_DEBUG RT_BIT(8)
90	#define HM_CHANGED_GUEST_RIP RT_BIT(9)
91	#define HM_CHANGED_GUEST_RSP RT_BIT(10)
92	#define HM_CHANGED_GUEST_RFLAGS RT_BIT(11)
93	#define HM_CHANGED_GUEST_CR2 RT_BIT(12)
94	#define HM_CHANGED_GUEST_SYSENTER_CS_MSR RT_BIT(13)
95	#define HM_CHANGED_GUEST_SYSENTER_EIP_MSR RT_BIT(14)
96	#define HM_CHANGED_GUEST_SYSENTER_ESP_MSR RT_BIT(15)
97	/* VT-x specific state. */
98	#define HM_CHANGED_VMX_GUEST_AUTO_MSRS RT_BIT(16)
99	#define HM_CHANGED_VMX_GUEST_ACTIVITY_STATE RT_BIT(17)
100	#define HM_CHANGED_VMX_GUEST_APIC_STATE RT_BIT(18)
101	#define HM_CHANGED_VMX_ENTRY_CTLS RT_BIT(19)
102	#define HM_CHANGED_VMX_EXIT_CTLS RT_BIT(20)
103	/* AMD-V specific state. */
104	#define HM_CHANGED_SVM_GUEST_EFER_MSR RT_BIT(16)
105	#define HM_CHANGED_SVM_GUEST_APIC_STATE RT_BIT(17)
106	#define HM_CHANGED_SVM_RESERVED1 RT_BIT(18)
107	#define HM_CHANGED_SVM_RESERVED2 RT_BIT(19)
108	#define HM_CHANGED_SVM_RESERVED3 RT_BIT(20)
109
110	#define HM_CHANGED_ALL_GUEST ( HM_CHANGED_GUEST_CR0 \
111	\| HM_CHANGED_GUEST_CR3 \
112	\| HM_CHANGED_GUEST_CR4 \
113	\| HM_CHANGED_GUEST_GDTR \
114	\| HM_CHANGED_GUEST_IDTR \
115	\| HM_CHANGED_GUEST_LDTR \
116	\| HM_CHANGED_GUEST_TR \
117	\| HM_CHANGED_GUEST_SEGMENT_REGS \
118	\| HM_CHANGED_GUEST_DEBUG \
119	\| HM_CHANGED_GUEST_RIP \
120	\| HM_CHANGED_GUEST_RSP \
121	\| HM_CHANGED_GUEST_RFLAGS \
122	\| HM_CHANGED_GUEST_CR2 \
123	\| HM_CHANGED_GUEST_SYSENTER_CS_MSR \
124	\| HM_CHANGED_GUEST_SYSENTER_EIP_MSR \
125	\| HM_CHANGED_GUEST_SYSENTER_ESP_MSR \
126	\| HM_CHANGED_VMX_GUEST_AUTO_MSRS \
127	\| HM_CHANGED_VMX_GUEST_ACTIVITY_STATE \
128	\| HM_CHANGED_VMX_GUEST_APIC_STATE \
129	\| HM_CHANGED_VMX_ENTRY_CTLS \
130	\| HM_CHANGED_VMX_EXIT_CTLS)
131
132	#define HM_CHANGED_HOST_CONTEXT RT_BIT(21)
133
134	/* Bits shared between host and guest. */
135	#define HM_CHANGED_HOST_GUEST_SHARED_STATE ( HM_CHANGED_GUEST_CR0 \
136	\| HM_CHANGED_GUEST_DEBUG)
137	/** @} */
138
139	/** Maximum number of page flushes we are willing to remember before considering a full TLB flush. */
140	#define HM_MAX_TLB_SHOOTDOWN_PAGES 8
141
142	/** Size for the EPT identity page table (1024 4 MB pages to cover the entire address space). */
143	#define HM_EPT_IDENTITY_PG_TABLE_SIZE PAGE_SIZE
144	/** Size of the TSS structure + 2 pages for the IO bitmap + end byte. */
145	#define HM_VTX_TSS_SIZE (sizeof(VBOXTSS) + 2 * PAGE_SIZE + 1)
146	/** Total guest mapped memory needed. */
147	#define HM_VTX_TOTAL_DEVHEAP_MEM (HM_EPT_IDENTITY_PG_TABLE_SIZE + HM_VTX_TSS_SIZE)
148
149	/** Enable for TPR guest patching. */
150	#define VBOX_HM_WITH_GUEST_PATCHING
151
152	/** HM SSM version
153	*/
154	#ifdef VBOX_HM_WITH_GUEST_PATCHING
155	# define HM_SSM_VERSION 5
156	# define HM_SSM_VERSION_NO_PATCHING 4
157	#else
158	# define HM_SSM_VERSION 4
159	# define HM_SSM_VERSION_NO_PATCHING 4
160	#endif
161	#define HM_SSM_VERSION_2_0_X 3
162
163	/**
164	* Global per-cpu information. (host)
165	*/
166	typedef struct HMGLOBALCPUINFO
167	{
168	/** The CPU ID. */
169	RTCPUID idCpu;
170	/** The memory object */
171	RTR0MEMOBJ hMemObj;
172	/** Current ASID (AMD-V) / VPID (Intel). */
173	uint32_t uCurrentAsid;
174	/** TLB flush count. */
175	uint32_t cTlbFlushes;
176	/** Whether to flush each new ASID/VPID before use. */
177	bool fFlushAsidBeforeUse;
178	/** Configured for VT-x or AMD-V. */
179	bool fConfigured;
180	/** Set if the VBOX_HWVIRTEX_IGNORE_SVM_IN_USE hack is active. */
181	bool fIgnoreAMDVInUseError;
182	/** In use by our code. (for power suspend) */
183	volatile bool fInUse;
184	} HMGLOBALCPUINFO;
185	/** Pointer to the per-cpu global information. */
186	typedef HMGLOBALCPUINFO *PHMGLOBALCPUINFO;
187
188	typedef enum
189	{
190	HMPENDINGIO_INVALID = 0,
191	HMPENDINGIO_PORT_READ,
192	HMPENDINGIO_PORT_WRITE,
193	HMPENDINGIO_STRING_READ,
194	HMPENDINGIO_STRING_WRITE,
195	/** The usual 32-bit paranoia. */
196	HMPENDINGIO_32BIT_HACK = 0x7fffffff
197	} HMPENDINGIO;
198
199
200	typedef enum
201	{
202	HMTPRINSTR_INVALID,
203	HMTPRINSTR_READ,
204	HMTPRINSTR_READ_SHR4,
205	HMTPRINSTR_WRITE_REG,
206	HMTPRINSTR_WRITE_IMM,
207	HMTPRINSTR_JUMP_REPLACEMENT,
208	/** The usual 32-bit paranoia. */
209	HMTPRINSTR_32BIT_HACK = 0x7fffffff
210	} HMTPRINSTR;
211
212	typedef struct
213	{
214	/** The key is the address of patched instruction. (32 bits GC ptr) */
215	AVLOU32NODECORE Core;
216	/** Original opcode. */
217	uint8_t aOpcode[16];
218	/** Instruction size. */
219	uint32_t cbOp;
220	/** Replacement opcode. */
221	uint8_t aNewOpcode[16];
222	/** Replacement instruction size. */
223	uint32_t cbNewOp;
224	/** Instruction type. */
225	HMTPRINSTR enmType;
226	/** Source operand. */
227	uint32_t uSrcOperand;
228	/** Destination operand. */
229	uint32_t uDstOperand;
230	/** Number of times the instruction caused a fault. */
231	uint32_t cFaults;
232	/** Patch address of the jump replacement. */
233	RTGCPTR32 pJumpTarget;
234	} HMTPRPATCH;
235	/** Pointer to HMTPRPATCH. */
236	typedef HMTPRPATCH *PHMTPRPATCH;
237
238	/**
239	* Switcher function, HC to the special 64-bit RC.
240	*
241	* @param pVM Pointer to the VM.
242	* @param offCpumVCpu Offset from pVM->cpum to pVM->aCpus[idCpu].cpum.
243	* @returns Return code indicating the action to take.
244	*/
245	typedef DECLCALLBACK(int) FNHMSWITCHERHC(PVM pVM, uint32_t offCpumVCpu);
246	/** Pointer to switcher function. */
247	typedef FNHMSWITCHERHC *PFNHMSWITCHERHC;
248
249	/**
250	* HM VM Instance data.
251	* Changes to this must checked against the padding of the hm union in VM!
252	*/
253	typedef struct HM
254	{
255	/** Set when we've initialized VMX or SVM. */
256	bool fInitialized;
257
258	/** Set if nested paging is enabled. */
259	bool fNestedPaging;
260
261	/** Set if nested paging is allowed. */
262	bool fAllowNestedPaging;
263
264	/** Set if large pages are enabled (requires nested paging). */
265	bool fLargePages;
266
267	/** Set if we can support 64-bit guests or not. */
268	bool fAllow64BitGuests;
269
270	/** Set if an IO-APIC is configured for this VM. */
271	bool fHasIoApic;
272
273	/** Set when TPR patching is allowed. */
274	bool fTRPPatchingAllowed;
275
276	/** Set when we initialize VT-x or AMD-V once for all CPUs. */
277	bool fGlobalInit;
278
279	/** Set when TPR patching is active. */
280	bool fTPRPatchingActive;
281	bool u8Alignment[7];
282
283	/** Maximum ASID allowed. */
284	uint32_t uMaxAsid;
285
286	/** The maximum number of resumes loops allowed in ring-0 (safety precaution).
287	* This number is set much higher when RTThreadPreemptIsPending is reliable. */
288	uint32_t cMaxResumeLoops;
289
290	/** Guest allocated memory for patching purposes. */
291	RTGCPTR pGuestPatchMem;
292	/** Current free pointer inside the patch block. */
293	RTGCPTR pFreeGuestPatchMem;
294	/** Size of the guest patch memory block. */
295	uint32_t cbGuestPatchMem;
296	uint32_t uPadding1;
297
298	#if HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS) && !defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
299	/** 32 to 64 bits switcher entrypoint. */
300	R0PTRTYPE(PFNHMSWITCHERHC) pfnHost32ToGuest64R0;
301	RTR0PTR uPadding2;
302	#endif
303
304	struct
305	{
306	/** Set by the ring-0 side of HM to indicate VMX is supported by the
307	* CPU. */
308	bool fSupported;
309
310	/** Set when we've enabled VMX. */
311	bool fEnabled;
312
313	/** Set if VPID is supported. */
314	bool fVpid;
315
316	/** Set if VT-x VPID is allowed. */
317	bool fAllowVpid;
318
319	/** Set if unrestricted guest execution is in use (real and protected mode without paging). */
320	bool fUnrestrictedGuest;
321
322	/** Set if unrestricted guest execution is allowed to be used. */
323	bool fAllowUnrestricted;
324
325	/** Whether we're using the preemption timer or not. */
326	bool fUsePreemptTimer;
327	/** The shift mask employed by the VMX-Preemption timer. */
328	uint8_t cPreemptTimerShift;
329
330	/** Virtual address of the TSS page used for real mode emulation. */
331	R3PTRTYPE(PVBOXTSS) pRealModeTSS;
332
333	/** Virtual address of the identity page table used for real mode and protected mode without paging emulation in EPT mode. */
334	R3PTRTYPE(PX86PD) pNonPagingModeEPTPageTable;
335
336	/** R0 memory object for the APIC-access page. */
337	RTR0MEMOBJ hMemObjApicAccess;
338	/** Physical address of the APIC-access page. */
339	RTHCPHYS HCPhysApicAccess;
340	/** Virtual address of the APIC-access page. */
341	R0PTRTYPE(uint8_t *) pbApicAccess;
342
343	#ifdef VBOX_WITH_CRASHDUMP_MAGIC
344	RTR0MEMOBJ hMemObjScratch;
345	RTHCPHYS HCPhysScratch;
346	R0PTRTYPE(uint8_t *) pbScratch;
347	#endif
348
349	/** Internal Id of which flush-handler to use for tagged-TLB entries. */
350	unsigned uFlushTaggedTlb;
351
352	#if HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS)
353	uint32_t u32Alignment;
354	#endif
355	/** Host CR4 value (set by ring-0 VMX init) */
356	uint64_t u64HostCr4;
357
358	/** Host EFER value (set by ring-0 VMX init) */
359	uint64_t u64HostEfer;
360
361	/** VMX MSR values */
362	VMXMSRS Msrs;
363
364	/** Flush types for invept & invvpid; they depend on capabilities. */
365	VMX_FLUSH_EPT enmFlushEpt;
366	VMX_FLUSH_VPID enmFlushVpid;
367	} vmx;
368
369	struct
370	{
371	/** Set by the ring-0 side of HM to indicate SVM is supported by the
372	* CPU. */
373	bool fSupported;
374	/** Set when we've enabled SVM. */
375	bool fEnabled;
376	/** Set if erratum 170 affects the AMD cpu. */
377	bool fAlwaysFlushTLB;
378	/** Set when the hack to ignore VERR_SVM_IN_USE is active. */
379	bool fIgnoreInUseError;
380
381	/** R0 memory object for the IO bitmap (12kb). */
382	RTR0MEMOBJ hMemObjIOBitmap;
383	/** Physical address of the IO bitmap (12kb). */
384	RTHCPHYS HCPhysIOBitmap;
385	/** Virtual address of the IO bitmap. */
386	R0PTRTYPE(void *) pvIOBitmap;
387
388	/* HWCR MSR (for diagnostics) */
389	uint64_t u64MsrHwcr;
390
391	/** SVM revision. */
392	uint32_t u32Rev;
393
394	/** SVM feature bits from cpuid 0x8000000a */
395	uint32_t u32Features;
396	} svm;
397
398	/**
399	* AVL tree with all patches (active or disabled) sorted by guest instruction address
400	*/
401	AVLOU32TREE PatchTree;
402	uint32_t cPatches;
403	HMTPRPATCH aPatches[64];
404
405	struct
406	{
407	uint32_t u32AMDFeatureECX;
408	uint32_t u32AMDFeatureEDX;
409	} cpuid;
410
411	/** Saved error from detection */
412	int32_t lLastError;
413
414	/** HMR0Init was run */
415	bool fHMR0Init;
416	bool u8Alignment1[7];
417
418	STAMCOUNTER StatTprPatchSuccess;
419	STAMCOUNTER StatTprPatchFailure;
420	STAMCOUNTER StatTprReplaceSuccess;
421	STAMCOUNTER StatTprReplaceFailure;
422	} HM;
423	/** Pointer to HM VM instance data. */
424	typedef HM *PHM;
425
426	/* Maximum number of cached entries. */
427	#define VMCSCACHE_MAX_ENTRY 128
428
429	/* Structure for storing read and write VMCS actions. */
430	typedef struct VMCSCACHE
431	{
432	#ifdef VBOX_WITH_CRASHDUMP_MAGIC
433	/* Magic marker for searching in crash dumps. */
434	uint8_t aMagic[16];
435	uint64_t uMagic;
436	uint64_t u64TimeEntry;
437	uint64_t u64TimeSwitch;
438	uint64_t cResume;
439	uint64_t interPD;
440	uint64_t pSwitcher;
441	uint32_t uPos;
442	uint32_t idCpu;
443	#endif
444	/* CR2 is saved here for EPT syncing. */
445	uint64_t cr2;
446	struct
447	{
448	uint32_t cValidEntries;
449	uint32_t uAlignment;
450	uint32_t aField[VMCSCACHE_MAX_ENTRY];
451	uint64_t aFieldVal[VMCSCACHE_MAX_ENTRY];
452	} Write;
453	struct
454	{
455	uint32_t cValidEntries;
456	uint32_t uAlignment;
457	uint32_t aField[VMCSCACHE_MAX_ENTRY];
458	uint64_t aFieldVal[VMCSCACHE_MAX_ENTRY];
459	} Read;
460	#ifdef VBOX_STRICT
461	struct
462	{
463	RTHCPHYS HCPhysCpuPage;
464	RTHCPHYS HCPhysVmcs;
465	RTGCPTR pCache;
466	RTGCPTR pCtx;
467	} TestIn;
468	struct
469	{
470	RTHCPHYS HCPhysVmcs;
471	RTGCPTR pCache;
472	RTGCPTR pCtx;
473	uint64_t eflags;
474	uint64_t cr8;
475	} TestOut;
476	struct
477	{
478	uint64_t param1;
479	uint64_t param2;
480	uint64_t param3;
481	uint64_t param4;
482	} ScratchPad;
483	#endif
484	} VMCSCACHE;
485	/** Pointer to VMCSCACHE. */
486	typedef VMCSCACHE *PVMCSCACHE;
487
488	/** VMX StartVM function. */
489	typedef DECLCALLBACK(int) FNHMVMXSTARTVM(RTHCUINT fResume, PCPUMCTX pCtx, PVMCSCACHE pCache, PVM pVM, PVMCPU pVCpu);
490	/** Pointer to a VMX StartVM function. */
491	typedef R0PTRTYPE(FNHMVMXSTARTVM *) PFNHMVMXSTARTVM;
492
493	/** SVM VMRun function. */
494	typedef DECLCALLBACK(int) FNHMSVMVMRUN(RTHCPHYS pVmcbHostPhys, RTHCPHYS pVmcbPhys, PCPUMCTX pCtx, PVM pVM, PVMCPU pVCpu);
495	/** Pointer to a SVM VMRun function. */
496	typedef R0PTRTYPE(FNHMSVMVMRUN *) PFNHMSVMVMRUN;
497
498	/**
499	* HM VMCPU Instance data.
500	*/
501	typedef struct HMCPU
502	{
503	/** Set if we need to flush the TLB during the world switch. */
504	bool fForceTLBFlush;
505	/** Set when we're using VT-x or AMD-V at that moment. */
506	bool fActive;
507	/** Set when the TLB has been checked until we return from the world switch. */
508	volatile bool fCheckedTLBFlush;
509	/** Whether we're executing a single instruction. */
510	bool fSingleInstruction;
511	/** Set if we need to clear the trap flag because of single stepping. */
512	bool fClearTrapFlag;
513	/** Whether we've completed the inner HM leave function. */
514	bool fLeaveDone;
515	/** Whether we're using the hyper DR7 or guest DR7. */
516	bool fUsingHyperDR7;
517	uint8_t abAlignment[1];
518
519	/** World switch exit counter. */
520	volatile uint32_t cWorldSwitchExits;
521	/** HM_CHANGED_* flags. */
522	uint32_t fContextUseFlags;
523	/** Id of the last cpu we were executing code on (NIL_RTCPUID for the first
524	* time). */
525	RTCPUID idLastCpu;
526	/** TLB flush count. */
527	uint32_t cTlbFlushes;
528	/** Current ASID in use by the VM. */
529	uint32_t uCurrentAsid;
530	/** An additional error code used for some gurus. */
531	uint32_t u32HMError;
532	/** Host's TSC_AUX MSR (used when RDTSCP doesn't cause VM-exits). */
533	uint64_t u64HostTscAux;
534
535	struct
536	{
537	/** Physical address of the VM control structure (VMCS). */
538	RTHCPHYS HCPhysVmcs;
539	/** R0 memory object for the VM control structure (VMCS). */
540	RTR0MEMOBJ hMemObjVmcs;
541	/** Virtual address of the VM control structure (VMCS). */
542	R0PTRTYPE(void *) pvVmcs;
543	/** Ring 0 handlers for VT-x. */
544	PFNHMVMXSTARTVM pfnStartVM;
545	#if HC_ARCH_BITS == 32
546	uint32_t u32Alignment1;
547	#endif
548
549	/** Current VMX_VMCS32_CTRL_PIN_EXEC. */
550	uint32_t u32PinCtls;
551	/** Current VMX_VMCS32_CTRL_PROC_EXEC. */
552	uint32_t u32ProcCtls;
553	/** Current VMX_VMCS32_CTRL_PROC_EXEC2. */
554	uint32_t u32ProcCtls2;
555	/** Current VMX_VMCS32_CTRL_EXIT. */
556	uint32_t u32ExitCtls;
557	/** Current VMX_VMCS32_CTRL_ENTRY. */
558	uint32_t u32EntryCtls;
559
560	/** Physical address of the virtual APIC page for TPR caching. */
561	RTHCPHYS HCPhysVirtApic;
562	/** R0 memory object for the virtual APIC page for TPR caching. */
563	RTR0MEMOBJ hMemObjVirtApic;
564	/** Virtual address of the virtual APIC page for TPR caching. */
565	R0PTRTYPE(uint8_t *) pbVirtApic;
566	#if HC_ARCH_BITS == 32
567	uint32_t u32Alignment2;
568	#endif
569
570	/** Current CR0 mask. */
571	uint32_t u32CR0Mask;
572	/** Current CR4 mask. */
573	uint32_t u32CR4Mask;
574	/** Current exception bitmap. */
575	uint32_t u32XcptBitmap;
576	/** The updated-guest-state mask. */
577	uint32_t fUpdatedGuestState;
578	/** Current EPTP. */
579	RTHCPHYS HCPhysEPTP;
580
581	/** Physical address of the MSR bitmap. */
582	RTHCPHYS HCPhysMsrBitmap;
583	/** R0 memory object for the MSR bitmap. */
584	RTR0MEMOBJ hMemObjMsrBitmap;
585	/** Virtual address of the MSR bitmap. */
586	R0PTRTYPE(void *) pvMsrBitmap;
587
588	#ifdef VBOX_WITH_AUTO_MSR_LOAD_RESTORE
589	/** Physical address of the VM-entry MSR-load and VM-exit MSR-store area (used
590	* for guest MSRs). */
591	RTHCPHYS HCPhysGuestMsr;
592	/** R0 memory object of the VM-entry MSR-load and VM-exit MSR-store area
593	* (used for guest MSRs). */
594	RTR0MEMOBJ hMemObjGuestMsr;
595	/** Virtual address of the VM-entry MSR-load and VM-exit MSR-store area (used
596	* for guest MSRs). */
597	R0PTRTYPE(void *) pvGuestMsr;
598
599	/** Physical address of the VM-exit MSR-load area (used for host MSRs). */
600	RTHCPHYS HCPhysHostMsr;
601	/** R0 memory object for the VM-exit MSR-load area (used for host MSRs). */
602	RTR0MEMOBJ hMemObjHostMsr;
603	/** Virtual address of the VM-exit MSR-load area (used for host MSRs). */
604	R0PTRTYPE(void *) pvHostMsr;
605
606	/** Number of automatically loaded/restored guest MSRs during the world switch. */
607	uint32_t cGuestMsrs;
608	uint32_t uAlignment;
609	#endif /* VBOX_WITH_AUTO_MSR_LOAD_RESTORE */
610
611	/** The cached APIC-base MSR used for identifying when to map the HC physical APIC-access page. */
612	uint64_t u64MsrApicBase;
613	/** Last use TSC offset value. (cached) */
614	uint64_t u64TSCOffset;
615
616	/** VMCS cache. */
617	VMCSCACHE VMCSCache;
618
619	/** Real-mode emulation state. */
620	struct
621	{
622	X86DESCATTR AttrCS;
623	X86DESCATTR AttrDS;
624	X86DESCATTR AttrES;
625	X86DESCATTR AttrFS;
626	X86DESCATTR AttrGS;
627	X86DESCATTR AttrSS;
628	X86EFLAGS Eflags;
629	uint32_t fRealOnV86Active;
630	} RealMode;
631
632	struct
633	{
634	uint64_t u64VMCSPhys;
635	uint32_t u32VMCSRevision;
636	uint32_t u32InstrError;
637	uint32_t u32ExitReason;
638	RTCPUID idEnteredCpu;
639	RTCPUID idCurrentCpu;
640	uint32_t u32Padding;
641	} LastError;
642
643	/** State of the VMCS. */
644	uint32_t uVmcsState;
645	/** Which host-state bits to restore before being preempted. */
646	uint32_t fRestoreHostFlags;
647	/** The host-state restoration structure. */
648	VMXRESTOREHOST RestoreHost;
649	/** Set if guest was executing in real mode (extra checks). */
650	bool fWasInRealMode;
651	/** Padding. */
652	uint32_t u32Padding;
653	} vmx;
654
655	struct
656	{
657	/** R0 memory object for the host VMCB which holds additional host-state. */
658	RTR0MEMOBJ hMemObjVmcbHost;
659	/** Physical address of the host VMCB which holds additional host-state. */
660	RTHCPHYS HCPhysVmcbHost;
661	/** Virtual address of the host VMCB which holds additional host-state. */
662	R0PTRTYPE(void *) pvVmcbHost;
663
664	/** R0 memory object for the guest VMCB. */
665	RTR0MEMOBJ hMemObjVmcb;
666	/** Physical address of the guest VMCB. */
667	RTHCPHYS HCPhysVmcb;
668	/** Virtual address of the guest VMCB. */
669	R0PTRTYPE(void *) pvVmcb;
670
671	/** Ring 0 handlers for VT-x. */
672	PFNHMSVMVMRUN pfnVMRun;
673
674	/** R0 memory object for the MSR bitmap (8 KB). */
675	RTR0MEMOBJ hMemObjMsrBitmap;
676	/** Physical address of the MSR bitmap (8 KB). */
677	RTHCPHYS HCPhysMsrBitmap;
678	/** Virtual address of the MSR bitmap. */
679	R0PTRTYPE(void *) pvMsrBitmap;
680
681	/** Whether VTPR with V_INTR_MASKING set is in effect, indicating
682	* we should check if the VTPR changed on every VM-exit. */
683	bool fSyncVTpr;
684	uint8_t u8Align[7];
685
686	/** Alignment padding. */
687	uint32_t u32Padding;
688	} svm;
689
690	/** Event injection state. */
691	struct
692	{
693	uint32_t fPending;
694	uint32_t u32ErrCode;
695	uint32_t cbInstr;
696	uint32_t u32Padding; /*< Explicit alignment padding. /
697	uint64_t u64IntrInfo;
698	RTGCUINTPTR GCPtrFaultAddress;
699	} Event;
700
701	/** IO Block emulation state. */
702	struct
703	{
704	bool fEnabled;
705	uint8_t u8Align[7];
706
707	/** RIP at the start of the io code we wish to emulate in the recompiler. */
708	RTGCPTR GCPtrFunctionEip;
709
710	uint64_t cr0;
711	} EmulateIoBlock;
712
713	struct
714	{
715	/** Pending IO operation type. */
716	HMPENDINGIO enmType;
717	uint32_t uPadding;
718	RTGCPTR GCPtrRip;
719	RTGCPTR GCPtrRipNext;
720	union
721	{
722	struct
723	{
724	uint32_t uPort;
725	uint32_t uAndVal;
726	uint32_t cbSize;
727	} Port;
728	uint64_t aRaw[2];
729	} s;
730	} PendingIO;
731
732	/** The PAE PDPEs used with Nested Paging (only valid when
733	* VMCPU_FF_HM_UPDATE_PAE_PDPES is set). */
734	X86PDPE aPdpes[4];
735
736	/** Current shadow paging mode. */
737	PGMMODE enmShadowMode;
738
739	/** The CPU ID of the CPU currently owning the VMCS. Set in
740	* HMR0Enter and cleared in HMR0Leave. */
741	RTCPUID idEnteredCpu;
742
743	/** To keep track of pending TLB shootdown pages. (SMP guest only) */
744	struct
745	{
746	RTGCPTR aPages[HM_MAX_TLB_SHOOTDOWN_PAGES];
747	uint32_t cPages;
748	uint32_t u32Padding; /*< Explicit alignment padding. /
749	} TlbShootdown;
750
751	/** For saving stack space, the disassembler state is allocated here instead of
752	* on the stack. */
753	DISCPUSTATE DisState;
754
755	STAMPROFILEADV StatEntry;
756	STAMPROFILEADV StatExit1;
757	STAMPROFILEADV StatExit2;
758	STAMPROFILEADV StatExitIO;
759	STAMPROFILEADV StatExitMovCRx;
760	STAMPROFILEADV StatExitXcptNmi;
761	STAMPROFILEADV StatLoadGuestState;
762	STAMPROFILEADV StatInGC;
763
764	#if HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS) && !defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
765	STAMPROFILEADV StatWorldSwitch3264;
766	#endif
767	STAMPROFILEADV StatPoke;
768	STAMPROFILEADV StatSpinPoke;
769	STAMPROFILEADV StatSpinPokeFailed;
770
771	STAMCOUNTER StatInjectInterrupt;
772	STAMCOUNTER StatInjectXcpt;
773	STAMCOUNTER StatInjectPendingReflect;
774
775	STAMCOUNTER StatExitAll;
776	STAMCOUNTER StatExitShadowNM;
777	STAMCOUNTER StatExitGuestNM;
778	STAMCOUNTER StatExitShadowPF; /* Misleading, currently used for MMIO #PFs as well. */
779	STAMCOUNTER StatExitShadowPFEM;
780	STAMCOUNTER StatExitGuestPF;
781	STAMCOUNTER StatExitGuestUD;
782	STAMCOUNTER StatExitGuestSS;
783	STAMCOUNTER StatExitGuestNP;
784	STAMCOUNTER StatExitGuestGP;
785	STAMCOUNTER StatExitGuestDE;
786	STAMCOUNTER StatExitGuestDB;
787	STAMCOUNTER StatExitGuestMF;
788	STAMCOUNTER StatExitGuestBP;
789	STAMCOUNTER StatExitGuestXF;
790	STAMCOUNTER StatExitGuestXcpUnk;
791	STAMCOUNTER StatExitInvlpg;
792	STAMCOUNTER StatExitInvd;
793	STAMCOUNTER StatExitWbinvd;
794	STAMCOUNTER StatExitPause;
795	STAMCOUNTER StatExitCpuid;
796	STAMCOUNTER StatExitRdtsc;
797	STAMCOUNTER StatExitRdtscp;
798	STAMCOUNTER StatExitRdpmc;
799	STAMCOUNTER StatExitRdrand;
800	STAMCOUNTER StatExitCli;
801	STAMCOUNTER StatExitSti;
802	STAMCOUNTER StatExitPushf;
803	STAMCOUNTER StatExitPopf;
804	STAMCOUNTER StatExitIret;
805	STAMCOUNTER StatExitInt;
806	STAMCOUNTER StatExitCRxWrite[16];
807	STAMCOUNTER StatExitCRxRead[16];
808	STAMCOUNTER StatExitDRxWrite;
809	STAMCOUNTER StatExitDRxRead;
810	STAMCOUNTER StatExitRdmsr;
811	STAMCOUNTER StatExitWrmsr;
812	STAMCOUNTER StatExitClts;
813	STAMCOUNTER StatExitXdtrAccess;
814	STAMCOUNTER StatExitHlt;
815	STAMCOUNTER StatExitMwait;
816	STAMCOUNTER StatExitMonitor;
817	STAMCOUNTER StatExitLmsw;
818	STAMCOUNTER StatExitIOWrite;
819	STAMCOUNTER StatExitIORead;
820	STAMCOUNTER StatExitIOStringWrite;
821	STAMCOUNTER StatExitIOStringRead;
822	STAMCOUNTER StatExitIntWindow;
823	STAMCOUNTER StatExitMaxResume;
824	STAMCOUNTER StatExitExtInt;
825	STAMCOUNTER StatExitHostNmiInGC;
826	STAMCOUNTER StatExitPreemptTimer;
827	STAMCOUNTER StatExitTprBelowThreshold;
828	STAMCOUNTER StatExitTaskSwitch;
829	STAMCOUNTER StatExitMtf;
830	STAMCOUNTER StatExitApicAccess;
831	STAMCOUNTER StatPendingHostIrq;
832
833	STAMCOUNTER StatPreemptPreempting;
834	STAMCOUNTER StatPreemptSaveHostState;
835
836	STAMCOUNTER StatFlushPage;
837	STAMCOUNTER StatFlushPageManual;
838	STAMCOUNTER StatFlushPhysPageManual;
839	STAMCOUNTER StatFlushTlb;
840	STAMCOUNTER StatFlushTlbManual;
841	STAMCOUNTER StatFlushTlbWorldSwitch;
842	STAMCOUNTER StatNoFlushTlbWorldSwitch;
843	STAMCOUNTER StatFlushEntire;
844	STAMCOUNTER StatFlushAsid;
845	STAMCOUNTER StatFlushNestedPaging;
846	STAMCOUNTER StatFlushTlbInvlpgVirt;
847	STAMCOUNTER StatFlushTlbInvlpgPhys;
848	STAMCOUNTER StatTlbShootdown;
849	STAMCOUNTER StatTlbShootdownFlush;
850
851	STAMCOUNTER StatSwitchGuestIrq;
852	STAMCOUNTER StatSwitchHmToR3FF;
853	STAMCOUNTER StatSwitchExitToR3;
854	STAMCOUNTER StatSwitchLongJmpToR3;
855
856	STAMCOUNTER StatTscOffset;
857	STAMCOUNTER StatTscIntercept;
858	STAMCOUNTER StatTscInterceptOverFlow;
859
860	STAMCOUNTER StatExitReasonNpf;
861	STAMCOUNTER StatDRxArmed;
862	STAMCOUNTER StatDRxContextSwitch;
863	STAMCOUNTER StatDRxIoCheck;
864
865	STAMCOUNTER StatLoadMinimal;
866	STAMCOUNTER StatLoadFull;
867
868	STAMCOUNTER StatVmxCheckBadRmSelBase;
869	STAMCOUNTER StatVmxCheckBadRmSelLimit;
870	STAMCOUNTER StatVmxCheckRmOk;
871
872	STAMCOUNTER StatVmxCheckBadSel;
873	STAMCOUNTER StatVmxCheckBadRpl;
874	STAMCOUNTER StatVmxCheckBadLdt;
875	STAMCOUNTER StatVmxCheckBadTr;
876	STAMCOUNTER StatVmxCheckPmOk;
877
878	#if HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS) && !defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
879	STAMCOUNTER StatFpu64SwitchBack;
880	STAMCOUNTER StatDebug64SwitchBack;
881	#endif
882
883	#ifdef VBOX_WITH_STATISTICS
884	R3PTRTYPE(PSTAMCOUNTER) paStatExitReason;
885	R0PTRTYPE(PSTAMCOUNTER) paStatExitReasonR0;
886	R3PTRTYPE(PSTAMCOUNTER) paStatInjectedIrqs;
887	R0PTRTYPE(PSTAMCOUNTER) paStatInjectedIrqsR0;
888	#endif
889	#ifdef HM_PROFILE_EXIT_DISPATCH
890	STAMPROFILEADV StatExitDispatch;
891	#endif
892	} HMCPU;
893	/** Pointer to HM VM instance data. */
894	typedef HMCPU *PHMCPU;
895
896
897	#ifdef IN_RING0
898
899	VMMR0DECL(PHMGLOBALCPUINFO) HMR0GetCurrentCpu(void);
900	VMMR0DECL(PHMGLOBALCPUINFO) HMR0GetCurrentCpuEx(RTCPUID idCpu);
901
902
903	#ifdef VBOX_STRICT
904	VMMR0DECL(void) HMDumpRegs(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx);
905	VMMR0DECL(void) HMR0DumpDescriptor(PCX86DESCHC pDesc, RTSEL Sel, const char *pszMsg);
906	#else
907	# define HMDumpRegs(a, b ,c) do { } while (0)
908	# define HMR0DumpDescriptor(a, b, c) do { } while (0)
909	#endif
910
911	# ifdef VBOX_WITH_KERNEL_USING_XMM
912	DECLASM(int) HMR0VMXStartVMWrapXMM(RTHCUINT fResume, PCPUMCTX pCtx, PVMCSCACHE pCache, PVM pVM, PVMCPU pVCpu, PFNHMVMXSTARTVM pfnStartVM);
913	DECLASM(int) HMR0SVMRunWrapXMM(RTHCPHYS pVmcbHostPhys, RTHCPHYS pVmcbPhys, PCPUMCTX pCtx, PVM pVM, PVMCPU pVCpu, PFNHMSVMVMRUN pfnVMRun);
914	# endif
915
916	# ifdef VBOX_WITH_HYBRID_32BIT_KERNEL
917	/**
918	* Gets 64-bit GDTR and IDTR on darwin.
919	* @param pGdtr Where to store the 64-bit GDTR.
920	* @param pIdtr Where to store the 64-bit IDTR.
921	*/
922	DECLASM(void) HMR0Get64bitGdtrAndIdtr(PX86XDTR64 pGdtr, PX86XDTR64 pIdtr);
923
924	/**
925	* Gets 64-bit CR3 on darwin.
926	* @returns CR3
927	*/
928	DECLASM(uint64_t) HMR0Get64bitCR3(void);
929	# endif
930
931	#endif /* IN_RING0 */
932
933	/** @} */
934
935	RT_C_DECLS_END
936
937	#endif
938

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source: vbox/trunk/src/VBox/VMM/include/HMInternal.h@ 48756

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