VirtualBox

source: vbox/trunk/src/VBox/VMM/include/HMInternal.h@ 57516

Last change on this file since 57516 was 57477, checked in by vboxsync, 9 years ago

VMM/HM: Implement PAUSE filter exiting for VT-x & AMD-V. Also corrected some reserved bits in EPT_VPID capability MSRs.
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File size: 40.8 KB
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1/* $Id: HMInternal.h 57477 2015-08-20 14:20:26Z vboxsync $ */
2/** @file
3 * HM - Internal header file.
4 */
5
6/*
7 * Copyright (C) 2006-2015 Oracle Corporation
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 */
17
18#ifndef ___HMInternal_h
19#define ___HMInternal_h
20
21#include <VBox/cdefs.h>
22#include <VBox/types.h>
23#include <VBox/vmm/em.h>
24#include <VBox/vmm/stam.h>
25#include <VBox/dis.h>
26#include <VBox/vmm/hm.h>
27#include <VBox/vmm/hm_vmx.h>
28#include <VBox/vmm/pgm.h>
29#include <VBox/vmm/cpum.h>
30#include <iprt/memobj.h>
31#include <iprt/cpuset.h>
32#include <iprt/mp.h>
33#include <iprt/avl.h>
34#include <iprt/string.h>
35
36#if defined(RT_OS_DARWIN) && HC_ARCH_BITS == 32
37# error "32-bit darwin is no longer supported. Go back to 4.3 or earlier!"
38#endif
39
40#if HC_ARCH_BITS == 64 || defined (VBOX_WITH_64_BITS_GUESTS)
41/* Enable 64 bits guest support. */
42# define VBOX_ENABLE_64_BITS_GUESTS
43#endif
44
45#if HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS)
46# define VMX_USE_CACHED_VMCS_ACCESSES
47#endif
48
49/** @def HM_PROFILE_EXIT_DISPATCH
50 * Enables profiling of the VM exit handler dispatching. */
51#if 0
52# define HM_PROFILE_EXIT_DISPATCH
53#endif
54
55RT_C_DECLS_BEGIN
56
57
58/** @defgroup grp_hm_int Internal
59 * @ingroup grp_hm
60 * @internal
61 * @{
62 */
63
64/** @def HMCPU_CF_CLEAR
65 * Clears a HM-context flag.
66 *
67 * @param pVCpu Pointer to the VMCPU.
68 * @param fFlag The flag to clear.
69 */
70#define HMCPU_CF_CLEAR(pVCpu, fFlag) (ASMAtomicUoAndU32(&(pVCpu)->hm.s.fContextUseFlags, ~(fFlag)))
71
72/** @def HMCPU_CF_SET
73 * Sets a HM-context flag.
74 *
75 * @param pVCpu Pointer to the VMCPU.
76 * @param fFlag The flag to set.
77 */
78#define HMCPU_CF_SET(pVCpu, fFlag) (ASMAtomicUoOrU32(&(pVCpu)->hm.s.fContextUseFlags, (fFlag)))
79
80/** @def HMCPU_CF_IS_SET
81 * Checks if all the flags in the specified HM-context set is pending.
82 *
83 * @param pVCpu Pointer to the VMCPU.
84 * @param fFlag The flag to check.
85 */
86#define HMCPU_CF_IS_SET(pVCpu, fFlag) ((ASMAtomicUoReadU32(&(pVCpu)->hm.s.fContextUseFlags) & (fFlag)) == (fFlag))
87
88/** @def HMCPU_CF_IS_PENDING
89 * Checks if one or more of the flags in the specified HM-context set is
90 * pending.
91 *
92 * @param pVCpu Pointer to the VMCPU.
93 * @param fFlags The flags to check for.
94 */
95#define HMCPU_CF_IS_PENDING(pVCpu, fFlags) RT_BOOL(ASMAtomicUoReadU32(&(pVCpu)->hm.s.fContextUseFlags) & (fFlags))
96
97/** @def HMCPU_CF_IS_PENDING_ONLY
98 * Checks if -only- one or more of the specified HM-context flags is pending.
99 *
100 * @param pVCpu Pointer to the VMCPU.
101 * @param fFlags The flags to check for.
102 */
103#define HMCPU_CF_IS_PENDING_ONLY(pVCpu, fFlags) !RT_BOOL(ASMAtomicUoReadU32(&(pVCpu)->hm.s.fContextUseFlags) & ~(fFlags))
104
105/** @def HMCPU_CF_IS_SET_ONLY
106 * Checks if -only- all the flags in the specified HM-context set is pending.
107 *
108 * @param pVCpu Pointer to the VMCPU.
109 * @param fFlags The flags to check for.
110 */
111#define HMCPU_CF_IS_SET_ONLY(pVCpu, fFlags) (ASMAtomicUoReadU32(&(pVCpu)->hm.s.fContextUseFlags) == (fFlags))
112
113/** @def HMCPU_CF_RESET_TO
114 * Resets the HM-context flags to the specified value.
115 *
116 * @param pVCpu Pointer to the VMCPU.
117 * @param fFlags The new value.
118 */
119#define HMCPU_CF_RESET_TO(pVCpu, fFlags) (ASMAtomicUoWriteU32(&(pVCpu)->hm.s.fContextUseFlags, (fFlags)))
120
121/** @def HMCPU_CF_VALUE
122 * Returns the current HM-context flags value.
123 *
124 * @param pVCpu Pointer to the VMCPU.
125 */
126#define HMCPU_CF_VALUE(pVCpu) (ASMAtomicUoReadU32(&(pVCpu)->hm.s.fContextUseFlags))
127
128
129/** Resets/initializes the VM-exit/#VMEXIT history array. */
130#define HMCPU_EXIT_HISTORY_RESET(pVCpu) (memset(&(pVCpu)->hm.s.auExitHistory, 0xff, sizeof((pVCpu)->hm.s.auExitHistory)))
131
132/** Updates the VM-exit/#VMEXIT history array. */
133#define HMCPU_EXIT_HISTORY_ADD(pVCpu, a_ExitReason) \
134 do { \
135 AssertMsg((pVCpu)->hm.s.idxExitHistoryFree < RT_ELEMENTS((pVCpu)->hm.s.auExitHistory), ("%u\n", (pVCpu)->hm.s.idxExitHistoryFree)); \
136 (pVCpu)->hm.s.auExitHistory[(pVCpu)->hm.s.idxExitHistoryFree++] = (uint16_t)(a_ExitReason); \
137 if ((pVCpu)->hm.s.idxExitHistoryFree == RT_ELEMENTS((pVCpu)->hm.s.auExitHistory)) \
138 (pVCpu)->hm.s.idxExitHistoryFree = 0; \
139 (pVCpu)->hm.s.auExitHistory[(pVCpu)->hm.s.idxExitHistoryFree] = UINT16_MAX; \
140 } while (0)
141
142/** Maximum number of exit reason statistics counters. */
143#define MAX_EXITREASON_STAT 0x100
144#define MASK_EXITREASON_STAT 0xff
145#define MASK_INJECT_IRQ_STAT 0xff
146
147/** @name HM changed flags.
148 * These flags are used to keep track of which important registers that
149 * have been changed since last they were reset.
150 * @{
151 */
152#define HM_CHANGED_GUEST_CR0 RT_BIT(0) /* Shared */
153#define HM_CHANGED_GUEST_CR3 RT_BIT(1)
154#define HM_CHANGED_GUEST_CR4 RT_BIT(2)
155#define HM_CHANGED_GUEST_GDTR RT_BIT(3)
156#define HM_CHANGED_GUEST_IDTR RT_BIT(4)
157#define HM_CHANGED_GUEST_LDTR RT_BIT(5)
158#define HM_CHANGED_GUEST_TR RT_BIT(6)
159#define HM_CHANGED_GUEST_SEGMENT_REGS RT_BIT(7)
160#define HM_CHANGED_GUEST_DEBUG RT_BIT(8) /* Shared */
161#define HM_CHANGED_GUEST_RIP RT_BIT(9)
162#define HM_CHANGED_GUEST_RSP RT_BIT(10)
163#define HM_CHANGED_GUEST_RFLAGS RT_BIT(11)
164#define HM_CHANGED_GUEST_CR2 RT_BIT(12)
165#define HM_CHANGED_GUEST_SYSENTER_CS_MSR RT_BIT(13)
166#define HM_CHANGED_GUEST_SYSENTER_EIP_MSR RT_BIT(14)
167#define HM_CHANGED_GUEST_SYSENTER_ESP_MSR RT_BIT(15)
168#define HM_CHANGED_GUEST_EFER_MSR RT_BIT(16)
169#define HM_CHANGED_GUEST_LAZY_MSRS RT_BIT(17) /* Shared */
170#define HM_CHANGED_GUEST_XCPT_INTERCEPTS RT_BIT(18)
171/* VT-x specific state. */
172#define HM_CHANGED_VMX_GUEST_AUTO_MSRS RT_BIT(19)
173#define HM_CHANGED_VMX_GUEST_ACTIVITY_STATE RT_BIT(20)
174#define HM_CHANGED_VMX_GUEST_APIC_STATE RT_BIT(21)
175#define HM_CHANGED_VMX_ENTRY_CTLS RT_BIT(22)
176#define HM_CHANGED_VMX_EXIT_CTLS RT_BIT(23)
177/* AMD-V specific state. */
178#define HM_CHANGED_SVM_GUEST_APIC_STATE RT_BIT(19)
179#define HM_CHANGED_SVM_RESERVED1 RT_BIT(20)
180#define HM_CHANGED_SVM_RESERVED2 RT_BIT(21)
181#define HM_CHANGED_SVM_RESERVED3 RT_BIT(22)
182#define HM_CHANGED_SVM_RESERVED4 RT_BIT(23)
183
184#define HM_CHANGED_ALL_GUEST ( HM_CHANGED_GUEST_CR0 \
185 | HM_CHANGED_GUEST_CR3 \
186 | HM_CHANGED_GUEST_CR4 \
187 | HM_CHANGED_GUEST_GDTR \
188 | HM_CHANGED_GUEST_IDTR \
189 | HM_CHANGED_GUEST_LDTR \
190 | HM_CHANGED_GUEST_TR \
191 | HM_CHANGED_GUEST_SEGMENT_REGS \
192 | HM_CHANGED_GUEST_DEBUG \
193 | HM_CHANGED_GUEST_RIP \
194 | HM_CHANGED_GUEST_RSP \
195 | HM_CHANGED_GUEST_RFLAGS \
196 | HM_CHANGED_GUEST_CR2 \
197 | HM_CHANGED_GUEST_SYSENTER_CS_MSR \
198 | HM_CHANGED_GUEST_SYSENTER_EIP_MSR \
199 | HM_CHANGED_GUEST_SYSENTER_ESP_MSR \
200 | HM_CHANGED_GUEST_EFER_MSR \
201 | HM_CHANGED_GUEST_LAZY_MSRS \
202 | HM_CHANGED_GUEST_XCPT_INTERCEPTS \
203 | HM_CHANGED_VMX_GUEST_AUTO_MSRS \
204 | HM_CHANGED_VMX_GUEST_ACTIVITY_STATE \
205 | HM_CHANGED_VMX_GUEST_APIC_STATE \
206 | HM_CHANGED_VMX_ENTRY_CTLS \
207 | HM_CHANGED_VMX_EXIT_CTLS)
208
209#define HM_CHANGED_HOST_CONTEXT RT_BIT(24)
210
211/* Bits shared between host and guest. */
212#define HM_CHANGED_HOST_GUEST_SHARED_STATE ( HM_CHANGED_GUEST_CR0 \
213 | HM_CHANGED_GUEST_DEBUG \
214 | HM_CHANGED_GUEST_LAZY_MSRS)
215/** @} */
216
217/** Size for the EPT identity page table (1024 4 MB pages to cover the entire address space). */
218#define HM_EPT_IDENTITY_PG_TABLE_SIZE PAGE_SIZE
219/** Size of the TSS structure + 2 pages for the IO bitmap + end byte. */
220#define HM_VTX_TSS_SIZE (sizeof(VBOXTSS) + 2 * PAGE_SIZE + 1)
221/** Total guest mapped memory needed. */
222#define HM_VTX_TOTAL_DEVHEAP_MEM (HM_EPT_IDENTITY_PG_TABLE_SIZE + HM_VTX_TSS_SIZE)
223
224
225/** @name Macros for enabling and disabling preemption.
226 * These are really just for hiding the RTTHREADPREEMPTSTATE and asserting that
227 * preemption has already been disabled when there is no context hook.
228 * @{ */
229#ifdef VBOX_STRICT
230# define HM_DISABLE_PREEMPT() \
231 RTTHREADPREEMPTSTATE PreemptStateInternal = RTTHREADPREEMPTSTATE_INITIALIZER; \
232 Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD) || VMMR0ThreadCtxHookIsEnabled(pVCpu)); \
233 RTThreadPreemptDisable(&PreemptStateInternal)
234#else
235# define HM_DISABLE_PREEMPT() \
236 RTTHREADPREEMPTSTATE PreemptStateInternal = RTTHREADPREEMPTSTATE_INITIALIZER; \
237 RTThreadPreemptDisable(&PreemptStateInternal)
238#endif /* VBOX_STRICT */
239#define HM_RESTORE_PREEMPT() do { RTThreadPreemptRestore(&PreemptStateInternal); } while(0)
240/** @} */
241
242
243/** Enable for TPR guest patching. */
244#define VBOX_HM_WITH_GUEST_PATCHING
245
246/** @name HM saved state versions
247 * @{
248 */
249#ifdef VBOX_HM_WITH_GUEST_PATCHING
250# define HM_SAVED_STATE_VERSION 5
251# define HM_SAVED_STATE_VERSION_NO_PATCHING 4
252#else
253# define HM_SAVED_STATE_VERSION 4
254# define HM_SAVED_STATE_VERSION_NO_PATCHING 4
255#endif
256#define HM_SAVED_STATE_VERSION_2_0_X 3
257/** @} */
258
259/**
260 * Global per-cpu information. (host)
261 */
262typedef struct HMGLOBALCPUINFO
263{
264 /** The CPU ID. */
265 RTCPUID idCpu;
266 /** The VM_HSAVE_AREA (AMD-V) / VMXON region (Intel) memory backing. */
267 RTR0MEMOBJ hMemObj;
268 /** Current ASID (AMD-V) / VPID (Intel). */
269 uint32_t uCurrentAsid;
270 /** TLB flush count. */
271 uint32_t cTlbFlushes;
272 /** Whether to flush each new ASID/VPID before use. */
273 bool fFlushAsidBeforeUse;
274 /** Configured for VT-x or AMD-V. */
275 bool fConfigured;
276 /** Set if the VBOX_HWVIRTEX_IGNORE_SVM_IN_USE hack is active. */
277 bool fIgnoreAMDVInUseError;
278 /** In use by our code. (for power suspend) */
279 volatile bool fInUse;
280} HMGLOBALCPUINFO;
281/** Pointer to the per-cpu global information. */
282typedef HMGLOBALCPUINFO *PHMGLOBALCPUINFO;
283
284typedef enum
285{
286 HMPENDINGIO_INVALID = 0,
287 HMPENDINGIO_PORT_READ,
288 HMPENDINGIO_PORT_WRITE,
289 HMPENDINGIO_STRING_READ,
290 HMPENDINGIO_STRING_WRITE,
291 /** The usual 32-bit paranoia. */
292 HMPENDINGIO_32BIT_HACK = 0x7fffffff
293} HMPENDINGIO;
294
295
296typedef enum
297{
298 HMTPRINSTR_INVALID,
299 HMTPRINSTR_READ,
300 HMTPRINSTR_READ_SHR4,
301 HMTPRINSTR_WRITE_REG,
302 HMTPRINSTR_WRITE_IMM,
303 HMTPRINSTR_JUMP_REPLACEMENT,
304 /** The usual 32-bit paranoia. */
305 HMTPRINSTR_32BIT_HACK = 0x7fffffff
306} HMTPRINSTR;
307
308typedef struct
309{
310 /** The key is the address of patched instruction. (32 bits GC ptr) */
311 AVLOU32NODECORE Core;
312 /** Original opcode. */
313 uint8_t aOpcode[16];
314 /** Instruction size. */
315 uint32_t cbOp;
316 /** Replacement opcode. */
317 uint8_t aNewOpcode[16];
318 /** Replacement instruction size. */
319 uint32_t cbNewOp;
320 /** Instruction type. */
321 HMTPRINSTR enmType;
322 /** Source operand. */
323 uint32_t uSrcOperand;
324 /** Destination operand. */
325 uint32_t uDstOperand;
326 /** Number of times the instruction caused a fault. */
327 uint32_t cFaults;
328 /** Patch address of the jump replacement. */
329 RTGCPTR32 pJumpTarget;
330} HMTPRPATCH;
331/** Pointer to HMTPRPATCH. */
332typedef HMTPRPATCH *PHMTPRPATCH;
333
334/**
335 * Switcher function, HC to the special 64-bit RC.
336 *
337 * @param pVM Pointer to the VM.
338 * @param offCpumVCpu Offset from pVM->cpum to pVM->aCpus[idCpu].cpum.
339 * @returns Return code indicating the action to take.
340 */
341typedef DECLCALLBACK(int) FNHMSWITCHERHC(PVM pVM, uint32_t offCpumVCpu);
342/** Pointer to switcher function. */
343typedef FNHMSWITCHERHC *PFNHMSWITCHERHC;
344
345/**
346 * HM VM Instance data.
347 * Changes to this must checked against the padding of the hm union in VM!
348 */
349typedef struct HM
350{
351 /** Set when we've initialized VMX or SVM. */
352 bool fInitialized;
353 /** Set if nested paging is enabled. */
354 bool fNestedPaging;
355 /** Set if nested paging is allowed. */
356 bool fAllowNestedPaging;
357 /** Set if large pages are enabled (requires nested paging). */
358 bool fLargePages;
359 /** Set if we can support 64-bit guests or not. */
360 bool fAllow64BitGuests;
361 /** Set if an IO-APIC is configured for this VM. */
362 bool fHasIoApic;
363 /** Set when TPR patching is allowed. */
364 bool fTprPatchingAllowed;
365 /** Set when we initialize VT-x or AMD-V once for all CPUs. */
366 bool fGlobalInit;
367 /** Set when TPR patching is active. */
368 bool fTPRPatchingActive;
369 bool u8Alignment[3];
370
371 /** Host kernel flags that HM might need to know (SUPKERNELFEATURES_XXX). */
372 uint32_t fHostKernelFeatures;
373
374 /** Maximum ASID allowed. */
375 uint32_t uMaxAsid;
376 /** The maximum number of resumes loops allowed in ring-0 (safety precaution).
377 * This number is set much higher when RTThreadPreemptIsPending is reliable. */
378 uint32_t cMaxResumeLoops;
379
380 /** Guest allocated memory for patching purposes. */
381 RTGCPTR pGuestPatchMem;
382 /** Current free pointer inside the patch block. */
383 RTGCPTR pFreeGuestPatchMem;
384 /** Size of the guest patch memory block. */
385 uint32_t cbGuestPatchMem;
386 uint32_t u32Alignment0;
387
388#if HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS)
389 /** 32 to 64 bits switcher entrypoint. */
390 R0PTRTYPE(PFNHMSWITCHERHC) pfnHost32ToGuest64R0;
391 RTR0PTR pvR0Alignment0;
392#endif
393
394 struct
395 {
396 /** Set by the ring-0 side of HM to indicate VMX is supported by the
397 * CPU. */
398 bool fSupported;
399 /** Set when we've enabled VMX. */
400 bool fEnabled;
401 /** Set if VPID is supported. */
402 bool fVpid;
403 /** Set if VT-x VPID is allowed. */
404 bool fAllowVpid;
405 /** Set if unrestricted guest execution is in use (real and protected mode without paging). */
406 bool fUnrestrictedGuest;
407 /** Set if unrestricted guest execution is allowed to be used. */
408 bool fAllowUnrestricted;
409 /** Whether we're using the preemption timer or not. */
410 bool fUsePreemptTimer;
411 /** The shift mask employed by the VMX-Preemption timer. */
412 uint8_t cPreemptTimerShift;
413
414 /** Virtual address of the TSS page used for real mode emulation. */
415 R3PTRTYPE(PVBOXTSS) pRealModeTSS;
416 /** Virtual address of the identity page table used for real mode and protected mode without paging emulation in EPT mode. */
417 R3PTRTYPE(PX86PD) pNonPagingModeEPTPageTable;
418
419 /** Physical address of the APIC-access page. */
420 RTHCPHYS HCPhysApicAccess;
421 /** R0 memory object for the APIC-access page. */
422 RTR0MEMOBJ hMemObjApicAccess;
423 /** Virtual address of the APIC-access page. */
424 R0PTRTYPE(uint8_t *) pbApicAccess;
425
426#ifdef VBOX_WITH_CRASHDUMP_MAGIC
427 RTHCPHYS HCPhysScratch;
428 RTR0MEMOBJ hMemObjScratch;
429 R0PTRTYPE(uint8_t *) pbScratch;
430#endif
431
432 /** Internal Id of which flush-handler to use for tagged-TLB entries. */
433 uint32_t uFlushTaggedTlb;
434
435 /** Pause-loop exiting (PLE) gap in ticks. */
436 uint32_t cPleGapTicks;
437 /** Pause-loop exiting (PLE) window in ticks. */
438 uint32_t cPleWindowTicks;
439 uint32_t u32Alignment0;
440
441 /** Host CR4 value (set by ring-0 VMX init) */
442 uint64_t u64HostCr4;
443
444 /** Host EFER value (set by ring-0 VMX init) */
445 uint64_t u64HostEfer;
446 /** Whether the CPU supports VMCS fields for swapping EFER. */
447 bool fSupportsVmcsEfer;
448 uint8_t u8Alignment2[7];
449
450 /** VMX MSR values. */
451 VMXMSRS Msrs;
452
453 /** Flush types for invept & invvpid; they depend on capabilities. */
454 VMXFLUSHEPT enmFlushEpt;
455 VMXFLUSHVPID enmFlushVpid;
456
457 /** Host-physical address for a failing VMXON instruction. */
458 RTHCPHYS HCPhysVmxEnableError;
459 } vmx;
460
461 struct
462 {
463 /** Set by the ring-0 side of HM to indicate SVM is supported by the
464 * CPU. */
465 bool fSupported;
466 /** Set when we've enabled SVM. */
467 bool fEnabled;
468 /** Set if erratum 170 affects the AMD cpu. */
469 bool fAlwaysFlushTLB;
470 /** Set when the hack to ignore VERR_SVM_IN_USE is active. */
471 bool fIgnoreInUseError;
472 uint8_t u8Alignment0[4];
473
474 /** Physical address of the IO bitmap (12kb). */
475 RTHCPHYS HCPhysIOBitmap;
476 /** R0 memory object for the IO bitmap (12kb). */
477 RTR0MEMOBJ hMemObjIOBitmap;
478 /** Virtual address of the IO bitmap. */
479 R0PTRTYPE(void *) pvIOBitmap;
480
481 /* HWCR MSR (for diagnostics) */
482 uint64_t u64MsrHwcr;
483
484 /** SVM revision. */
485 uint32_t u32Rev;
486 /** SVM feature bits from cpuid 0x8000000a */
487 uint32_t u32Features;
488
489 /** Pause filter counter. */
490 uint16_t cPauseFilter;
491 /** Pause filter treshold in ticks. */
492 uint16_t cPauseFilterThresholdTicks;
493 uint32_t u32Alignment0;
494 } svm;
495
496 /**
497 * AVL tree with all patches (active or disabled) sorted by guest instruction
498 * address.
499 */
500 AVLOU32TREE PatchTree;
501 uint32_t cPatches;
502 HMTPRPATCH aPatches[64];
503
504 struct
505 {
506 uint32_t u32AMDFeatureECX;
507 uint32_t u32AMDFeatureEDX;
508 } cpuid;
509
510 /** Saved error from detection */
511 int32_t lLastError;
512
513 /** HMR0Init was run */
514 bool fHMR0Init;
515 bool u8Alignment1[3];
516
517 STAMCOUNTER StatTprPatchSuccess;
518 STAMCOUNTER StatTprPatchFailure;
519 STAMCOUNTER StatTprReplaceSuccess;
520 STAMCOUNTER StatTprReplaceFailure;
521} HM;
522/** Pointer to HM VM instance data. */
523typedef HM *PHM;
524
525AssertCompileMemberAlignment(HM, StatTprPatchSuccess, 8);
526
527/* Maximum number of cached entries. */
528#define VMCSCACHE_MAX_ENTRY 128
529
530/**
531 * Structure for storing read and write VMCS actions.
532 */
533typedef struct VMCSCACHE
534{
535#ifdef VBOX_WITH_CRASHDUMP_MAGIC
536 /* Magic marker for searching in crash dumps. */
537 uint8_t aMagic[16];
538 uint64_t uMagic;
539 uint64_t u64TimeEntry;
540 uint64_t u64TimeSwitch;
541 uint64_t cResume;
542 uint64_t interPD;
543 uint64_t pSwitcher;
544 uint32_t uPos;
545 uint32_t idCpu;
546#endif
547 /* CR2 is saved here for EPT syncing. */
548 uint64_t cr2;
549 struct
550 {
551 uint32_t cValidEntries;
552 uint32_t uAlignment;
553 uint32_t aField[VMCSCACHE_MAX_ENTRY];
554 uint64_t aFieldVal[VMCSCACHE_MAX_ENTRY];
555 } Write;
556 struct
557 {
558 uint32_t cValidEntries;
559 uint32_t uAlignment;
560 uint32_t aField[VMCSCACHE_MAX_ENTRY];
561 uint64_t aFieldVal[VMCSCACHE_MAX_ENTRY];
562 } Read;
563#ifdef VBOX_STRICT
564 struct
565 {
566 RTHCPHYS HCPhysCpuPage;
567 RTHCPHYS HCPhysVmcs;
568 RTGCPTR pCache;
569 RTGCPTR pCtx;
570 } TestIn;
571 struct
572 {
573 RTHCPHYS HCPhysVmcs;
574 RTGCPTR pCache;
575 RTGCPTR pCtx;
576 uint64_t eflags;
577 uint64_t cr8;
578 } TestOut;
579 struct
580 {
581 uint64_t param1;
582 uint64_t param2;
583 uint64_t param3;
584 uint64_t param4;
585 } ScratchPad;
586#endif
587} VMCSCACHE;
588/** Pointer to VMCSCACHE. */
589typedef VMCSCACHE *PVMCSCACHE;
590AssertCompileSizeAlignment(VMCSCACHE, 8);
591
592/** VMX StartVM function. */
593typedef DECLCALLBACK(int) FNHMVMXSTARTVM(RTHCUINT fResume, PCPUMCTX pCtx, PVMCSCACHE pCache, PVM pVM, PVMCPU pVCpu);
594/** Pointer to a VMX StartVM function. */
595typedef R0PTRTYPE(FNHMVMXSTARTVM *) PFNHMVMXSTARTVM;
596
597/** SVM VMRun function. */
598typedef DECLCALLBACK(int) FNHMSVMVMRUN(RTHCPHYS pVmcbHostPhys, RTHCPHYS pVmcbPhys, PCPUMCTX pCtx, PVM pVM, PVMCPU pVCpu);
599/** Pointer to a SVM VMRun function. */
600typedef R0PTRTYPE(FNHMSVMVMRUN *) PFNHMSVMVMRUN;
601
602/**
603 * HM VMCPU Instance data.
604 *
605 * Note! If you change members of this struct, make sure to check if the
606 * assembly counterpart in HMInternal.mac needs to be updated as well.
607 */
608typedef struct HMCPU
609{
610 /** Set if we need to flush the TLB during the world switch. */
611 bool fForceTLBFlush;
612 /** Set when we're using VT-x or AMD-V at that moment. */
613 bool fActive;
614 /** Set when the TLB has been checked until we return from the world switch. */
615 volatile bool fCheckedTLBFlush;
616 /** Whether we're executing a single instruction. */
617 bool fSingleInstruction;
618 /** Set if we need to clear the trap flag because of single stepping. */
619 bool fClearTrapFlag;
620 /** Whether we've completed the inner HM leave function. */
621 bool fLeaveDone;
622 /** Whether we're using the hyper DR7 or guest DR7. */
623 bool fUsingHyperDR7;
624 /** Whether to preload the guest-FPU state to avoid #NM VM-exit overhead. */
625 bool fPreloadGuestFpu;
626 /** Set if XCR0 needs to be loaded and saved when entering and exiting guest
627 * code execution. */
628 bool fLoadSaveGuestXcr0;
629
630 /** Whether #UD needs to be intercepted (required by certain GIM providers). */
631 bool fGIMTrapXcptUD;
632 /** Whether paravirt. hypercalls are enabled. */
633 bool fHypercallsEnabled;
634 uint8_t u8Alignment0[5];
635
636 /** World switch exit counter. */
637 volatile uint32_t cWorldSwitchExits;
638 /** HM_CHANGED_* flags. */
639 volatile uint32_t fContextUseFlags;
640 /** Id of the last cpu we were executing code on (NIL_RTCPUID for the first
641 * time). */
642 RTCPUID idLastCpu;
643 /** TLB flush count. */
644 uint32_t cTlbFlushes;
645 /** Current ASID in use by the VM. */
646 uint32_t uCurrentAsid;
647 /** An additional error code used for some gurus. */
648 uint32_t u32HMError;
649 /** Host's TSC_AUX MSR (used when RDTSCP doesn't cause VM-exits). */
650 uint64_t u64HostTscAux;
651
652 struct
653 {
654 /** Ring 0 handlers for VT-x. */
655 PFNHMVMXSTARTVM pfnStartVM;
656#if HC_ARCH_BITS == 32
657 uint32_t u32Alignment0;
658#endif
659 /** Current VMX_VMCS32_CTRL_PIN_EXEC. */
660 uint32_t u32PinCtls;
661 /** Current VMX_VMCS32_CTRL_PROC_EXEC. */
662 uint32_t u32ProcCtls;
663 /** Current VMX_VMCS32_CTRL_PROC_EXEC2. */
664 uint32_t u32ProcCtls2;
665 /** Current VMX_VMCS32_CTRL_EXIT. */
666 uint32_t u32ExitCtls;
667 /** Current VMX_VMCS32_CTRL_ENTRY. */
668 uint32_t u32EntryCtls;
669
670 /** Current CR0 mask. */
671 uint32_t u32CR0Mask;
672 /** Current CR4 mask. */
673 uint32_t u32CR4Mask;
674 /** Current exception bitmap. */
675 uint32_t u32XcptBitmap;
676 /** The updated-guest-state mask. */
677 volatile uint32_t fUpdatedGuestState;
678 uint32_t u32Alignment1;
679
680 /** Physical address of the VM control structure (VMCS). */
681 RTHCPHYS HCPhysVmcs;
682 /** R0 memory object for the VM control structure (VMCS). */
683 RTR0MEMOBJ hMemObjVmcs;
684 /** Virtual address of the VM control structure (VMCS). */
685 R0PTRTYPE(void *) pvVmcs;
686
687 /** Physical address of the virtual APIC page for TPR caching. */
688 RTHCPHYS HCPhysVirtApic;
689 /** R0 memory object for the virtual APIC page for TPR caching. */
690 RTR0MEMOBJ hMemObjVirtApic;
691 /** Virtual address of the virtual APIC page for TPR caching. */
692 R0PTRTYPE(uint8_t *) pbVirtApic;
693
694 /** Physical address of the MSR bitmap. */
695 RTHCPHYS HCPhysMsrBitmap;
696 /** R0 memory object for the MSR bitmap. */
697 RTR0MEMOBJ hMemObjMsrBitmap;
698 /** Virtual address of the MSR bitmap. */
699 R0PTRTYPE(void *) pvMsrBitmap;
700
701 /** Physical address of the VM-entry MSR-load and VM-exit MSR-store area (used
702 * for guest MSRs). */
703 RTHCPHYS HCPhysGuestMsr;
704 /** R0 memory object of the VM-entry MSR-load and VM-exit MSR-store area
705 * (used for guest MSRs). */
706 RTR0MEMOBJ hMemObjGuestMsr;
707 /** Virtual address of the VM-entry MSR-load and VM-exit MSR-store area (used
708 * for guest MSRs). */
709 R0PTRTYPE(void *) pvGuestMsr;
710
711 /** Physical address of the VM-exit MSR-load area (used for host MSRs). */
712 RTHCPHYS HCPhysHostMsr;
713 /** R0 memory object for the VM-exit MSR-load area (used for host MSRs). */
714 RTR0MEMOBJ hMemObjHostMsr;
715 /** Virtual address of the VM-exit MSR-load area (used for host MSRs). */
716 R0PTRTYPE(void *) pvHostMsr;
717
718 /** Current EPTP. */
719 RTHCPHYS HCPhysEPTP;
720
721 /** Number of guest/host MSR pairs in the auto-load/store area. */
722 uint32_t cMsrs;
723 /** Whether the host MSR values are up-to-date in the auto-load/store area. */
724 bool fUpdatedHostMsrs;
725 uint8_t u8Alignment0[3];
726
727 /** Host LSTAR MSR value to restore lazily while leaving VT-x. */
728 uint64_t u64HostLStarMsr;
729 /** Host STAR MSR value to restore lazily while leaving VT-x. */
730 uint64_t u64HostStarMsr;
731 /** Host SF_MASK MSR value to restore lazily while leaving VT-x. */
732 uint64_t u64HostSFMaskMsr;
733 /** Host KernelGS-Base MSR value to restore lazily while leaving VT-x. */
734 uint64_t u64HostKernelGSBaseMsr;
735 /** A mask of which MSRs have been swapped and need restoration. */
736 uint32_t fLazyMsrs;
737 uint32_t u32Alignment2;
738
739 /** The cached APIC-base MSR used for identifying when to map the HC physical APIC-access page. */
740 uint64_t u64MsrApicBase;
741 /** Last use TSC offset value. (cached) */
742 uint64_t u64TSCOffset;
743
744 /** VMCS cache. */
745 VMCSCACHE VMCSCache;
746
747 /** Real-mode emulation state. */
748 struct
749 {
750 X86DESCATTR AttrCS;
751 X86DESCATTR AttrDS;
752 X86DESCATTR AttrES;
753 X86DESCATTR AttrFS;
754 X86DESCATTR AttrGS;
755 X86DESCATTR AttrSS;
756 X86EFLAGS Eflags;
757 uint32_t fRealOnV86Active;
758 } RealMode;
759
760 /** VT-x error-reporting (mainly for ring-3 propagation). */
761 struct
762 {
763 uint64_t u64VMCSPhys;
764 uint32_t u32VMCSRevision;
765 uint32_t u32InstrError;
766 uint32_t u32ExitReason;
767 RTCPUID idEnteredCpu;
768 RTCPUID idCurrentCpu;
769 uint32_t u32Alignment0;
770 } LastError;
771
772 /** Current state of the VMCS. */
773 uint32_t uVmcsState;
774 /** Which host-state bits to restore before being preempted. */
775 uint32_t fRestoreHostFlags;
776 /** The host-state restoration structure. */
777 VMXRESTOREHOST RestoreHost;
778
779 /** Set if guest was executing in real mode (extra checks). */
780 bool fWasInRealMode;
781 uint8_t u8Alignment1[7];
782 } vmx;
783
784 struct
785 {
786 /** Ring 0 handlers for VT-x. */
787 PFNHMSVMVMRUN pfnVMRun;
788#if HC_ARCH_BITS == 32
789 uint32_t u32Alignment0;
790#endif
791
792 /** Physical address of the host VMCB which holds additional host-state. */
793 RTHCPHYS HCPhysVmcbHost;
794 /** R0 memory object for the host VMCB which holds additional host-state. */
795 RTR0MEMOBJ hMemObjVmcbHost;
796 /** Virtual address of the host VMCB which holds additional host-state. */
797 R0PTRTYPE(void *) pvVmcbHost;
798
799 /** Physical address of the guest VMCB. */
800 RTHCPHYS HCPhysVmcb;
801 /** R0 memory object for the guest VMCB. */
802 RTR0MEMOBJ hMemObjVmcb;
803 /** Virtual address of the guest VMCB. */
804 R0PTRTYPE(void *) pvVmcb;
805
806 /** Physical address of the MSR bitmap (8 KB). */
807 RTHCPHYS HCPhysMsrBitmap;
808 /** R0 memory object for the MSR bitmap (8 KB). */
809 RTR0MEMOBJ hMemObjMsrBitmap;
810 /** Virtual address of the MSR bitmap. */
811 R0PTRTYPE(void *) pvMsrBitmap;
812
813 /** Whether VTPR with V_INTR_MASKING set is in effect, indicating
814 * we should check if the VTPR changed on every VM-exit. */
815 bool fSyncVTpr;
816 uint8_t u8Alignment0[7];
817 } svm;
818
819 /** Event injection state. */
820 struct
821 {
822 uint32_t fPending;
823 uint32_t u32ErrCode;
824 uint32_t cbInstr;
825 uint32_t u32Padding; /**< Explicit alignment padding. */
826 uint64_t u64IntInfo;
827 RTGCUINTPTR GCPtrFaultAddress;
828 } Event;
829
830 /** IO Block emulation state. */
831 struct
832 {
833 bool fEnabled;
834 uint8_t u8Align[7];
835
836 /** RIP at the start of the io code we wish to emulate in the recompiler. */
837 RTGCPTR GCPtrFunctionEip;
838
839 uint64_t cr0;
840 } EmulateIoBlock;
841
842 struct
843 {
844 /** Pending IO operation type. */
845 HMPENDINGIO enmType;
846 uint32_t u32Alignment0;
847 RTGCPTR GCPtrRip;
848 RTGCPTR GCPtrRipNext;
849 union
850 {
851 struct
852 {
853 uint32_t uPort;
854 uint32_t uAndVal;
855 uint32_t cbSize;
856 } Port;
857 uint64_t aRaw[2];
858 } s;
859 } PendingIO;
860
861 /** The PAE PDPEs used with Nested Paging (only valid when
862 * VMCPU_FF_HM_UPDATE_PAE_PDPES is set). */
863 X86PDPE aPdpes[4];
864
865 /** Current shadow paging mode. */
866 PGMMODE enmShadowMode;
867
868 /** The CPU ID of the CPU currently owning the VMCS. Set in
869 * HMR0Enter and cleared in HMR0Leave. */
870 RTCPUID idEnteredCpu;
871
872 /** VT-x/AMD-V VM-exit/#VMXEXIT history, circular array. */
873 uint16_t auExitHistory[31];
874 /** The index of the next free slot in the history array. */
875 uint16_t idxExitHistoryFree;
876
877 /** For saving stack space, the disassembler state is allocated here instead of
878 * on the stack. */
879 DISCPUSTATE DisState;
880
881 STAMPROFILEADV StatEntry;
882 STAMPROFILEADV StatExit1;
883 STAMPROFILEADV StatExit2;
884 STAMPROFILEADV StatExitIO;
885 STAMPROFILEADV StatExitMovCRx;
886 STAMPROFILEADV StatExitXcptNmi;
887 STAMPROFILEADV StatLoadGuestState;
888 STAMPROFILEADV StatInGC;
889
890#if HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS)
891 STAMPROFILEADV StatWorldSwitch3264;
892#endif
893 STAMPROFILEADV StatPoke;
894 STAMPROFILEADV StatSpinPoke;
895 STAMPROFILEADV StatSpinPokeFailed;
896
897 STAMCOUNTER StatInjectInterrupt;
898 STAMCOUNTER StatInjectXcpt;
899 STAMCOUNTER StatInjectPendingReflect;
900
901 STAMCOUNTER StatExitAll;
902 STAMCOUNTER StatExitShadowNM;
903 STAMCOUNTER StatExitGuestNM;
904 STAMCOUNTER StatExitShadowPF; /* Misleading, currently used for MMIO #PFs as well. */
905 STAMCOUNTER StatExitShadowPFEM;
906 STAMCOUNTER StatExitGuestPF;
907 STAMCOUNTER StatExitGuestUD;
908 STAMCOUNTER StatExitGuestSS;
909 STAMCOUNTER StatExitGuestNP;
910 STAMCOUNTER StatExitGuestTS;
911 STAMCOUNTER StatExitGuestGP;
912 STAMCOUNTER StatExitGuestDE;
913 STAMCOUNTER StatExitGuestDB;
914 STAMCOUNTER StatExitGuestMF;
915 STAMCOUNTER StatExitGuestBP;
916 STAMCOUNTER StatExitGuestXF;
917 STAMCOUNTER StatExitGuestXcpUnk;
918 STAMCOUNTER StatExitInvlpg;
919 STAMCOUNTER StatExitInvd;
920 STAMCOUNTER StatExitWbinvd;
921 STAMCOUNTER StatExitPause;
922 STAMCOUNTER StatExitCpuid;
923 STAMCOUNTER StatExitRdtsc;
924 STAMCOUNTER StatExitRdtscp;
925 STAMCOUNTER StatExitRdpmc;
926 STAMCOUNTER StatExitVmcall;
927 STAMCOUNTER StatExitRdrand;
928 STAMCOUNTER StatExitCli;
929 STAMCOUNTER StatExitSti;
930 STAMCOUNTER StatExitPushf;
931 STAMCOUNTER StatExitPopf;
932 STAMCOUNTER StatExitIret;
933 STAMCOUNTER StatExitInt;
934 STAMCOUNTER StatExitCRxWrite[16];
935 STAMCOUNTER StatExitCRxRead[16];
936 STAMCOUNTER StatExitDRxWrite;
937 STAMCOUNTER StatExitDRxRead;
938 STAMCOUNTER StatExitRdmsr;
939 STAMCOUNTER StatExitWrmsr;
940 STAMCOUNTER StatExitClts;
941 STAMCOUNTER StatExitXdtrAccess;
942 STAMCOUNTER StatExitHlt;
943 STAMCOUNTER StatExitMwait;
944 STAMCOUNTER StatExitMonitor;
945 STAMCOUNTER StatExitLmsw;
946 STAMCOUNTER StatExitIOWrite;
947 STAMCOUNTER StatExitIORead;
948 STAMCOUNTER StatExitIOStringWrite;
949 STAMCOUNTER StatExitIOStringRead;
950 STAMCOUNTER StatExitIntWindow;
951 STAMCOUNTER StatExitExtInt;
952 STAMCOUNTER StatExitHostNmiInGC;
953 STAMCOUNTER StatExitPreemptTimer;
954 STAMCOUNTER StatExitTprBelowThreshold;
955 STAMCOUNTER StatExitTaskSwitch;
956 STAMCOUNTER StatExitMtf;
957 STAMCOUNTER StatExitApicAccess;
958 STAMCOUNTER StatPendingHostIrq;
959
960 STAMCOUNTER StatFlushPage;
961 STAMCOUNTER StatFlushPageManual;
962 STAMCOUNTER StatFlushPhysPageManual;
963 STAMCOUNTER StatFlushTlb;
964 STAMCOUNTER StatFlushTlbManual;
965 STAMCOUNTER StatFlushTlbWorldSwitch;
966 STAMCOUNTER StatNoFlushTlbWorldSwitch;
967 STAMCOUNTER StatFlushEntire;
968 STAMCOUNTER StatFlushAsid;
969 STAMCOUNTER StatFlushNestedPaging;
970 STAMCOUNTER StatFlushTlbInvlpgVirt;
971 STAMCOUNTER StatFlushTlbInvlpgPhys;
972 STAMCOUNTER StatTlbShootdown;
973 STAMCOUNTER StatTlbShootdownFlush;
974
975 STAMCOUNTER StatSwitchGuestIrq;
976 STAMCOUNTER StatSwitchHmToR3FF;
977 STAMCOUNTER StatSwitchExitToR3;
978 STAMCOUNTER StatSwitchLongJmpToR3;
979 STAMCOUNTER StatSwitchMaxResumeLoops;
980 STAMCOUNTER StatSwitchHltToR3;
981 STAMCOUNTER StatSwitchApicAccessToR3;
982 STAMCOUNTER StatSwitchPreempt;
983 STAMCOUNTER StatSwitchPreemptSaveHostState;
984
985 STAMCOUNTER StatTscParavirt;
986 STAMCOUNTER StatTscOffset;
987 STAMCOUNTER StatTscIntercept;
988
989 STAMCOUNTER StatExitReasonNpf;
990 STAMCOUNTER StatDRxArmed;
991 STAMCOUNTER StatDRxContextSwitch;
992 STAMCOUNTER StatDRxIoCheck;
993
994 STAMCOUNTER StatLoadMinimal;
995 STAMCOUNTER StatLoadFull;
996
997 STAMCOUNTER StatVmxCheckBadRmSelBase;
998 STAMCOUNTER StatVmxCheckBadRmSelLimit;
999 STAMCOUNTER StatVmxCheckRmOk;
1000
1001 STAMCOUNTER StatVmxCheckBadSel;
1002 STAMCOUNTER StatVmxCheckBadRpl;
1003 STAMCOUNTER StatVmxCheckBadLdt;
1004 STAMCOUNTER StatVmxCheckBadTr;
1005 STAMCOUNTER StatVmxCheckPmOk;
1006
1007#if HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS)
1008 STAMCOUNTER StatFpu64SwitchBack;
1009 STAMCOUNTER StatDebug64SwitchBack;
1010#endif
1011
1012#ifdef VBOX_WITH_STATISTICS
1013 R3PTRTYPE(PSTAMCOUNTER) paStatExitReason;
1014 R0PTRTYPE(PSTAMCOUNTER) paStatExitReasonR0;
1015 R3PTRTYPE(PSTAMCOUNTER) paStatInjectedIrqs;
1016 R0PTRTYPE(PSTAMCOUNTER) paStatInjectedIrqsR0;
1017#endif
1018#ifdef HM_PROFILE_EXIT_DISPATCH
1019 STAMPROFILEADV StatExitDispatch;
1020#endif
1021} HMCPU;
1022/** Pointer to HM VMCPU instance data. */
1023typedef HMCPU *PHMCPU;
1024AssertCompileMemberAlignment(HMCPU, vmx, 8);
1025AssertCompileMemberAlignment(HMCPU, svm, 8);
1026AssertCompileMemberAlignment(HMCPU, Event, 8);
1027
1028
1029#ifdef IN_RING0
1030VMMR0DECL(PHMGLOBALCPUINFO) HMR0GetCurrentCpu(void);
1031VMMR0DECL(PHMGLOBALCPUINFO) HMR0GetCurrentCpuEx(RTCPUID idCpu);
1032
1033
1034# ifdef VBOX_STRICT
1035VMMR0DECL(void) HMDumpRegs(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx);
1036VMMR0DECL(void) HMR0DumpDescriptor(PCX86DESCHC pDesc, RTSEL Sel, const char *pszMsg);
1037# else
1038# define HMDumpRegs(a, b ,c) do { } while (0)
1039# define HMR0DumpDescriptor(a, b, c) do { } while (0)
1040# endif /* VBOX_STRICT */
1041
1042# ifdef VBOX_WITH_KERNEL_USING_XMM
1043DECLASM(int) HMR0VMXStartVMWrapXMM(RTHCUINT fResume, PCPUMCTX pCtx, PVMCSCACHE pCache, PVM pVM, PVMCPU pVCpu, PFNHMVMXSTARTVM pfnStartVM);
1044DECLASM(int) HMR0SVMRunWrapXMM(RTHCPHYS pVmcbHostPhys, RTHCPHYS pVmcbPhys, PCPUMCTX pCtx, PVM pVM, PVMCPU pVCpu, PFNHMSVMVMRUN pfnVMRun);
1045# endif
1046
1047#endif /* IN_RING0 */
1048
1049/** @} */
1050
1051RT_C_DECLS_END
1052
1053#endif
1054
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