VirtualBox

source: vbox/trunk/src/VBox/VMM/include/HMInternal.h@ 60189

Last change on this file since 60189 was 59020, checked in by vboxsync, 9 years ago

VMM/HM: Log IA32_SMM_MONITOR_CTL for VT-x hosts, useful diagnostic info.
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1/* $Id: HMInternal.h 59020 2015-12-07 12:26:47Z vboxsync $ */
2/** @file
3 * HM - Internal header file.
4 */
5
6/*
7 * Copyright (C) 2006-2015 Oracle Corporation
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 */
17
18#ifndef ___HMInternal_h
19#define ___HMInternal_h
20
21#include <VBox/cdefs.h>
22#include <VBox/types.h>
23#include <VBox/vmm/em.h>
24#include <VBox/vmm/stam.h>
25#include <VBox/dis.h>
26#include <VBox/vmm/hm.h>
27#include <VBox/vmm/hm_vmx.h>
28#include <VBox/vmm/pgm.h>
29#include <VBox/vmm/cpum.h>
30#include <iprt/memobj.h>
31#include <iprt/cpuset.h>
32#include <iprt/mp.h>
33#include <iprt/avl.h>
34#include <iprt/string.h>
35
36#if defined(RT_OS_DARWIN) && HC_ARCH_BITS == 32
37# error "32-bit darwin is no longer supported. Go back to 4.3 or earlier!"
38#endif
39
40#if HC_ARCH_BITS == 64 || defined (VBOX_WITH_64_BITS_GUESTS)
41/* Enable 64 bits guest support. */
42# define VBOX_ENABLE_64_BITS_GUESTS
43#endif
44
45#if HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS)
46# define VMX_USE_CACHED_VMCS_ACCESSES
47#endif
48
49/** @def HM_PROFILE_EXIT_DISPATCH
50 * Enables profiling of the VM exit handler dispatching. */
51#if 0 || defined(DOXYGEN_RUNNING)
52# define HM_PROFILE_EXIT_DISPATCH
53#endif
54
55RT_C_DECLS_BEGIN
56
57
58/** @defgroup grp_hm_int Internal
59 * @ingroup grp_hm
60 * @internal
61 * @{
62 */
63
64/** @def HMCPU_CF_CLEAR
65 * Clears a HM-context flag.
66 *
67 * @param pVCpu The cross context virtual CPU structure.
68 * @param fFlag The flag to clear.
69 */
70#define HMCPU_CF_CLEAR(pVCpu, fFlag) (ASMAtomicUoAndU32(&(pVCpu)->hm.s.fContextUseFlags, ~(fFlag)))
71
72/** @def HMCPU_CF_SET
73 * Sets a HM-context flag.
74 *
75 * @param pVCpu The cross context virtual CPU structure.
76 * @param fFlag The flag to set.
77 */
78#define HMCPU_CF_SET(pVCpu, fFlag) (ASMAtomicUoOrU32(&(pVCpu)->hm.s.fContextUseFlags, (fFlag)))
79
80/** @def HMCPU_CF_IS_SET
81 * Checks if all the flags in the specified HM-context set is pending.
82 *
83 * @param pVCpu The cross context virtual CPU structure.
84 * @param fFlag The flag to check.
85 */
86#define HMCPU_CF_IS_SET(pVCpu, fFlag) ((ASMAtomicUoReadU32(&(pVCpu)->hm.s.fContextUseFlags) & (fFlag)) == (fFlag))
87
88/** @def HMCPU_CF_IS_PENDING
89 * Checks if one or more of the flags in the specified HM-context set is
90 * pending.
91 *
92 * @param pVCpu The cross context virtual CPU structure.
93 * @param fFlags The flags to check for.
94 */
95#define HMCPU_CF_IS_PENDING(pVCpu, fFlags) RT_BOOL(ASMAtomicUoReadU32(&(pVCpu)->hm.s.fContextUseFlags) & (fFlags))
96
97/** @def HMCPU_CF_IS_PENDING_ONLY
98 * Checks if -only- one or more of the specified HM-context flags is pending.
99 *
100 * @param pVCpu The cross context virtual CPU structure.
101 * @param fFlags The flags to check for.
102 */
103#define HMCPU_CF_IS_PENDING_ONLY(pVCpu, fFlags) !RT_BOOL(ASMAtomicUoReadU32(&(pVCpu)->hm.s.fContextUseFlags) & ~(fFlags))
104
105/** @def HMCPU_CF_IS_SET_ONLY
106 * Checks if -only- all the flags in the specified HM-context set is pending.
107 *
108 * @param pVCpu The cross context virtual CPU structure.
109 * @param fFlags The flags to check for.
110 */
111#define HMCPU_CF_IS_SET_ONLY(pVCpu, fFlags) (ASMAtomicUoReadU32(&(pVCpu)->hm.s.fContextUseFlags) == (fFlags))
112
113/** @def HMCPU_CF_RESET_TO
114 * Resets the HM-context flags to the specified value.
115 *
116 * @param pVCpu The cross context virtual CPU structure.
117 * @param fFlags The new value.
118 */
119#define HMCPU_CF_RESET_TO(pVCpu, fFlags) (ASMAtomicUoWriteU32(&(pVCpu)->hm.s.fContextUseFlags, (fFlags)))
120
121/** @def HMCPU_CF_VALUE
122 * Returns the current HM-context flags value.
123 *
124 * @param pVCpu The cross context virtual CPU structure.
125 */
126#define HMCPU_CF_VALUE(pVCpu) (ASMAtomicUoReadU32(&(pVCpu)->hm.s.fContextUseFlags))
127
128
129/** Resets/initializes the VM-exit/\#VMEXIT history array. */
130#define HMCPU_EXIT_HISTORY_RESET(pVCpu) (memset(&(pVCpu)->hm.s.auExitHistory, 0xff, sizeof((pVCpu)->hm.s.auExitHistory)))
131
132/** Updates the VM-exit/\#VMEXIT history array. */
133#define HMCPU_EXIT_HISTORY_ADD(pVCpu, a_ExitReason) \
134 do { \
135 AssertMsg((pVCpu)->hm.s.idxExitHistoryFree < RT_ELEMENTS((pVCpu)->hm.s.auExitHistory), ("%u\n", (pVCpu)->hm.s.idxExitHistoryFree)); \
136 (pVCpu)->hm.s.auExitHistory[(pVCpu)->hm.s.idxExitHistoryFree++] = (uint16_t)(a_ExitReason); \
137 if ((pVCpu)->hm.s.idxExitHistoryFree == RT_ELEMENTS((pVCpu)->hm.s.auExitHistory)) \
138 (pVCpu)->hm.s.idxExitHistoryFree = 0; \
139 (pVCpu)->hm.s.auExitHistory[(pVCpu)->hm.s.idxExitHistoryFree] = UINT16_MAX; \
140 } while (0)
141
142/** Maximum number of exit reason statistics counters. */
143#define MAX_EXITREASON_STAT 0x100
144#define MASK_EXITREASON_STAT 0xff
145#define MASK_INJECT_IRQ_STAT 0xff
146
147/** @name HM changed flags.
148 * These flags are used to keep track of which important registers that
149 * have been changed since last they were reset.
150 * @{
151 */
152#define HM_CHANGED_GUEST_CR0 RT_BIT(0) /* Shared */
153#define HM_CHANGED_GUEST_CR3 RT_BIT(1)
154#define HM_CHANGED_GUEST_CR4 RT_BIT(2)
155#define HM_CHANGED_GUEST_GDTR RT_BIT(3)
156#define HM_CHANGED_GUEST_IDTR RT_BIT(4)
157#define HM_CHANGED_GUEST_LDTR RT_BIT(5)
158#define HM_CHANGED_GUEST_TR RT_BIT(6)
159#define HM_CHANGED_GUEST_SEGMENT_REGS RT_BIT(7)
160#define HM_CHANGED_GUEST_DEBUG RT_BIT(8) /* Shared */
161#define HM_CHANGED_GUEST_RIP RT_BIT(9)
162#define HM_CHANGED_GUEST_RSP RT_BIT(10)
163#define HM_CHANGED_GUEST_RFLAGS RT_BIT(11)
164#define HM_CHANGED_GUEST_CR2 RT_BIT(12)
165#define HM_CHANGED_GUEST_SYSENTER_CS_MSR RT_BIT(13)
166#define HM_CHANGED_GUEST_SYSENTER_EIP_MSR RT_BIT(14)
167#define HM_CHANGED_GUEST_SYSENTER_ESP_MSR RT_BIT(15)
168#define HM_CHANGED_GUEST_EFER_MSR RT_BIT(16)
169#define HM_CHANGED_GUEST_LAZY_MSRS RT_BIT(17) /* Shared */
170#define HM_CHANGED_GUEST_XCPT_INTERCEPTS RT_BIT(18)
171/* VT-x specific state. */
172#define HM_CHANGED_VMX_GUEST_AUTO_MSRS RT_BIT(19)
173#define HM_CHANGED_VMX_GUEST_ACTIVITY_STATE RT_BIT(20)
174#define HM_CHANGED_VMX_GUEST_APIC_STATE RT_BIT(21)
175#define HM_CHANGED_VMX_ENTRY_CTLS RT_BIT(22)
176#define HM_CHANGED_VMX_EXIT_CTLS RT_BIT(23)
177/* AMD-V specific state. */
178#define HM_CHANGED_SVM_GUEST_APIC_STATE RT_BIT(19)
179#define HM_CHANGED_SVM_RESERVED1 RT_BIT(20)
180#define HM_CHANGED_SVM_RESERVED2 RT_BIT(21)
181#define HM_CHANGED_SVM_RESERVED3 RT_BIT(22)
182#define HM_CHANGED_SVM_RESERVED4 RT_BIT(23)
183
184#define HM_CHANGED_ALL_GUEST ( HM_CHANGED_GUEST_CR0 \
185 | HM_CHANGED_GUEST_CR3 \
186 | HM_CHANGED_GUEST_CR4 \
187 | HM_CHANGED_GUEST_GDTR \
188 | HM_CHANGED_GUEST_IDTR \
189 | HM_CHANGED_GUEST_LDTR \
190 | HM_CHANGED_GUEST_TR \
191 | HM_CHANGED_GUEST_SEGMENT_REGS \
192 | HM_CHANGED_GUEST_DEBUG \
193 | HM_CHANGED_GUEST_RIP \
194 | HM_CHANGED_GUEST_RSP \
195 | HM_CHANGED_GUEST_RFLAGS \
196 | HM_CHANGED_GUEST_CR2 \
197 | HM_CHANGED_GUEST_SYSENTER_CS_MSR \
198 | HM_CHANGED_GUEST_SYSENTER_EIP_MSR \
199 | HM_CHANGED_GUEST_SYSENTER_ESP_MSR \
200 | HM_CHANGED_GUEST_EFER_MSR \
201 | HM_CHANGED_GUEST_LAZY_MSRS \
202 | HM_CHANGED_GUEST_XCPT_INTERCEPTS \
203 | HM_CHANGED_VMX_GUEST_AUTO_MSRS \
204 | HM_CHANGED_VMX_GUEST_ACTIVITY_STATE \
205 | HM_CHANGED_VMX_GUEST_APIC_STATE \
206 | HM_CHANGED_VMX_ENTRY_CTLS \
207 | HM_CHANGED_VMX_EXIT_CTLS)
208
209#define HM_CHANGED_HOST_CONTEXT RT_BIT(24)
210
211/* Bits shared between host and guest. */
212#define HM_CHANGED_HOST_GUEST_SHARED_STATE ( HM_CHANGED_GUEST_CR0 \
213 | HM_CHANGED_GUEST_DEBUG \
214 | HM_CHANGED_GUEST_LAZY_MSRS)
215/** @} */
216
217/** Size for the EPT identity page table (1024 4 MB pages to cover the entire address space). */
218#define HM_EPT_IDENTITY_PG_TABLE_SIZE PAGE_SIZE
219/** Size of the TSS structure + 2 pages for the IO bitmap + end byte. */
220#define HM_VTX_TSS_SIZE (sizeof(VBOXTSS) + 2 * PAGE_SIZE + 1)
221/** Total guest mapped memory needed. */
222#define HM_VTX_TOTAL_DEVHEAP_MEM (HM_EPT_IDENTITY_PG_TABLE_SIZE + HM_VTX_TSS_SIZE)
223
224
225/** @name Macros for enabling and disabling preemption.
226 * These are really just for hiding the RTTHREADPREEMPTSTATE and asserting that
227 * preemption has already been disabled when there is no context hook.
228 * @{ */
229#ifdef VBOX_STRICT
230# define HM_DISABLE_PREEMPT() \
231 RTTHREADPREEMPTSTATE PreemptStateInternal = RTTHREADPREEMPTSTATE_INITIALIZER; \
232 Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD) || VMMR0ThreadCtxHookIsEnabled(pVCpu)); \
233 RTThreadPreemptDisable(&PreemptStateInternal)
234#else
235# define HM_DISABLE_PREEMPT() \
236 RTTHREADPREEMPTSTATE PreemptStateInternal = RTTHREADPREEMPTSTATE_INITIALIZER; \
237 RTThreadPreemptDisable(&PreemptStateInternal)
238#endif /* VBOX_STRICT */
239#define HM_RESTORE_PREEMPT() do { RTThreadPreemptRestore(&PreemptStateInternal); } while(0)
240/** @} */
241
242
243/** Enable for TPR guest patching. */
244#define VBOX_HM_WITH_GUEST_PATCHING
245
246/** @name HM saved state versions
247 * @{
248 */
249#ifdef VBOX_HM_WITH_GUEST_PATCHING
250# define HM_SAVED_STATE_VERSION 5
251# define HM_SAVED_STATE_VERSION_NO_PATCHING 4
252#else
253# define HM_SAVED_STATE_VERSION 4
254# define HM_SAVED_STATE_VERSION_NO_PATCHING 4
255#endif
256#define HM_SAVED_STATE_VERSION_2_0_X 3
257/** @} */
258
259/**
260 * Global per-cpu information. (host)
261 */
262typedef struct HMGLOBALCPUINFO
263{
264 /** The CPU ID. */
265 RTCPUID idCpu;
266 /** The VM_HSAVE_AREA (AMD-V) / VMXON region (Intel) memory backing. */
267 RTR0MEMOBJ hMemObj;
268 /** The physical address of the first page in hMemObj (it's a
269 * physcially contigous allocation if it spans multiple pages). */
270 RTHCPHYS HCPhysMemObj;
271 /** The address of the memory (for pfnEnable). */
272 void *pvMemObj;
273 /** Current ASID (AMD-V) / VPID (Intel). */
274 uint32_t uCurrentAsid;
275 /** TLB flush count. */
276 uint32_t cTlbFlushes;
277 /** Whether to flush each new ASID/VPID before use. */
278 bool fFlushAsidBeforeUse;
279 /** Configured for VT-x or AMD-V. */
280 bool fConfigured;
281 /** Set if the VBOX_HWVIRTEX_IGNORE_SVM_IN_USE hack is active. */
282 bool fIgnoreAMDVInUseError;
283 /** In use by our code. (for power suspend) */
284 volatile bool fInUse;
285} HMGLOBALCPUINFO;
286/** Pointer to the per-cpu global information. */
287typedef HMGLOBALCPUINFO *PHMGLOBALCPUINFO;
288
289typedef enum
290{
291 HMPENDINGIO_INVALID = 0,
292 HMPENDINGIO_PORT_READ,
293 HMPENDINGIO_PORT_WRITE,
294 HMPENDINGIO_STRING_READ,
295 HMPENDINGIO_STRING_WRITE,
296 /** The usual 32-bit paranoia. */
297 HMPENDINGIO_32BIT_HACK = 0x7fffffff
298} HMPENDINGIO;
299
300
301typedef enum
302{
303 HMTPRINSTR_INVALID,
304 HMTPRINSTR_READ,
305 HMTPRINSTR_READ_SHR4,
306 HMTPRINSTR_WRITE_REG,
307 HMTPRINSTR_WRITE_IMM,
308 HMTPRINSTR_JUMP_REPLACEMENT,
309 /** The usual 32-bit paranoia. */
310 HMTPRINSTR_32BIT_HACK = 0x7fffffff
311} HMTPRINSTR;
312
313typedef struct
314{
315 /** The key is the address of patched instruction. (32 bits GC ptr) */
316 AVLOU32NODECORE Core;
317 /** Original opcode. */
318 uint8_t aOpcode[16];
319 /** Instruction size. */
320 uint32_t cbOp;
321 /** Replacement opcode. */
322 uint8_t aNewOpcode[16];
323 /** Replacement instruction size. */
324 uint32_t cbNewOp;
325 /** Instruction type. */
326 HMTPRINSTR enmType;
327 /** Source operand. */
328 uint32_t uSrcOperand;
329 /** Destination operand. */
330 uint32_t uDstOperand;
331 /** Number of times the instruction caused a fault. */
332 uint32_t cFaults;
333 /** Patch address of the jump replacement. */
334 RTGCPTR32 pJumpTarget;
335} HMTPRPATCH;
336/** Pointer to HMTPRPATCH. */
337typedef HMTPRPATCH *PHMTPRPATCH;
338
339/**
340 * Switcher function, HC to the special 64-bit RC.
341 *
342 * @param pVM The cross context VM structure.
343 * @param offCpumVCpu Offset from pVM->cpum to pVM->aCpus[idCpu].cpum.
344 * @returns Return code indicating the action to take.
345 */
346typedef DECLCALLBACK(int) FNHMSWITCHERHC(PVM pVM, uint32_t offCpumVCpu);
347/** Pointer to switcher function. */
348typedef FNHMSWITCHERHC *PFNHMSWITCHERHC;
349
350/**
351 * HM VM Instance data.
352 * Changes to this must checked against the padding of the hm union in VM!
353 */
354typedef struct HM
355{
356 /** Set when we've initialized VMX or SVM. */
357 bool fInitialized;
358 /** Set if nested paging is enabled. */
359 bool fNestedPaging;
360 /** Set if nested paging is allowed. */
361 bool fAllowNestedPaging;
362 /** Set if large pages are enabled (requires nested paging). */
363 bool fLargePages;
364 /** Set if we can support 64-bit guests or not. */
365 bool fAllow64BitGuests;
366 /** Set if an IO-APIC is configured for this VM. */
367 bool fHasIoApic;
368 /** Set when TPR patching is allowed. */
369 bool fTprPatchingAllowed;
370 /** Set when we initialize VT-x or AMD-V once for all CPUs. */
371 bool fGlobalInit;
372 /** Set when TPR patching is active. */
373 bool fTPRPatchingActive;
374 /** Set when the debug facility has breakpoints/events enabled that requires
375 * us to use the debug execution loop in ring-0. */
376 bool fUseDebugLoop;
377 bool u8Alignment[2];
378
379 /** Host kernel flags that HM might need to know (SUPKERNELFEATURES_XXX). */
380 uint32_t fHostKernelFeatures;
381
382 /** Maximum ASID allowed. */
383 uint32_t uMaxAsid;
384 /** The maximum number of resumes loops allowed in ring-0 (safety precaution).
385 * This number is set much higher when RTThreadPreemptIsPending is reliable. */
386 uint32_t cMaxResumeLoops;
387
388 /** Guest allocated memory for patching purposes. */
389 RTGCPTR pGuestPatchMem;
390 /** Current free pointer inside the patch block. */
391 RTGCPTR pFreeGuestPatchMem;
392 /** Size of the guest patch memory block. */
393 uint32_t cbGuestPatchMem;
394 uint32_t u32Alignment0;
395
396#if HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS)
397 /** 32 to 64 bits switcher entrypoint. */
398 R0PTRTYPE(PFNHMSWITCHERHC) pfnHost32ToGuest64R0;
399 RTR0PTR pvR0Alignment0;
400#endif
401
402 struct
403 {
404 /** Set by the ring-0 side of HM to indicate VMX is supported by the
405 * CPU. */
406 bool fSupported;
407 /** Set when we've enabled VMX. */
408 bool fEnabled;
409 /** Set if VPID is supported. */
410 bool fVpid;
411 /** Set if VT-x VPID is allowed. */
412 bool fAllowVpid;
413 /** Set if unrestricted guest execution is in use (real and protected mode without paging). */
414 bool fUnrestrictedGuest;
415 /** Set if unrestricted guest execution is allowed to be used. */
416 bool fAllowUnrestricted;
417 /** Whether we're using the preemption timer or not. */
418 bool fUsePreemptTimer;
419 /** The shift mask employed by the VMX-Preemption timer. */
420 uint8_t cPreemptTimerShift;
421
422 /** Virtual address of the TSS page used for real mode emulation. */
423 R3PTRTYPE(PVBOXTSS) pRealModeTSS;
424 /** Virtual address of the identity page table used for real mode and protected mode without paging emulation in EPT mode. */
425 R3PTRTYPE(PX86PD) pNonPagingModeEPTPageTable;
426
427 /** Physical address of the APIC-access page. */
428 RTHCPHYS HCPhysApicAccess;
429 /** R0 memory object for the APIC-access page. */
430 RTR0MEMOBJ hMemObjApicAccess;
431 /** Virtual address of the APIC-access page. */
432 R0PTRTYPE(uint8_t *) pbApicAccess;
433
434#ifdef VBOX_WITH_CRASHDUMP_MAGIC
435 RTHCPHYS HCPhysScratch;
436 RTR0MEMOBJ hMemObjScratch;
437 R0PTRTYPE(uint8_t *) pbScratch;
438#endif
439
440 /** Internal Id of which flush-handler to use for tagged-TLB entries. */
441 uint32_t uFlushTaggedTlb;
442
443 /** Pause-loop exiting (PLE) gap in ticks. */
444 uint32_t cPleGapTicks;
445 /** Pause-loop exiting (PLE) window in ticks. */
446 uint32_t cPleWindowTicks;
447 uint32_t u32Alignment0;
448
449 /** Host CR4 value (set by ring-0 VMX init) */
450 uint64_t u64HostCr4;
451 /** Host SMM monitor control (set by ring-0 VMX init) */
452 uint64_t u64HostSmmMonitorCtl;
453 /** Host EFER value (set by ring-0 VMX init) */
454 uint64_t u64HostEfer;
455 /** Whether the CPU supports VMCS fields for swapping EFER. */
456 bool fSupportsVmcsEfer;
457 uint8_t u8Alignment2[7];
458
459 /** VMX MSR values. */
460 VMXMSRS Msrs;
461
462 /** Flush types for invept & invvpid; they depend on capabilities. */
463 VMXFLUSHEPT enmFlushEpt;
464 VMXFLUSHVPID enmFlushVpid;
465
466 /** Host-physical address for a failing VMXON instruction. */
467 RTHCPHYS HCPhysVmxEnableError;
468 } vmx;
469
470 struct
471 {
472 /** Set by the ring-0 side of HM to indicate SVM is supported by the
473 * CPU. */
474 bool fSupported;
475 /** Set when we've enabled SVM. */
476 bool fEnabled;
477 /** Set if erratum 170 affects the AMD cpu. */
478 bool fAlwaysFlushTLB;
479 /** Set when the hack to ignore VERR_SVM_IN_USE is active. */
480 bool fIgnoreInUseError;
481 uint8_t u8Alignment0[4];
482
483 /** Physical address of the IO bitmap (12kb). */
484 RTHCPHYS HCPhysIOBitmap;
485 /** R0 memory object for the IO bitmap (12kb). */
486 RTR0MEMOBJ hMemObjIOBitmap;
487 /** Virtual address of the IO bitmap. */
488 R0PTRTYPE(void *) pvIOBitmap;
489
490 /* HWCR MSR (for diagnostics) */
491 uint64_t u64MsrHwcr;
492
493 /** SVM revision. */
494 uint32_t u32Rev;
495 /** SVM feature bits from cpuid 0x8000000a */
496 uint32_t u32Features;
497
498 /** Pause filter counter. */
499 uint16_t cPauseFilter;
500 /** Pause filter treshold in ticks. */
501 uint16_t cPauseFilterThresholdTicks;
502 uint32_t u32Alignment0;
503 } svm;
504
505 /**
506 * AVL tree with all patches (active or disabled) sorted by guest instruction
507 * address.
508 */
509 AVLOU32TREE PatchTree;
510 uint32_t cPatches;
511 HMTPRPATCH aPatches[64];
512
513 struct
514 {
515 uint32_t u32AMDFeatureECX;
516 uint32_t u32AMDFeatureEDX;
517 } cpuid;
518
519 /** Saved error from detection */
520 int32_t lLastError;
521
522 /** HMR0Init was run */
523 bool fHMR0Init;
524 bool u8Alignment1[3];
525
526 STAMCOUNTER StatTprPatchSuccess;
527 STAMCOUNTER StatTprPatchFailure;
528 STAMCOUNTER StatTprReplaceSuccessCr8;
529 STAMCOUNTER StatTprReplaceSuccessVmc;
530 STAMCOUNTER StatTprReplaceFailure;
531} HM;
532/** Pointer to HM VM instance data. */
533typedef HM *PHM;
534
535AssertCompileMemberAlignment(HM, StatTprPatchSuccess, 8);
536
537/* Maximum number of cached entries. */
538#define VMCSCACHE_MAX_ENTRY 128
539
540/**
541 * Structure for storing read and write VMCS actions.
542 */
543typedef struct VMCSCACHE
544{
545#ifdef VBOX_WITH_CRASHDUMP_MAGIC
546 /* Magic marker for searching in crash dumps. */
547 uint8_t aMagic[16];
548 uint64_t uMagic;
549 uint64_t u64TimeEntry;
550 uint64_t u64TimeSwitch;
551 uint64_t cResume;
552 uint64_t interPD;
553 uint64_t pSwitcher;
554 uint32_t uPos;
555 uint32_t idCpu;
556#endif
557 /* CR2 is saved here for EPT syncing. */
558 uint64_t cr2;
559 struct
560 {
561 uint32_t cValidEntries;
562 uint32_t uAlignment;
563 uint32_t aField[VMCSCACHE_MAX_ENTRY];
564 uint64_t aFieldVal[VMCSCACHE_MAX_ENTRY];
565 } Write;
566 struct
567 {
568 uint32_t cValidEntries;
569 uint32_t uAlignment;
570 uint32_t aField[VMCSCACHE_MAX_ENTRY];
571 uint64_t aFieldVal[VMCSCACHE_MAX_ENTRY];
572 } Read;
573#ifdef VBOX_STRICT
574 struct
575 {
576 RTHCPHYS HCPhysCpuPage;
577 RTHCPHYS HCPhysVmcs;
578 RTGCPTR pCache;
579 RTGCPTR pCtx;
580 } TestIn;
581 struct
582 {
583 RTHCPHYS HCPhysVmcs;
584 RTGCPTR pCache;
585 RTGCPTR pCtx;
586 uint64_t eflags;
587 uint64_t cr8;
588 } TestOut;
589 struct
590 {
591 uint64_t param1;
592 uint64_t param2;
593 uint64_t param3;
594 uint64_t param4;
595 } ScratchPad;
596#endif
597} VMCSCACHE;
598/** Pointer to VMCSCACHE. */
599typedef VMCSCACHE *PVMCSCACHE;
600AssertCompileSizeAlignment(VMCSCACHE, 8);
601
602/**
603 * VMX StartVM function.
604 *
605 * @returns VBox status code (no informational stuff).
606 * @param fResume Whether to use VMRESUME (true) or VMLAUNCH (false).
607 * @param pCtx The CPU register context.
608 * @param pCache The VMCS cache.
609 * @param pVM Pointer to the cross context VM structure.
610 * @param pVCpu Pointer to the cross context per-CPU structure.
611 */
612typedef DECLCALLBACK(int) FNHMVMXSTARTVM(RTHCUINT fResume, PCPUMCTX pCtx, PVMCSCACHE pCache, PVM pVM, PVMCPU pVCpu);
613/** Pointer to a VMX StartVM function. */
614typedef R0PTRTYPE(FNHMVMXSTARTVM *) PFNHMVMXSTARTVM;
615
616/** SVM VMRun function. */
617typedef DECLCALLBACK(int) FNHMSVMVMRUN(RTHCPHYS pVmcbHostPhys, RTHCPHYS pVmcbPhys, PCPUMCTX pCtx, PVM pVM, PVMCPU pVCpu);
618/** Pointer to a SVM VMRun function. */
619typedef R0PTRTYPE(FNHMSVMVMRUN *) PFNHMSVMVMRUN;
620
621/**
622 * HM VMCPU Instance data.
623 *
624 * Note! If you change members of this struct, make sure to check if the
625 * assembly counterpart in HMInternal.mac needs to be updated as well.
626 */
627typedef struct HMCPU
628{
629 /** Set if we need to flush the TLB during the world switch. */
630 bool fForceTLBFlush;
631 /** Set when we're using VT-x or AMD-V at that moment. */
632 bool fActive;
633 /** Set when the TLB has been checked until we return from the world switch. */
634 volatile bool fCheckedTLBFlush;
635 /** Whether we've completed the inner HM leave function. */
636 bool fLeaveDone;
637 /** Whether we're using the hyper DR7 or guest DR7. */
638 bool fUsingHyperDR7;
639 /** Whether to preload the guest-FPU state to avoid \#NM VM-exit overhead. */
640 bool fPreloadGuestFpu;
641 /** Set if XCR0 needs to be loaded and saved when entering and exiting guest
642 * code execution. */
643 bool fLoadSaveGuestXcr0;
644
645 /** Whether we should use the debug loop because of single stepping or special
646 * debug breakpoints / events are armed. */
647 bool fUseDebugLoop;
648 /** Whether we are currently executing in the debug loop.
649 * Mainly for assertions. */
650 bool fUsingDebugLoop;
651 /** Set if we using the debug loop and wish to intercept RDTSC. */
652 bool fDebugWantRdTscExit;
653 /** Whether we're executing a single instruction. */
654 bool fSingleInstruction;
655 /** Set if we need to clear the trap flag because of single stepping. */
656 bool fClearTrapFlag;
657
658 /** Whether \#UD needs to be intercepted (required by certain GIM providers). */
659 bool fGIMTrapXcptUD;
660 /** Whether paravirt. hypercalls are enabled. */
661 bool fHypercallsEnabled;
662 uint8_t u8Alignment0[2];
663
664 /** World switch exit counter. */
665 volatile uint32_t cWorldSwitchExits;
666 /** HM_CHANGED_* flags. */
667 volatile uint32_t fContextUseFlags;
668 /** Id of the last cpu we were executing code on (NIL_RTCPUID for the first
669 * time). */
670 RTCPUID idLastCpu;
671 /** TLB flush count. */
672 uint32_t cTlbFlushes;
673 /** Current ASID in use by the VM. */
674 uint32_t uCurrentAsid;
675 /** An additional error code used for some gurus. */
676 uint32_t u32HMError;
677 /** Host's TSC_AUX MSR (used when RDTSCP doesn't cause VM-exits). */
678 uint64_t u64HostTscAux;
679
680 struct
681 {
682 /** Ring 0 handlers for VT-x. */
683 PFNHMVMXSTARTVM pfnStartVM;
684#if HC_ARCH_BITS == 32
685 uint32_t u32Alignment0;
686#endif
687 /** Current VMX_VMCS32_CTRL_PIN_EXEC. */
688 uint32_t u32PinCtls;
689 /** Current VMX_VMCS32_CTRL_PROC_EXEC. */
690 uint32_t u32ProcCtls;
691 /** Current VMX_VMCS32_CTRL_PROC_EXEC2. */
692 uint32_t u32ProcCtls2;
693 /** Current VMX_VMCS32_CTRL_EXIT. */
694 uint32_t u32ExitCtls;
695 /** Current VMX_VMCS32_CTRL_ENTRY. */
696 uint32_t u32EntryCtls;
697
698 /** Current CR0 mask. */
699 uint32_t u32CR0Mask;
700 /** Current CR4 mask. */
701 uint32_t u32CR4Mask;
702 /** Current exception bitmap. */
703 uint32_t u32XcptBitmap;
704 /** The updated-guest-state mask. */
705 volatile uint32_t fUpdatedGuestState;
706 uint32_t u32Alignment1;
707
708 /** Physical address of the VM control structure (VMCS). */
709 RTHCPHYS HCPhysVmcs;
710 /** R0 memory object for the VM control structure (VMCS). */
711 RTR0MEMOBJ hMemObjVmcs;
712 /** Virtual address of the VM control structure (VMCS). */
713 R0PTRTYPE(void *) pvVmcs;
714
715 /** Physical address of the virtual APIC page for TPR caching. */
716 RTHCPHYS HCPhysVirtApic;
717 /** R0 memory object for the virtual APIC page for TPR caching. */
718 RTR0MEMOBJ hMemObjVirtApic;
719 /** Virtual address of the virtual APIC page for TPR caching. */
720 R0PTRTYPE(uint8_t *) pbVirtApic;
721
722 /** Physical address of the MSR bitmap. */
723 RTHCPHYS HCPhysMsrBitmap;
724 /** R0 memory object for the MSR bitmap. */
725 RTR0MEMOBJ hMemObjMsrBitmap;
726 /** Virtual address of the MSR bitmap. */
727 R0PTRTYPE(void *) pvMsrBitmap;
728
729 /** Physical address of the VM-entry MSR-load and VM-exit MSR-store area (used
730 * for guest MSRs). */
731 RTHCPHYS HCPhysGuestMsr;
732 /** R0 memory object of the VM-entry MSR-load and VM-exit MSR-store area
733 * (used for guest MSRs). */
734 RTR0MEMOBJ hMemObjGuestMsr;
735 /** Virtual address of the VM-entry MSR-load and VM-exit MSR-store area (used
736 * for guest MSRs). */
737 R0PTRTYPE(void *) pvGuestMsr;
738
739 /** Physical address of the VM-exit MSR-load area (used for host MSRs). */
740 RTHCPHYS HCPhysHostMsr;
741 /** R0 memory object for the VM-exit MSR-load area (used for host MSRs). */
742 RTR0MEMOBJ hMemObjHostMsr;
743 /** Virtual address of the VM-exit MSR-load area (used for host MSRs). */
744 R0PTRTYPE(void *) pvHostMsr;
745
746 /** Current EPTP. */
747 RTHCPHYS HCPhysEPTP;
748
749 /** Number of guest/host MSR pairs in the auto-load/store area. */
750 uint32_t cMsrs;
751 /** Whether the host MSR values are up-to-date in the auto-load/store area. */
752 bool fUpdatedHostMsrs;
753 uint8_t u8Alignment0[3];
754
755 /** Host LSTAR MSR value to restore lazily while leaving VT-x. */
756 uint64_t u64HostLStarMsr;
757 /** Host STAR MSR value to restore lazily while leaving VT-x. */
758 uint64_t u64HostStarMsr;
759 /** Host SF_MASK MSR value to restore lazily while leaving VT-x. */
760 uint64_t u64HostSFMaskMsr;
761 /** Host KernelGS-Base MSR value to restore lazily while leaving VT-x. */
762 uint64_t u64HostKernelGSBaseMsr;
763 /** A mask of which MSRs have been swapped and need restoration. */
764 uint32_t fLazyMsrs;
765 uint32_t u32Alignment2;
766
767 /** The cached APIC-base MSR used for identifying when to map the HC physical APIC-access page. */
768 uint64_t u64MsrApicBase;
769 /** Last use TSC offset value. (cached) */
770 uint64_t u64TSCOffset;
771
772 /** VMCS cache. */
773 VMCSCACHE VMCSCache;
774
775 /** Real-mode emulation state. */
776 struct
777 {
778 X86DESCATTR AttrCS;
779 X86DESCATTR AttrDS;
780 X86DESCATTR AttrES;
781 X86DESCATTR AttrFS;
782 X86DESCATTR AttrGS;
783 X86DESCATTR AttrSS;
784 X86EFLAGS Eflags;
785 uint32_t fRealOnV86Active;
786 } RealMode;
787
788 /** VT-x error-reporting (mainly for ring-3 propagation). */
789 struct
790 {
791 uint64_t u64VMCSPhys;
792 uint32_t u32VMCSRevision;
793 uint32_t u32InstrError;
794 uint32_t u32ExitReason;
795 RTCPUID idEnteredCpu;
796 RTCPUID idCurrentCpu;
797 uint32_t u32Alignment0;
798 } LastError;
799
800 /** Current state of the VMCS. */
801 uint32_t uVmcsState;
802 /** Which host-state bits to restore before being preempted. */
803 uint32_t fRestoreHostFlags;
804 /** The host-state restoration structure. */
805 VMXRESTOREHOST RestoreHost;
806
807 /** Set if guest was executing in real mode (extra checks). */
808 bool fWasInRealMode;
809 uint8_t u8Alignment1[7];
810 } vmx;
811
812 struct
813 {
814 /** Ring 0 handlers for VT-x. */
815 PFNHMSVMVMRUN pfnVMRun;
816#if HC_ARCH_BITS == 32
817 uint32_t u32Alignment0;
818#endif
819
820 /** Physical address of the host VMCB which holds additional host-state. */
821 RTHCPHYS HCPhysVmcbHost;
822 /** R0 memory object for the host VMCB which holds additional host-state. */
823 RTR0MEMOBJ hMemObjVmcbHost;
824 /** Virtual address of the host VMCB which holds additional host-state. */
825 R0PTRTYPE(void *) pvVmcbHost;
826
827 /** Physical address of the guest VMCB. */
828 RTHCPHYS HCPhysVmcb;
829 /** R0 memory object for the guest VMCB. */
830 RTR0MEMOBJ hMemObjVmcb;
831 /** Virtual address of the guest VMCB. */
832 R0PTRTYPE(void *) pvVmcb;
833
834 /** Physical address of the MSR bitmap (8 KB). */
835 RTHCPHYS HCPhysMsrBitmap;
836 /** R0 memory object for the MSR bitmap (8 KB). */
837 RTR0MEMOBJ hMemObjMsrBitmap;
838 /** Virtual address of the MSR bitmap. */
839 R0PTRTYPE(void *) pvMsrBitmap;
840
841 /** Whether VTPR with V_INTR_MASKING set is in effect, indicating
842 * we should check if the VTPR changed on every VM-exit. */
843 bool fSyncVTpr;
844 uint8_t u8Alignment0[7];
845 } svm;
846
847 /** Event injection state. */
848 struct
849 {
850 uint32_t fPending;
851 uint32_t u32ErrCode;
852 uint32_t cbInstr;
853 uint32_t u32Padding; /**< Explicit alignment padding. */
854 uint64_t u64IntInfo;
855 RTGCUINTPTR GCPtrFaultAddress;
856 } Event;
857
858 /** IO Block emulation state. */
859 struct
860 {
861 bool fEnabled;
862 uint8_t u8Align[7];
863
864 /** RIP at the start of the io code we wish to emulate in the recompiler. */
865 RTGCPTR GCPtrFunctionEip;
866
867 uint64_t cr0;
868 } EmulateIoBlock;
869
870 struct
871 {
872 /** Pending IO operation type. */
873 HMPENDINGIO enmType;
874 uint32_t u32Alignment0;
875 RTGCPTR GCPtrRip;
876 RTGCPTR GCPtrRipNext;
877 union
878 {
879 struct
880 {
881 uint32_t uPort;
882 uint32_t uAndVal;
883 uint32_t cbSize;
884 } Port;
885 uint64_t aRaw[2];
886 } s;
887 } PendingIO;
888
889 /** The PAE PDPEs used with Nested Paging (only valid when
890 * VMCPU_FF_HM_UPDATE_PAE_PDPES is set). */
891 X86PDPE aPdpes[4];
892
893 /** Current shadow paging mode. */
894 PGMMODE enmShadowMode;
895
896 /** The CPU ID of the CPU currently owning the VMCS. Set in
897 * HMR0Enter and cleared in HMR0Leave. */
898 RTCPUID idEnteredCpu;
899
900 /** VT-x/AMD-V VM-exit/\#VMXEXIT history, circular array. */
901 uint16_t auExitHistory[31];
902 /** The index of the next free slot in the history array. */
903 uint16_t idxExitHistoryFree;
904
905 /** For saving stack space, the disassembler state is allocated here instead of
906 * on the stack. */
907 DISCPUSTATE DisState;
908
909 STAMPROFILEADV StatEntry;
910 STAMPROFILEADV StatExit1;
911 STAMPROFILEADV StatExit2;
912 STAMPROFILEADV StatExitIO;
913 STAMPROFILEADV StatExitMovCRx;
914 STAMPROFILEADV StatExitXcptNmi;
915 STAMPROFILEADV StatLoadGuestState;
916 STAMPROFILEADV StatInGC;
917
918#if HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS)
919 STAMPROFILEADV StatWorldSwitch3264;
920#endif
921 STAMPROFILEADV StatPoke;
922 STAMPROFILEADV StatSpinPoke;
923 STAMPROFILEADV StatSpinPokeFailed;
924
925 STAMCOUNTER StatInjectInterrupt;
926 STAMCOUNTER StatInjectXcpt;
927 STAMCOUNTER StatInjectPendingReflect;
928
929 STAMCOUNTER StatExitAll;
930 STAMCOUNTER StatExitShadowNM;
931 STAMCOUNTER StatExitGuestNM;
932 STAMCOUNTER StatExitShadowPF; /**< Misleading, currently used for MMIO \#PFs as well. */
933 STAMCOUNTER StatExitShadowPFEM;
934 STAMCOUNTER StatExitGuestPF;
935 STAMCOUNTER StatExitGuestUD;
936 STAMCOUNTER StatExitGuestSS;
937 STAMCOUNTER StatExitGuestNP;
938 STAMCOUNTER StatExitGuestTS;
939 STAMCOUNTER StatExitGuestGP;
940 STAMCOUNTER StatExitGuestDE;
941 STAMCOUNTER StatExitGuestDB;
942 STAMCOUNTER StatExitGuestMF;
943 STAMCOUNTER StatExitGuestBP;
944 STAMCOUNTER StatExitGuestXF;
945 STAMCOUNTER StatExitGuestXcpUnk;
946 STAMCOUNTER StatExitInvlpg;
947 STAMCOUNTER StatExitInvd;
948 STAMCOUNTER StatExitWbinvd;
949 STAMCOUNTER StatExitPause;
950 STAMCOUNTER StatExitCpuid;
951 STAMCOUNTER StatExitRdtsc;
952 STAMCOUNTER StatExitRdtscp;
953 STAMCOUNTER StatExitRdpmc;
954 STAMCOUNTER StatExitVmcall;
955 STAMCOUNTER StatExitRdrand;
956 STAMCOUNTER StatExitCli;
957 STAMCOUNTER StatExitSti;
958 STAMCOUNTER StatExitPushf;
959 STAMCOUNTER StatExitPopf;
960 STAMCOUNTER StatExitIret;
961 STAMCOUNTER StatExitInt;
962 STAMCOUNTER StatExitCRxWrite[16];
963 STAMCOUNTER StatExitCRxRead[16];
964 STAMCOUNTER StatExitDRxWrite;
965 STAMCOUNTER StatExitDRxRead;
966 STAMCOUNTER StatExitRdmsr;
967 STAMCOUNTER StatExitWrmsr;
968 STAMCOUNTER StatExitClts;
969 STAMCOUNTER StatExitXdtrAccess;
970 STAMCOUNTER StatExitHlt;
971 STAMCOUNTER StatExitMwait;
972 STAMCOUNTER StatExitMonitor;
973 STAMCOUNTER StatExitLmsw;
974 STAMCOUNTER StatExitIOWrite;
975 STAMCOUNTER StatExitIORead;
976 STAMCOUNTER StatExitIOStringWrite;
977 STAMCOUNTER StatExitIOStringRead;
978 STAMCOUNTER StatExitIntWindow;
979 STAMCOUNTER StatExitExtInt;
980 STAMCOUNTER StatExitHostNmiInGC;
981 STAMCOUNTER StatExitPreemptTimer;
982 STAMCOUNTER StatExitTprBelowThreshold;
983 STAMCOUNTER StatExitTaskSwitch;
984 STAMCOUNTER StatExitMtf;
985 STAMCOUNTER StatExitApicAccess;
986 STAMCOUNTER StatPendingHostIrq;
987
988 STAMCOUNTER StatFlushPage;
989 STAMCOUNTER StatFlushPageManual;
990 STAMCOUNTER StatFlushPhysPageManual;
991 STAMCOUNTER StatFlushTlb;
992 STAMCOUNTER StatFlushTlbManual;
993 STAMCOUNTER StatFlushTlbWorldSwitch;
994 STAMCOUNTER StatNoFlushTlbWorldSwitch;
995 STAMCOUNTER StatFlushEntire;
996 STAMCOUNTER StatFlushAsid;
997 STAMCOUNTER StatFlushNestedPaging;
998 STAMCOUNTER StatFlushTlbInvlpgVirt;
999 STAMCOUNTER StatFlushTlbInvlpgPhys;
1000 STAMCOUNTER StatTlbShootdown;
1001 STAMCOUNTER StatTlbShootdownFlush;
1002
1003 STAMCOUNTER StatSwitchGuestIrq;
1004 STAMCOUNTER StatSwitchHmToR3FF;
1005 STAMCOUNTER StatSwitchExitToR3;
1006 STAMCOUNTER StatSwitchLongJmpToR3;
1007 STAMCOUNTER StatSwitchMaxResumeLoops;
1008 STAMCOUNTER StatSwitchHltToR3;
1009 STAMCOUNTER StatSwitchApicAccessToR3;
1010 STAMCOUNTER StatSwitchPreempt;
1011 STAMCOUNTER StatSwitchPreemptSaveHostState;
1012
1013 STAMCOUNTER StatTscParavirt;
1014 STAMCOUNTER StatTscOffset;
1015 STAMCOUNTER StatTscIntercept;
1016
1017 STAMCOUNTER StatExitReasonNpf;
1018 STAMCOUNTER StatDRxArmed;
1019 STAMCOUNTER StatDRxContextSwitch;
1020 STAMCOUNTER StatDRxIoCheck;
1021
1022 STAMCOUNTER StatLoadMinimal;
1023 STAMCOUNTER StatLoadFull;
1024
1025 STAMCOUNTER StatVmxCheckBadRmSelBase;
1026 STAMCOUNTER StatVmxCheckBadRmSelLimit;
1027 STAMCOUNTER StatVmxCheckRmOk;
1028
1029 STAMCOUNTER StatVmxCheckBadSel;
1030 STAMCOUNTER StatVmxCheckBadRpl;
1031 STAMCOUNTER StatVmxCheckBadLdt;
1032 STAMCOUNTER StatVmxCheckBadTr;
1033 STAMCOUNTER StatVmxCheckPmOk;
1034
1035#if HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS)
1036 STAMCOUNTER StatFpu64SwitchBack;
1037 STAMCOUNTER StatDebug64SwitchBack;
1038#endif
1039
1040#ifdef VBOX_WITH_STATISTICS
1041 R3PTRTYPE(PSTAMCOUNTER) paStatExitReason;
1042 R0PTRTYPE(PSTAMCOUNTER) paStatExitReasonR0;
1043 R3PTRTYPE(PSTAMCOUNTER) paStatInjectedIrqs;
1044 R0PTRTYPE(PSTAMCOUNTER) paStatInjectedIrqsR0;
1045#endif
1046#ifdef HM_PROFILE_EXIT_DISPATCH
1047 STAMPROFILEADV StatExitDispatch;
1048#endif
1049} HMCPU;
1050/** Pointer to HM VMCPU instance data. */
1051typedef HMCPU *PHMCPU;
1052AssertCompileMemberAlignment(HMCPU, vmx, 8);
1053AssertCompileMemberAlignment(HMCPU, svm, 8);
1054AssertCompileMemberAlignment(HMCPU, Event, 8);
1055
1056
1057#ifdef IN_RING0
1058/** @todo r=bird: s/[[:space:]]HM/ hm/ - internal functions starts with a
1059 * lower cased prefix. HMInternal.h is an internal header, so
1060 * everything here must be internal. */
1061VMMR0DECL(PHMGLOBALCPUINFO) HMR0GetCurrentCpu(void);
1062VMMR0DECL(PHMGLOBALCPUINFO) HMR0GetCurrentCpuEx(RTCPUID idCpu);
1063
1064
1065# ifdef VBOX_STRICT
1066VMMR0DECL(void) HMDumpRegs(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx);
1067VMMR0DECL(void) HMR0DumpDescriptor(PCX86DESCHC pDesc, RTSEL Sel, const char *pszMsg);
1068# else
1069# define HMDumpRegs(a, b ,c) do { } while (0)
1070# define HMR0DumpDescriptor(a, b, c) do { } while (0)
1071# endif /* VBOX_STRICT */
1072
1073# ifdef VBOX_WITH_KERNEL_USING_XMM
1074DECLASM(int) HMR0VMXStartVMWrapXMM(RTHCUINT fResume, PCPUMCTX pCtx, PVMCSCACHE pCache, PVM pVM, PVMCPU pVCpu, PFNHMVMXSTARTVM pfnStartVM);
1075DECLASM(int) HMR0SVMRunWrapXMM(RTHCPHYS pVmcbHostPhys, RTHCPHYS pVmcbPhys, PCPUMCTX pCtx, PVM pVM, PVMCPU pVCpu, PFNHMSVMVMRUN pfnVMRun);
1076# endif
1077
1078#endif /* IN_RING0 */
1079
1080/** @} */
1081
1082RT_C_DECLS_END
1083
1084#endif
1085
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