VirtualBox

source: vbox/trunk/src/VBox/VMM/include/HMInternal.h@ 78650

Last change on this file since 78650 was 78632, checked in by vboxsync, 6 years ago

Forward ported 130474,130475,130477,130479. bugref:9453
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1/* $Id: HMInternal.h 78632 2019-05-21 13:56:11Z vboxsync $ */
2/** @file
3 * HM - Internal header file.
4 */
5
6/*
7 * Copyright (C) 2006-2019 Oracle Corporation
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 */
17
18#ifndef VMM_INCLUDED_SRC_include_HMInternal_h
19#define VMM_INCLUDED_SRC_include_HMInternal_h
20#ifndef RT_WITHOUT_PRAGMA_ONCE
21# pragma once
22#endif
23
24#include <VBox/cdefs.h>
25#include <VBox/types.h>
26#include <VBox/vmm/stam.h>
27#include <VBox/dis.h>
28#include <VBox/vmm/hm.h>
29#include <VBox/vmm/hm_vmx.h>
30#include <VBox/vmm/hm_svm.h>
31#include <VBox/vmm/pgm.h>
32#include <VBox/vmm/cpum.h>
33#include <VBox/vmm/trpm.h>
34#include <iprt/memobj.h>
35#include <iprt/cpuset.h>
36#include <iprt/mp.h>
37#include <iprt/avl.h>
38#include <iprt/string.h>
39
40#if HC_ARCH_BITS == 32 && defined(RT_OS_DARWIN)
41# error "32-bit darwin is no longer supported. Go back to 4.3 or earlier!"
42#endif
43
44#if HC_ARCH_BITS == 64 || defined(VBOX_WITH_64_BITS_GUESTS)
45/* Enable 64 bits guest support. */
46# define VBOX_ENABLE_64_BITS_GUESTS
47#endif
48
49#if HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS)
50# define VMX_USE_CACHED_VMCS_ACCESSES
51#endif
52
53/** @def HM_PROFILE_EXIT_DISPATCH
54 * Enables profiling of the VM exit handler dispatching. */
55#if 0 || defined(DOXYGEN_RUNNING)
56# define HM_PROFILE_EXIT_DISPATCH
57#endif
58
59RT_C_DECLS_BEGIN
60
61
62/** @defgroup grp_hm_int Internal
63 * @ingroup grp_hm
64 * @internal
65 * @{
66 */
67
68/** @name HM_CHANGED_XXX
69 * HM CPU-context changed flags.
70 *
71 * These flags are used to keep track of which registers and state has been
72 * modified since they were imported back into the guest-CPU context.
73 *
74 * @{
75 */
76#define HM_CHANGED_HOST_CONTEXT UINT64_C(0x0000000000000001)
77#define HM_CHANGED_GUEST_RIP UINT64_C(0x0000000000000004)
78#define HM_CHANGED_GUEST_RFLAGS UINT64_C(0x0000000000000008)
79
80#define HM_CHANGED_GUEST_RAX UINT64_C(0x0000000000000010)
81#define HM_CHANGED_GUEST_RCX UINT64_C(0x0000000000000020)
82#define HM_CHANGED_GUEST_RDX UINT64_C(0x0000000000000040)
83#define HM_CHANGED_GUEST_RBX UINT64_C(0x0000000000000080)
84#define HM_CHANGED_GUEST_RSP UINT64_C(0x0000000000000100)
85#define HM_CHANGED_GUEST_RBP UINT64_C(0x0000000000000200)
86#define HM_CHANGED_GUEST_RSI UINT64_C(0x0000000000000400)
87#define HM_CHANGED_GUEST_RDI UINT64_C(0x0000000000000800)
88#define HM_CHANGED_GUEST_R8_R15 UINT64_C(0x0000000000001000)
89#define HM_CHANGED_GUEST_GPRS_MASK UINT64_C(0x0000000000001ff0)
90
91#define HM_CHANGED_GUEST_ES UINT64_C(0x0000000000002000)
92#define HM_CHANGED_GUEST_CS UINT64_C(0x0000000000004000)
93#define HM_CHANGED_GUEST_SS UINT64_C(0x0000000000008000)
94#define HM_CHANGED_GUEST_DS UINT64_C(0x0000000000010000)
95#define HM_CHANGED_GUEST_FS UINT64_C(0x0000000000020000)
96#define HM_CHANGED_GUEST_GS UINT64_C(0x0000000000040000)
97#define HM_CHANGED_GUEST_SREG_MASK UINT64_C(0x000000000007e000)
98
99#define HM_CHANGED_GUEST_GDTR UINT64_C(0x0000000000080000)
100#define HM_CHANGED_GUEST_IDTR UINT64_C(0x0000000000100000)
101#define HM_CHANGED_GUEST_LDTR UINT64_C(0x0000000000200000)
102#define HM_CHANGED_GUEST_TR UINT64_C(0x0000000000400000)
103#define HM_CHANGED_GUEST_TABLE_MASK UINT64_C(0x0000000000780000)
104
105#define HM_CHANGED_GUEST_CR0 UINT64_C(0x0000000000800000)
106#define HM_CHANGED_GUEST_CR2 UINT64_C(0x0000000001000000)
107#define HM_CHANGED_GUEST_CR3 UINT64_C(0x0000000002000000)
108#define HM_CHANGED_GUEST_CR4 UINT64_C(0x0000000004000000)
109#define HM_CHANGED_GUEST_CR_MASK UINT64_C(0x0000000007800000)
110
111#define HM_CHANGED_GUEST_APIC_TPR UINT64_C(0x0000000008000000)
112#define HM_CHANGED_GUEST_EFER_MSR UINT64_C(0x0000000010000000)
113
114#define HM_CHANGED_GUEST_DR0_DR3 UINT64_C(0x0000000020000000)
115#define HM_CHANGED_GUEST_DR6 UINT64_C(0x0000000040000000)
116#define HM_CHANGED_GUEST_DR7 UINT64_C(0x0000000080000000)
117#define HM_CHANGED_GUEST_DR_MASK UINT64_C(0x00000000e0000000)
118
119#define HM_CHANGED_GUEST_X87 UINT64_C(0x0000000100000000)
120#define HM_CHANGED_GUEST_SSE_AVX UINT64_C(0x0000000200000000)
121#define HM_CHANGED_GUEST_OTHER_XSAVE UINT64_C(0x0000000400000000)
122#define HM_CHANGED_GUEST_XCRx UINT64_C(0x0000000800000000)
123
124#define HM_CHANGED_GUEST_KERNEL_GS_BASE UINT64_C(0x0000001000000000)
125#define HM_CHANGED_GUEST_SYSCALL_MSRS UINT64_C(0x0000002000000000)
126#define HM_CHANGED_GUEST_SYSENTER_CS_MSR UINT64_C(0x0000004000000000)
127#define HM_CHANGED_GUEST_SYSENTER_EIP_MSR UINT64_C(0x0000008000000000)
128#define HM_CHANGED_GUEST_SYSENTER_ESP_MSR UINT64_C(0x0000010000000000)
129#define HM_CHANGED_GUEST_SYSENTER_MSR_MASK UINT64_C(0x000001c000000000)
130#define HM_CHANGED_GUEST_TSC_AUX UINT64_C(0x0000020000000000)
131#define HM_CHANGED_GUEST_OTHER_MSRS UINT64_C(0x0000040000000000)
132#define HM_CHANGED_GUEST_ALL_MSRS ( HM_CHANGED_GUEST_EFER \
133 | HM_CHANGED_GUEST_KERNEL_GS_BASE \
134 | HM_CHANGED_GUEST_SYSCALL_MSRS \
135 | HM_CHANGED_GUEST_SYSENTER_MSR_MASK \
136 | HM_CHANGED_GUEST_TSC_AUX \
137 | HM_CHANGED_GUEST_OTHER_MSRS)
138
139#define HM_CHANGED_GUEST_HWVIRT UINT64_C(0x0000080000000000)
140#define HM_CHANGED_GUEST_MASK UINT64_C(0x00000ffffffffffc)
141
142#define HM_CHANGED_KEEPER_STATE_MASK UINT64_C(0xffff000000000000)
143
144/** @todo r=ramshankar: Remove "GUEST" from XCPT_INTERCEPTS. */
145#define HM_CHANGED_VMX_GUEST_XCPT_INTERCEPTS UINT64_C(0x0001000000000000)
146#define HM_CHANGED_VMX_GUEST_AUTO_MSRS UINT64_C(0x0002000000000000)
147#define HM_CHANGED_VMX_GUEST_LAZY_MSRS UINT64_C(0x0004000000000000)
148#define HM_CHANGED_VMX_ENTRY_EXIT_CTLS UINT64_C(0x0008000000000000)
149#define HM_CHANGED_VMX_MASK UINT64_C(0x000f000000000000)
150#define HM_CHANGED_VMX_HOST_GUEST_SHARED_STATE ( HM_CHANGED_GUEST_DR_MASK \
151 | HM_CHANGED_VMX_GUEST_LAZY_MSRS)
152
153/** @todo r=ramshankar: Remove "GUEST" from XCPT_INTERCEPTS. */
154#define HM_CHANGED_SVM_GUEST_XCPT_INTERCEPTS UINT64_C(0x0001000000000000)
155#define HM_CHANGED_SVM_MASK UINT64_C(0x0001000000000000)
156#define HM_CHANGED_SVM_HOST_GUEST_SHARED_STATE HM_CHANGED_GUEST_DR_MASK
157
158#define HM_CHANGED_ALL_GUEST ( HM_CHANGED_GUEST_MASK \
159 | HM_CHANGED_KEEPER_STATE_MASK)
160
161/** Mask of what state might have changed when IEM raised an exception.
162 * This is a based on IEM_CPUMCTX_EXTRN_XCPT_MASK. */
163#define HM_CHANGED_RAISED_XCPT_MASK ( HM_CHANGED_GUEST_GPRS_MASK \
164 | HM_CHANGED_GUEST_RIP \
165 | HM_CHANGED_GUEST_RFLAGS \
166 | HM_CHANGED_GUEST_SS \
167 | HM_CHANGED_GUEST_CS \
168 | HM_CHANGED_GUEST_CR0 \
169 | HM_CHANGED_GUEST_CR3 \
170 | HM_CHANGED_GUEST_CR4 \
171 | HM_CHANGED_GUEST_APIC_TPR \
172 | HM_CHANGED_GUEST_EFER_MSR \
173 | HM_CHANGED_GUEST_DR7 \
174 | HM_CHANGED_GUEST_CR2 \
175 | HM_CHANGED_GUEST_SREG_MASK \
176 | HM_CHANGED_GUEST_TABLE_MASK)
177
178#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
179/** Mask of what state might have changed when \#VMEXIT is emulated. */
180# define HM_CHANGED_SVM_VMEXIT_MASK ( HM_CHANGED_GUEST_RSP \
181 | HM_CHANGED_GUEST_RAX \
182 | HM_CHANGED_GUEST_RIP \
183 | HM_CHANGED_GUEST_RFLAGS \
184 | HM_CHANGED_GUEST_CS \
185 | HM_CHANGED_GUEST_SS \
186 | HM_CHANGED_GUEST_DS \
187 | HM_CHANGED_GUEST_ES \
188 | HM_CHANGED_GUEST_GDTR \
189 | HM_CHANGED_GUEST_IDTR \
190 | HM_CHANGED_GUEST_CR_MASK \
191 | HM_CHANGED_GUEST_EFER_MSR \
192 | HM_CHANGED_GUEST_DR6 \
193 | HM_CHANGED_GUEST_DR7 \
194 | HM_CHANGED_GUEST_OTHER_MSRS \
195 | HM_CHANGED_GUEST_HWVIRT \
196 | HM_CHANGED_SVM_MASK \
197 | HM_CHANGED_GUEST_APIC_TPR)
198
199/** Mask of what state might have changed when \#VMEXIT is emulated. */
200# define HM_CHANGED_SVM_VMRUN_MASK HM_CHANGED_SVM_VMEXIT_MASK
201#endif
202/** @} */
203
204/** Maximum number of exit reason statistics counters. */
205#define MAX_EXITREASON_STAT 0x100
206#define MASK_EXITREASON_STAT 0xff
207#define MASK_INJECT_IRQ_STAT 0xff
208
209/** Size for the EPT identity page table (1024 4 MB pages to cover the entire address space). */
210#define HM_EPT_IDENTITY_PG_TABLE_SIZE PAGE_SIZE
211/** Size of the TSS structure + 2 pages for the IO bitmap + end byte. */
212#define HM_VTX_TSS_SIZE (sizeof(VBOXTSS) + 2 * PAGE_SIZE + 1)
213/** Total guest mapped memory needed. */
214#define HM_VTX_TOTAL_DEVHEAP_MEM (HM_EPT_IDENTITY_PG_TABLE_SIZE + HM_VTX_TSS_SIZE)
215
216
217/** @name Macros for enabling and disabling preemption.
218 * These are really just for hiding the RTTHREADPREEMPTSTATE and asserting that
219 * preemption has already been disabled when there is no context hook.
220 * @{ */
221#ifdef VBOX_STRICT
222# define HM_DISABLE_PREEMPT(a_pVCpu) \
223 RTTHREADPREEMPTSTATE PreemptStateInternal = RTTHREADPREEMPTSTATE_INITIALIZER; \
224 Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD) || VMMR0ThreadCtxHookIsEnabled((a_pVCpu))); \
225 RTThreadPreemptDisable(&PreemptStateInternal)
226#else
227# define HM_DISABLE_PREEMPT(a_pVCpu) \
228 RTTHREADPREEMPTSTATE PreemptStateInternal = RTTHREADPREEMPTSTATE_INITIALIZER; \
229 RTThreadPreemptDisable(&PreemptStateInternal)
230#endif /* VBOX_STRICT */
231#define HM_RESTORE_PREEMPT() do { RTThreadPreemptRestore(&PreemptStateInternal); } while(0)
232/** @} */
233
234
235/** @name HM saved state versions.
236 * @{
237 */
238#define HM_SAVED_STATE_VERSION HM_SAVED_STATE_VERSION_SVM_NESTED_HWVIRT
239#define HM_SAVED_STATE_VERSION_SVM_NESTED_HWVIRT 6
240#define HM_SAVED_STATE_VERSION_TPR_PATCHING 5
241#define HM_SAVED_STATE_VERSION_NO_TPR_PATCHING 4
242#define HM_SAVED_STATE_VERSION_2_0_X 3
243/** @} */
244
245
246/**
247 * HM physical (host) CPU information.
248 */
249typedef struct HMPHYSCPU
250{
251 /** The CPU ID. */
252 RTCPUID idCpu;
253 /** The VM_HSAVE_AREA (AMD-V) / VMXON region (Intel) memory backing. */
254 RTR0MEMOBJ hMemObj;
255 /** The physical address of the first page in hMemObj (it's a
256 * physcially contigous allocation if it spans multiple pages). */
257 RTHCPHYS HCPhysMemObj;
258 /** The address of the memory (for pfnEnable). */
259 void *pvMemObj;
260 /** Current ASID (AMD-V) / VPID (Intel). */
261 uint32_t uCurrentAsid;
262 /** TLB flush count. */
263 uint32_t cTlbFlushes;
264 /** Whether to flush each new ASID/VPID before use. */
265 bool fFlushAsidBeforeUse;
266 /** Configured for VT-x or AMD-V. */
267 bool fConfigured;
268 /** Set if the VBOX_HWVIRTEX_IGNORE_SVM_IN_USE hack is active. */
269 bool fIgnoreAMDVInUseError;
270 /** In use by our code. (for power suspend) */
271 bool volatile fInUse;
272#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
273 /** Nested-guest union (put data common to SVM/VMX outside the union). */
274 union
275 {
276 /** Nested-guest SVM data. */
277 struct
278 {
279 /** The active nested-guest MSR permission bitmap memory backing. */
280 RTR0MEMOBJ hNstGstMsrpm;
281 /** The physical address of the first page in hNstGstMsrpm (physcially
282 * contiguous allocation). */
283 RTHCPHYS HCPhysNstGstMsrpm;
284 /** The address of the active nested-guest MSRPM. */
285 void *pvNstGstMsrpm;
286 } svm;
287 /** @todo Nested-VMX. */
288 } n;
289#endif
290} HMPHYSCPU;
291/** Pointer to HMPHYSCPU struct. */
292typedef HMPHYSCPU *PHMPHYSCPU;
293/** Pointer to a const HMPHYSCPU struct. */
294typedef const HMPHYSCPU *PCHMPHYSCPU;
295
296/**
297 * TPR-instruction type.
298 */
299typedef enum
300{
301 HMTPRINSTR_INVALID,
302 HMTPRINSTR_READ,
303 HMTPRINSTR_READ_SHR4,
304 HMTPRINSTR_WRITE_REG,
305 HMTPRINSTR_WRITE_IMM,
306 HMTPRINSTR_JUMP_REPLACEMENT,
307 /** The usual 32-bit paranoia. */
308 HMTPRINSTR_32BIT_HACK = 0x7fffffff
309} HMTPRINSTR;
310
311/**
312 * TPR patch information.
313 */
314typedef struct
315{
316 /** The key is the address of patched instruction. (32 bits GC ptr) */
317 AVLOU32NODECORE Core;
318 /** Original opcode. */
319 uint8_t aOpcode[16];
320 /** Instruction size. */
321 uint32_t cbOp;
322 /** Replacement opcode. */
323 uint8_t aNewOpcode[16];
324 /** Replacement instruction size. */
325 uint32_t cbNewOp;
326 /** Instruction type. */
327 HMTPRINSTR enmType;
328 /** Source operand. */
329 uint32_t uSrcOperand;
330 /** Destination operand. */
331 uint32_t uDstOperand;
332 /** Number of times the instruction caused a fault. */
333 uint32_t cFaults;
334 /** Patch address of the jump replacement. */
335 RTGCPTR32 pJumpTarget;
336} HMTPRPATCH;
337/** Pointer to HMTPRPATCH. */
338typedef HMTPRPATCH *PHMTPRPATCH;
339/** Pointer to a const HMTPRPATCH. */
340typedef const HMTPRPATCH *PCHMTPRPATCH;
341
342
343/**
344 * Makes a HMEXITSTAT::uKey value from a program counter and an exit code.
345 *
346 * @returns 64-bit key
347 * @param a_uPC The RIP + CS.BASE value of the exit.
348 * @param a_uExit The exit code.
349 * @todo Add CPL?
350 */
351#define HMEXITSTAT_MAKE_KEY(a_uPC, a_uExit) (((a_uPC) & UINT64_C(0x0000ffffffffffff)) | (uint64_t)(a_uExit) << 48)
352
353typedef struct HMEXITINFO
354{
355 /** See HMEXITSTAT_MAKE_KEY(). */
356 uint64_t uKey;
357 /** Number of recent hits (depreciates with time). */
358 uint32_t volatile cHits;
359 /** The age + lock. */
360 uint16_t volatile uAge;
361 /** Action or action table index. */
362 uint16_t iAction;
363} HMEXITINFO;
364AssertCompileSize(HMEXITINFO, 16); /* Lots of these guys, so don't add any unnecessary stuff! */
365
366typedef struct HMEXITHISTORY
367{
368 /** The exit timestamp. */
369 uint64_t uTscExit;
370 /** The index of the corresponding HMEXITINFO entry.
371 * UINT32_MAX if none (too many collisions, race, whatever). */
372 uint32_t iExitInfo;
373 /** Figure out later, needed for padding now. */
374 uint32_t uSomeClueOrSomething;
375} HMEXITHISTORY;
376
377/**
378 * Switcher function, HC to the special 64-bit RC.
379 *
380 * @param pVM The cross context VM structure.
381 * @param offCpumVCpu Offset from pVM->cpum to pVM->aCpus[idCpu].cpum.
382 * @returns Return code indicating the action to take.
383 */
384typedef DECLCALLBACK(int) FNHMSWITCHERHC(PVM pVM, uint32_t offCpumVCpu);
385/** Pointer to switcher function. */
386typedef FNHMSWITCHERHC *PFNHMSWITCHERHC;
387
388/** @def HM_UNION_NM
389 * For compilers (like DTrace) that does not grok nameless unions, we have a
390 * little hack to make them palatable.
391 */
392/** @def HM_STRUCT_NM
393 * For compilers (like DTrace) that does not grok nameless structs (it is
394 * non-standard C++), we have a little hack to make them palatable.
395 */
396#ifdef VBOX_FOR_DTRACE_LIB
397# define HM_UNION_NM(a_Nm) a_Nm
398# define HM_STRUCT_NM(a_Nm) a_Nm
399#elif defined(IPRT_WITHOUT_NAMED_UNIONS_AND_STRUCTS)
400# define HM_UNION_NM(a_Nm) a_Nm
401# define HM_STRUCT_NM(a_Nm) a_Nm
402#else
403# define HM_UNION_NM(a_Nm)
404# define HM_STRUCT_NM(a_Nm)
405#endif
406
407/**
408 * HM event.
409 *
410 * VT-x and AMD-V common event injection structure.
411 */
412typedef struct HMEVENT
413{
414 /** Whether the event is pending. */
415 uint32_t fPending;
416 /** The error-code associated with the event. */
417 uint32_t u32ErrCode;
418 /** The length of the instruction in bytes (only relevant for software
419 * interrupts or software exceptions). */
420 uint32_t cbInstr;
421 /** Alignment. */
422 uint32_t u32Padding;
423 /** The encoded event (VM-entry interruption-information for VT-x or EVENTINJ
424 * for SVM). */
425 uint64_t u64IntInfo;
426 /** Guest virtual address if this is a page-fault event. */
427 RTGCUINTPTR GCPtrFaultAddress;
428} HMEVENT;
429/** Pointer to a HMEVENT struct. */
430typedef HMEVENT *PHMEVENT;
431/** Pointer to a const HMEVENT struct. */
432typedef const HMEVENT *PCHMEVENT;
433AssertCompileSizeAlignment(HMEVENT, 8);
434
435/**
436 * HM VM Instance data.
437 * Changes to this must checked against the padding of the hm union in VM!
438 */
439typedef struct HM
440{
441 /** Set when we've initialized VMX or SVM. */
442 bool fInitialized;
443 /** Set if nested paging is enabled. */
444 bool fNestedPaging;
445 /** Set if nested paging is allowed. */
446 bool fAllowNestedPaging;
447 /** Set if large pages are enabled (requires nested paging). */
448 bool fLargePages;
449 /** Set if we can support 64-bit guests or not. */
450 bool fAllow64BitGuests;
451 /** Set when TPR patching is allowed. */
452 bool fTprPatchingAllowed;
453 /** Set when we initialize VT-x or AMD-V once for all CPUs. */
454 bool fGlobalInit;
455 /** Set when TPR patching is active. */
456 bool fTPRPatchingActive;
457 /** Set when the debug facility has breakpoints/events enabled that requires
458 * us to use the debug execution loop in ring-0. */
459 bool fUseDebugLoop;
460 /** Set if hardware APIC virtualization is enabled. */
461 bool fVirtApicRegs;
462 /** Set if posted interrupt processing is enabled. */
463 bool fPostedIntrs;
464 /** Set if indirect branch prediction barrier on VM exit. */
465 bool fIbpbOnVmExit;
466 /** Set if indirect branch prediction barrier on VM entry. */
467 bool fIbpbOnVmEntry;
468 /** Set if level 1 data cache should be flushed on VM entry. */
469 bool fL1dFlushOnVmEntry;
470 /** Set if level 1 data cache should be flushed on EMT scheduling. */
471 bool fL1dFlushOnSched;
472 /** Set if host manages speculation control settings. */
473 bool fSpecCtrlByHost;
474 /** Set if MDS related buffers should be cleared on VM entry. */
475 bool fMdsClearOnVmEntry;
476 /** Set if MDS related buffers should be cleared on EMT scheduling. */
477 bool fMdsClearOnSched;
478 /** Alignment padding. */
479 bool afPaddingMinus1[6];
480
481 /** Maximum ASID allowed. */
482 uint32_t uMaxAsid;
483 /** The maximum number of resumes loops allowed in ring-0 (safety precaution).
484 * This number is set much higher when RTThreadPreemptIsPending is reliable. */
485 uint32_t cMaxResumeLoops;
486
487 /** Host kernel flags that HM might need to know (SUPKERNELFEATURES_XXX). */
488 uint32_t fHostKernelFeatures;
489
490 /** Size of the guest patch memory block. */
491 uint32_t cbGuestPatchMem;
492 /** Guest allocated memory for patching purposes. */
493 RTGCPTR pGuestPatchMem;
494 /** Current free pointer inside the patch block. */
495 RTGCPTR pFreeGuestPatchMem;
496
497#if HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS)
498 /** 32 to 64 bits switcher entrypoint. */
499 R0PTRTYPE(PFNHMSWITCHERHC) pfnHost32ToGuest64R0;
500 RTR0PTR pvR0Alignment0;
501#endif
502
503 struct
504 {
505 /** Set by the ring-0 side of HM to indicate VMX is supported by the
506 * CPU. */
507 bool fSupported;
508 /** Set when we've enabled VMX. */
509 bool fEnabled;
510 /** Set if VPID is supported. */
511 bool fVpid;
512 /** Set if VT-x VPID is allowed. */
513 bool fAllowVpid;
514 /** Set if unrestricted guest execution is in use (real and protected mode without paging). */
515 bool fUnrestrictedGuest;
516 /** Set if unrestricted guest execution is allowed to be used. */
517 bool fAllowUnrestricted;
518 /** Set if the preemption timer is in use or not. */
519 bool fUsePreemptTimer;
520 /** The shift mask employed by the VMX-Preemption timer. */
521 uint8_t cPreemptTimerShift;
522
523 /** Virtual address of the TSS page used for real mode emulation. */
524 R3PTRTYPE(PVBOXTSS) pRealModeTSS;
525 /** Virtual address of the identity page table used for real mode and protected mode without paging emulation in EPT mode. */
526 R3PTRTYPE(PX86PD) pNonPagingModeEPTPageTable;
527
528 /** Physical address of the APIC-access page. */
529 RTHCPHYS HCPhysApicAccess;
530 /** R0 memory object for the APIC-access page. */
531 RTR0MEMOBJ hMemObjApicAccess;
532 /** Virtual address of the APIC-access page. */
533 R0PTRTYPE(uint8_t *) pbApicAccess;
534
535#ifdef VBOX_WITH_CRASHDUMP_MAGIC
536 RTHCPHYS HCPhysScratch;
537 RTR0MEMOBJ hMemObjScratch;
538 R0PTRTYPE(uint8_t *) pbScratch;
539#endif
540
541 /** Tagged-TLB flush type. */
542 VMXTLBFLUSHTYPE enmTlbFlushType;
543 /** Flush type to use for INVEPT. */
544 VMXTLBFLUSHEPT enmTlbFlushEpt;
545 /** Flush type to use for INVVPID. */
546 VMXTLBFLUSHVPID enmTlbFlushVpid;
547
548 /** Pause-loop exiting (PLE) gap in ticks. */
549 uint32_t cPleGapTicks;
550 /** Pause-loop exiting (PLE) window in ticks. */
551 uint32_t cPleWindowTicks;
552 uint32_t u32Alignment0;
553
554 /** Host CR4 value (set by ring-0 VMX init) */
555 uint64_t u64HostCr4;
556 /** Host SMM monitor control (set by ring-0 VMX init) */
557 uint64_t u64HostSmmMonitorCtl;
558 /** Host EFER value (set by ring-0 VMX init) */
559 uint64_t u64HostMsrEfer;
560 /** Whether the CPU supports VMCS fields for swapping EFER. */
561 bool fSupportsVmcsEfer;
562 uint8_t u8Alignment2[7];
563
564 /** VMX MSR values. */
565 VMXMSRS Msrs;
566
567 /** Host-physical address for a failing VMXON instruction. */
568 RTHCPHYS HCPhysVmxEnableError;
569 } vmx;
570
571 struct
572 {
573 /** Set by the ring-0 side of HM to indicate SVM is supported by the
574 * CPU. */
575 bool fSupported;
576 /** Set when we've enabled SVM. */
577 bool fEnabled;
578 /** Set if erratum 170 affects the AMD cpu. */
579 bool fAlwaysFlushTLB;
580 /** Set when the hack to ignore VERR_SVM_IN_USE is active. */
581 bool fIgnoreInUseError;
582 /** Whether to use virtualized VMSAVE/VMLOAD feature. */
583 bool fVirtVmsaveVmload;
584 /** Whether to use virtual GIF feature. */
585 bool fVGif;
586 uint8_t u8Alignment0[2];
587
588 /** Physical address of the IO bitmap (12kb). */
589 RTHCPHYS HCPhysIOBitmap;
590 /** R0 memory object for the IO bitmap (12kb). */
591 RTR0MEMOBJ hMemObjIOBitmap;
592 /** Virtual address of the IO bitmap. */
593 R0PTRTYPE(void *) pvIOBitmap;
594
595 /* HWCR MSR (for diagnostics) */
596 uint64_t u64MsrHwcr;
597
598 /** SVM revision. */
599 uint32_t u32Rev;
600 /** SVM feature bits from cpuid 0x8000000a */
601 uint32_t u32Features;
602
603 /** Pause filter counter. */
604 uint16_t cPauseFilter;
605 /** Pause filter treshold in ticks. */
606 uint16_t cPauseFilterThresholdTicks;
607 uint32_t u32Alignment0;
608 } svm;
609
610 /**
611 * AVL tree with all patches (active or disabled) sorted by guest instruction
612 * address.
613 */
614 AVLOU32TREE PatchTree;
615 uint32_t cPatches;
616 HMTPRPATCH aPatches[64];
617
618 /** Last recorded error code during HM ring-0 init. */
619 int32_t rcInit;
620
621 /** HMR0Init was run */
622 bool fHMR0Init;
623 bool u8Alignment1[3];
624
625 STAMCOUNTER StatTprPatchSuccess;
626 STAMCOUNTER StatTprPatchFailure;
627 STAMCOUNTER StatTprReplaceSuccessCr8;
628 STAMCOUNTER StatTprReplaceSuccessVmc;
629 STAMCOUNTER StatTprReplaceFailure;
630} HM;
631/** Pointer to HM VM instance data. */
632typedef HM *PHM;
633
634AssertCompileMemberAlignment(HM, StatTprPatchSuccess, 8);
635
636/* Maximum number of cached entries. */
637#define VMX_VMCS_CACHE_MAX_ENTRY 128
638
639/**
640 * Cache of a VMCS for batch reads or writes.
641 */
642typedef struct VMXVMCSCACHE
643{
644#ifdef VBOX_WITH_CRASHDUMP_MAGIC
645 /* Magic marker for searching in crash dumps. */
646 uint8_t aMagic[16];
647 uint64_t uMagic;
648 uint64_t u64TimeEntry;
649 uint64_t u64TimeSwitch;
650 uint64_t cResume;
651 uint64_t interPD;
652 uint64_t pSwitcher;
653 uint32_t uPos;
654 uint32_t idCpu;
655#endif
656 /* CR2 is saved here for EPT syncing. */
657 uint64_t cr2;
658 struct
659 {
660 uint32_t cValidEntries;
661 uint32_t uAlignment;
662 uint32_t aField[VMX_VMCS_CACHE_MAX_ENTRY];
663 uint64_t aFieldVal[VMX_VMCS_CACHE_MAX_ENTRY];
664 } Write;
665 struct
666 {
667 uint32_t cValidEntries;
668 uint32_t uAlignment;
669 uint32_t aField[VMX_VMCS_CACHE_MAX_ENTRY];
670 uint64_t aFieldVal[VMX_VMCS_CACHE_MAX_ENTRY];
671 } Read;
672#ifdef VBOX_STRICT
673 struct
674 {
675 RTHCPHYS HCPhysCpuPage;
676 RTHCPHYS HCPhysVmcs;
677 RTGCPTR pCache;
678 RTGCPTR pCtx;
679 } TestIn;
680 struct
681 {
682 RTHCPHYS HCPhysVmcs;
683 RTGCPTR pCache;
684 RTGCPTR pCtx;
685 uint64_t eflags;
686 uint64_t cr8;
687 } TestOut;
688 struct
689 {
690 uint64_t param1;
691 uint64_t param2;
692 uint64_t param3;
693 uint64_t param4;
694 } ScratchPad;
695#endif
696} VMXVMCSCACHE;
697/** Pointer to VMXVMCSCACHE. */
698typedef VMXVMCSCACHE *PVMXVMCSCACHE;
699AssertCompileSizeAlignment(VMXVMCSCACHE, 8);
700
701/**
702 * VMX StartVM function.
703 *
704 * @returns VBox status code (no informational stuff).
705 * @param fResume Whether to use VMRESUME (true) or VMLAUNCH (false).
706 * @param pCtx The CPU register context.
707 * @param pVmcsCache The VMCS batch cache.
708 * @param pVM Pointer to the cross context VM structure.
709 * @param pVCpu Pointer to the cross context per-CPU structure.
710 */
711typedef DECLCALLBACK(int) FNHMVMXSTARTVM(RTHCUINT fResume, PCPUMCTX pCtx, PVMXVMCSCACHE pVmcsCache, PVM pVM, PVMCPU pVCpu);
712/** Pointer to a VMX StartVM function. */
713typedef R0PTRTYPE(FNHMVMXSTARTVM *) PFNHMVMXSTARTVM;
714
715/** SVM VMRun function. */
716typedef DECLCALLBACK(int) FNHMSVMVMRUN(RTHCPHYS pVmcbHostPhys, RTHCPHYS pVmcbPhys, PCPUMCTX pCtx, PVM pVM, PVMCPU pVCpu);
717/** Pointer to a SVM VMRun function. */
718typedef R0PTRTYPE(FNHMSVMVMRUN *) PFNHMSVMVMRUN;
719
720/**
721 * VMX VMCS information.
722 *
723 * This structure provides information maintained for and during the executing of a
724 * guest (or nested-guest) VMCS (VM control structure) using hardware-assisted VMX.
725 */
726typedef struct VMXVMCSINFO
727{
728 /** @name VMLAUNCH/VMRESUME information.
729 * @{ */
730 /** Ring-0 pointer to the hardware-assisted VMX execution function. */
731 PFNHMVMXSTARTVM pfnStartVM;
732#if HC_ARCH_BITS == 32
733 uint32_t u32Alignment0;
734#endif
735 /** @} */
736
737 /** @name VMCS and related data structures.
738 * @{ */
739 /** Host-physical address of the VMCS. */
740 RTHCPHYS HCPhysVmcs;
741 /** R0 memory object for the VMCS. */
742 RTR0MEMOBJ hMemObjVmcs;
743 /** Host-virtual address of the VMCS. */
744 R0PTRTYPE(void *) pvVmcs;
745
746 /** Host-physical address of the virtual APIC page. */
747 RTHCPHYS HCPhysVirtApic;
748 /** Alignment. */
749 R0PTRTYPE(void *) pvAlignment0;
750 /** Host-virtual address of the virtual-APIC page. */
751 R0PTRTYPE(uint8_t *) pbVirtApic;
752
753 /** Host-physical address of the MSR bitmap. */
754 RTHCPHYS HCPhysMsrBitmap;
755 /** R0 memory object for the MSR bitmap. */
756 RTR0MEMOBJ hMemObjMsrBitmap;
757 /** Host-virtual address of the MSR bitmap. */
758 R0PTRTYPE(void *) pvMsrBitmap;
759
760 /** Host-physical address of the VM-entry MSR-load area. */
761 RTHCPHYS HCPhysGuestMsrLoad;
762 /** R0 memory object of the VM-entry MSR-load area. */
763 RTR0MEMOBJ hMemObjGuestMsrLoad;
764 /** Host-virtual address of the VM-entry MSR-load area. */
765 R0PTRTYPE(void *) pvGuestMsrLoad;
766
767 /** Host-physical address of the VM-exit MSR-store area. */
768 RTHCPHYS HCPhysGuestMsrStore;
769 /** R0 memory object of the VM-exit MSR-store area. */
770 RTR0MEMOBJ hMemObjGuestMsrStore;
771 /** Host-virtual address of the VM-exit MSR-store area. */
772 R0PTRTYPE(void *) pvGuestMsrStore;
773
774 /** Host-physical address of the VM-exit MSR-load area. */
775 RTHCPHYS HCPhysHostMsrLoad;
776 /** R0 memory object for the VM-exit MSR-load area. */
777 RTR0MEMOBJ hMemObjHostMsrLoad;
778 /** Host-virtual address of the VM-exit MSR-load area. */
779 R0PTRTYPE(void *) pvHostMsrLoad;
780
781 /** Host-physical address of the EPTP. */
782 RTHCPHYS HCPhysEPTP;
783 /** Number of guest MSRs in the VM-entry MSR-load area. */
784 uint32_t cEntryMsrLoad;
785 /** Number of guest MSRs in the VM-exit MSR-store area. */
786 uint32_t cExitMsrStore;
787 /** Number of host MSRs in the VM-exit MSR-load area. */
788 uint32_t cExitMsrLoad;
789 /** Padding. */
790 uint32_t u32Padding0;
791 /** @} */
792
793 /** @name Auxiliary information.
794 * @{ */
795 /** The VMCS launch state, see VMX_V_VMCS_LAUNCH_STATE_XXX. */
796 uint32_t fVmcsState;
797 /** Set if guest was executing in real mode (extra checks). */
798 bool fWasInRealMode;
799 /** Set if the guest switched to 64-bit mode on a 32-bit host. */
800 bool fSwitchedTo64on32;
801 /** Padding. */
802 bool afPadding0[2];
803 /** @} */
804
805 /** @name Cache of execution related VMCS fields.
806 * @{ */
807 /** Pin-based VM-execution controls. */
808 uint32_t u32PinCtls;
809 /** Processor-based VM-execution controls. */
810 uint32_t u32ProcCtls;
811 /** Secondary processor-based VM-execution controls. */
812 uint32_t u32ProcCtls2;
813 /** VM-entry controls. */
814 uint32_t u32EntryCtls;
815 /** VM-exit controls. */
816 uint32_t u32ExitCtls;
817 /** Exception bitmap. */
818 uint32_t u32XcptBitmap;
819 /** CR0 guest/host mask. */
820 uint64_t u64Cr0Mask;
821 /** CR4 guest/host mask. */
822 uint64_t u64Cr4Mask;
823 /** Page-fault exception error-code mask. */
824 uint32_t u32XcptPFMask;
825 /** Page-fault exception error-code match. */
826 uint32_t u32XcptPFMatch;
827 /** TSC offset. */
828 uint64_t u64TscOffset;
829 /** VMCS link pointer. */
830 uint64_t u64VmcsLinkPtr;
831 /** @} */
832
833 /** @name Real-mode emulation state.
834 * @{ */
835 struct
836 {
837 X86DESCATTR AttrCS;
838 X86DESCATTR AttrDS;
839 X86DESCATTR AttrES;
840 X86DESCATTR AttrFS;
841 X86DESCATTR AttrGS;
842 X86DESCATTR AttrSS;
843 X86EFLAGS Eflags;
844 bool fRealOnV86Active;
845 bool afPadding1[3];
846 } RealMode;
847 /** @} */
848
849 /** Padding. */
850 uint64_t au64Padding[2];
851} VMXVMCSINFO;
852/** Pointer to a VMXVMCSINFO struct. */
853typedef VMXVMCSINFO *PVMXVMCSINFO;
854/** Pointer to a const VMXVMCSINFO struct. */
855typedef const VMXVMCSINFO *PCVMXVMCSINFO;
856AssertCompileSizeAlignment(VMXVMCSINFO, 8);
857AssertCompileMemberAlignment(VMXVMCSINFO, fVmcsState, 8);
858AssertCompileMemberAlignment(VMXVMCSINFO, u32PinCtls, 8);
859AssertCompileMemberAlignment(VMXVMCSINFO, u64VmcsLinkPtr, 8);
860
861/**
862 * HM VMCPU Instance data.
863 *
864 * Note! If you change members of this struct, make sure to check if the
865 * assembly counterpart in HMInternal.mac needs to be updated as well.
866 */
867typedef struct HMCPU
868{
869 /** Set when the TLB has been checked until we return from the world switch. */
870 bool volatile fCheckedTLBFlush;
871 /** Set if we need to flush the TLB during the world switch. */
872 bool fForceTLBFlush;
873 /** Set when we're using VT-x or AMD-V at that moment. */
874 bool fActive;
875 /** Whether we've completed the inner HM leave function. */
876 bool fLeaveDone;
877 /** Whether we're using the hyper DR7 or guest DR7. */
878 bool fUsingHyperDR7;
879 /** Set if XCR0 needs to be saved/restored when entering/exiting guest code
880 * execution. */
881 bool fLoadSaveGuestXcr0;
882
883 /** Whether we should use the debug loop because of single stepping or special
884 * debug breakpoints / events are armed. */
885 bool fUseDebugLoop;
886 /** Whether we are currently executing in the debug loop.
887 * Mainly for assertions. */
888 bool fUsingDebugLoop;
889 /** Set if we using the debug loop and wish to intercept RDTSC. */
890 bool fDebugWantRdTscExit;
891 /** Whether we're executing a single instruction. */
892 bool fSingleInstruction;
893 /** Set if we need to clear the trap flag because of single stepping. */
894 bool fClearTrapFlag;
895
896 /** Whether \#UD needs to be intercepted (required by certain GIM providers). */
897 bool fGIMTrapXcptUD;
898 /** Whether \#GP needs to be intercept for mesa driver workaround. */
899 bool fTrapXcptGpForLovelyMesaDrv;
900 uint8_t u8Alignment0[3];
901
902 /** World switch exit counter. */
903 uint32_t volatile cWorldSwitchExits;
904 /** The last CPU we were executing code on (NIL_RTCPUID for the first time). */
905 RTCPUID idLastCpu;
906 /** TLB flush count. */
907 uint32_t cTlbFlushes;
908 /** Current ASID in use by the VM. */
909 uint32_t uCurrentAsid;
910 /** An additional error code used for some gurus. */
911 uint32_t u32HMError;
912 /** The last exit-to-ring-3 reason. */
913 int32_t rcLastExitToR3;
914 /** CPU-context changed flags (see HM_CHANGED_xxx). */
915 uint64_t fCtxChanged;
916 /** Host's TSC_AUX MSR (used when RDTSCP doesn't cause VM-exits). */
917 uint64_t u64HostTscAux; /** @todo r=ramshankar: Can be removed and put in SVMTRANSIENT instead! */
918
919 union /* no tag! */
920 {
921 /** VT-x data. */
922 struct
923 {
924 /** @name Guest information.
925 * @{ */
926 /** Guest VMCS information. */
927 VMXVMCSINFO VmcsInfo;
928 /** Nested-guest VMCS information. */
929 VMXVMCSINFO VmcsInfoNstGst;
930 /** Whether the nested-guest VMCS was the last current VMCS. */
931 bool fSwitchedToNstGstVmcs;
932 /** Whether the static guest VMCS controls has been merged with the
933 * nested-guest VMCS controls. */
934 bool fMergedNstGstCtls;
935 /** Alignment. */
936 bool afAlignment0[6];
937 /** Cached guest APIC-base MSR for identifying when to map the APIC-access page. */
938 uint64_t u64GstMsrApicBase;
939 /** VMCS cache for batched vmread/vmwrites. */
940 VMXVMCSCACHE VmcsCache;
941 /** @} */
942
943 /** @name Host information.
944 * @{ */
945 /** Host LSTAR MSR to restore lazily while leaving VT-x. */
946 uint64_t u64HostMsrLStar;
947 /** Host STAR MSR to restore lazily while leaving VT-x. */
948 uint64_t u64HostMsrStar;
949 /** Host SF_MASK MSR to restore lazily while leaving VT-x. */
950 uint64_t u64HostMsrSfMask;
951 /** Host KernelGS-Base MSR to restore lazily while leaving VT-x. */
952 uint64_t u64HostMsrKernelGsBase;
953 /** The mask of lazy MSRs swap/restore state, see VMX_LAZY_MSRS_XXX. */
954 uint32_t fLazyMsrs;
955 /** Whether the host MSR values are up-to-date in the auto-load/store MSR area. */
956 bool fUpdatedHostAutoMsrs;
957 /** Alignment. */
958 uint8_t au8Alignment0[3];
959 /** Which host-state bits to restore before being preempted. */
960 uint32_t fRestoreHostFlags;
961 /** Alignment. */
962 uint32_t u32Alignment0;
963 /** The host-state restoration structure. */
964 VMXRESTOREHOST RestoreHost;
965 /** @} */
966
967 /** @name Error reporting and diagnostics.
968 * @{ */
969 /** VT-x error-reporting (mainly for ring-3 propagation). */
970 struct
971 {
972 RTHCPHYS HCPhysCurrentVmcs;
973 uint32_t u32VmcsRev;
974 uint32_t u32InstrError;
975 uint32_t u32ExitReason;
976 uint32_t u32Alignment0;
977 RTCPUID idEnteredCpu;
978 RTCPUID idCurrentCpu;
979 } LastError;
980 /** @} */
981 } vmx;
982
983 /** SVM data. */
984 struct
985 {
986 /** Ring 0 handlers for VT-x. */
987 PFNHMSVMVMRUN pfnVMRun;
988#if HC_ARCH_BITS == 32
989 uint32_t u32Alignment0;
990#endif
991
992 /** Physical address of the host VMCB which holds additional host-state. */
993 RTHCPHYS HCPhysVmcbHost;
994 /** R0 memory object for the host VMCB which holds additional host-state. */
995 RTR0MEMOBJ hMemObjVmcbHost;
996 /** Padding. */
997 R0PTRTYPE(void *) pvPadding;
998
999 /** Physical address of the guest VMCB. */
1000 RTHCPHYS HCPhysVmcb;
1001 /** R0 memory object for the guest VMCB. */
1002 RTR0MEMOBJ hMemObjVmcb;
1003 /** Pointer to the guest VMCB. */
1004 R0PTRTYPE(PSVMVMCB) pVmcb;
1005
1006 /** Physical address of the MSR bitmap (8 KB). */
1007 RTHCPHYS HCPhysMsrBitmap;
1008 /** R0 memory object for the MSR bitmap (8 KB). */
1009 RTR0MEMOBJ hMemObjMsrBitmap;
1010 /** Pointer to the MSR bitmap. */
1011 R0PTRTYPE(void *) pvMsrBitmap;
1012
1013 /** Whether VTPR with V_INTR_MASKING set is in effect, indicating
1014 * we should check if the VTPR changed on every VM-exit. */
1015 bool fSyncVTpr;
1016 uint8_t au8Alignment0[7];
1017
1018 /** Cache of the nested-guest's VMCB fields that we modify in order to run the
1019 * nested-guest using AMD-V. This will be restored on \#VMEXIT. */
1020 SVMNESTEDVMCBCACHE NstGstVmcbCache;
1021 } svm;
1022 } HM_UNION_NM(u);
1023
1024 /** Event injection state. */
1025 HMEVENT Event;
1026
1027 /** The PAE PDPEs used with Nested Paging (only valid when
1028 * VMCPU_FF_HM_UPDATE_PAE_PDPES is set). */
1029 X86PDPE aPdpes[4];
1030
1031 /** Current shadow paging mode for updating CR4. */
1032 PGMMODE enmShadowMode;
1033
1034 /** The CPU ID of the CPU currently owning the VMCS. Set in
1035 * HMR0Enter and cleared in HMR0Leave. */
1036 RTCPUID idEnteredCpu;
1037
1038 /** For saving stack space, the disassembler state is allocated here instead of
1039 * on the stack. */
1040 DISCPUSTATE DisState;
1041
1042 STAMPROFILEADV StatEntry;
1043 STAMPROFILEADV StatPreExit;
1044 STAMPROFILEADV StatExitHandling;
1045 STAMPROFILEADV StatExitIO;
1046 STAMPROFILEADV StatExitMovCRx;
1047 STAMPROFILEADV StatExitXcptNmi;
1048 STAMPROFILEADV StatImportGuestState;
1049 STAMPROFILEADV StatExportGuestState;
1050 STAMPROFILEADV StatLoadGuestFpuState;
1051 STAMPROFILEADV StatInGC;
1052#if HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS)
1053 STAMPROFILEADV StatWorldSwitch3264;
1054#endif
1055 STAMPROFILEADV StatPoke;
1056 STAMPROFILEADV StatSpinPoke;
1057 STAMPROFILEADV StatSpinPokeFailed;
1058
1059 STAMCOUNTER StatInjectInterrupt;
1060 STAMCOUNTER StatInjectXcpt;
1061 STAMCOUNTER StatInjectPendingReflect;
1062 STAMCOUNTER StatInjectPendingInterpret;
1063
1064 STAMCOUNTER StatExitAll;
1065 STAMCOUNTER StatExitShadowNM;
1066 STAMCOUNTER StatExitGuestNM;
1067 STAMCOUNTER StatExitShadowPF; /**< Misleading, currently used for MMIO \#PFs as well. */
1068 STAMCOUNTER StatExitShadowPFEM;
1069 STAMCOUNTER StatExitGuestPF;
1070 STAMCOUNTER StatExitGuestUD;
1071 STAMCOUNTER StatExitGuestSS;
1072 STAMCOUNTER StatExitGuestNP;
1073 STAMCOUNTER StatExitGuestTS;
1074 STAMCOUNTER StatExitGuestGP;
1075 STAMCOUNTER StatExitGuestDE;
1076 STAMCOUNTER StatExitGuestDB;
1077 STAMCOUNTER StatExitGuestMF;
1078 STAMCOUNTER StatExitGuestBP;
1079 STAMCOUNTER StatExitGuestXF;
1080 STAMCOUNTER StatExitGuestXcpUnk;
1081 STAMCOUNTER StatExitDRxWrite;
1082 STAMCOUNTER StatExitDRxRead;
1083 STAMCOUNTER StatExitCR0Read;
1084 STAMCOUNTER StatExitCR2Read;
1085 STAMCOUNTER StatExitCR3Read;
1086 STAMCOUNTER StatExitCR4Read;
1087 STAMCOUNTER StatExitCR8Read;
1088 STAMCOUNTER StatExitCR0Write;
1089 STAMCOUNTER StatExitCR2Write;
1090 STAMCOUNTER StatExitCR3Write;
1091 STAMCOUNTER StatExitCR4Write;
1092 STAMCOUNTER StatExitCR8Write;
1093 STAMCOUNTER StatExitRdmsr;
1094 STAMCOUNTER StatExitWrmsr;
1095 STAMCOUNTER StatExitClts;
1096 STAMCOUNTER StatExitXdtrAccess;
1097 STAMCOUNTER StatExitLmsw;
1098 STAMCOUNTER StatExitIOWrite;
1099 STAMCOUNTER StatExitIORead;
1100 STAMCOUNTER StatExitIOStringWrite;
1101 STAMCOUNTER StatExitIOStringRead;
1102 STAMCOUNTER StatExitIntWindow;
1103 STAMCOUNTER StatExitExtInt;
1104 STAMCOUNTER StatExitHostNmiInGC;
1105 STAMCOUNTER StatExitPreemptTimer;
1106 STAMCOUNTER StatExitTprBelowThreshold;
1107 STAMCOUNTER StatExitTaskSwitch;
1108 STAMCOUNTER StatExitApicAccess;
1109 STAMCOUNTER StatExitReasonNpf;
1110
1111 STAMCOUNTER StatNestedExitReasonNpf;
1112
1113 STAMCOUNTER StatFlushPage;
1114 STAMCOUNTER StatFlushPageManual;
1115 STAMCOUNTER StatFlushPhysPageManual;
1116 STAMCOUNTER StatFlushTlb;
1117 STAMCOUNTER StatFlushTlbManual;
1118 STAMCOUNTER StatFlushTlbWorldSwitch;
1119 STAMCOUNTER StatNoFlushTlbWorldSwitch;
1120 STAMCOUNTER StatFlushEntire;
1121 STAMCOUNTER StatFlushAsid;
1122 STAMCOUNTER StatFlushNestedPaging;
1123 STAMCOUNTER StatFlushTlbInvlpgVirt;
1124 STAMCOUNTER StatFlushTlbInvlpgPhys;
1125 STAMCOUNTER StatTlbShootdown;
1126 STAMCOUNTER StatTlbShootdownFlush;
1127
1128 STAMCOUNTER StatSwitchPendingHostIrq;
1129 STAMCOUNTER StatSwitchTprMaskedIrq;
1130 STAMCOUNTER StatSwitchGuestIrq;
1131 STAMCOUNTER StatSwitchHmToR3FF;
1132 STAMCOUNTER StatSwitchExitToR3;
1133 STAMCOUNTER StatSwitchLongJmpToR3;
1134 STAMCOUNTER StatSwitchMaxResumeLoops;
1135 STAMCOUNTER StatSwitchHltToR3;
1136 STAMCOUNTER StatSwitchApicAccessToR3;
1137 STAMCOUNTER StatSwitchPreempt;
1138 STAMCOUNTER StatSwitchPreemptExportHostState;
1139
1140 STAMCOUNTER StatTscParavirt;
1141 STAMCOUNTER StatTscOffset;
1142 STAMCOUNTER StatTscIntercept;
1143
1144 STAMCOUNTER StatDRxArmed;
1145 STAMCOUNTER StatDRxContextSwitch;
1146 STAMCOUNTER StatDRxIoCheck;
1147
1148 STAMCOUNTER StatExportMinimal;
1149 STAMCOUNTER StatExportFull;
1150 STAMCOUNTER StatLoadGuestFpu;
1151
1152 STAMCOUNTER StatVmxCheckBadRmSelBase;
1153 STAMCOUNTER StatVmxCheckBadRmSelLimit;
1154 STAMCOUNTER StatVmxCheckBadRmSelAttr;
1155 STAMCOUNTER StatVmxCheckBadV86SelBase;
1156 STAMCOUNTER StatVmxCheckBadV86SelLimit;
1157 STAMCOUNTER StatVmxCheckBadV86SelAttr;
1158 STAMCOUNTER StatVmxCheckRmOk;
1159 STAMCOUNTER StatVmxCheckBadSel;
1160 STAMCOUNTER StatVmxCheckBadRpl;
1161 STAMCOUNTER StatVmxCheckPmOk;
1162
1163#if HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS)
1164 STAMCOUNTER StatFpu64SwitchBack;
1165 STAMCOUNTER StatDebug64SwitchBack;
1166#endif
1167#ifdef VBOX_WITH_STATISTICS
1168 R3PTRTYPE(PSTAMCOUNTER) paStatExitReason;
1169 R0PTRTYPE(PSTAMCOUNTER) paStatExitReasonR0;
1170 R3PTRTYPE(PSTAMCOUNTER) paStatInjectedIrqs;
1171 R0PTRTYPE(PSTAMCOUNTER) paStatInjectedIrqsR0;
1172 R3PTRTYPE(PSTAMCOUNTER) paStatNestedExitReason;
1173 R0PTRTYPE(PSTAMCOUNTER) paStatNestedExitReasonR0;
1174#endif
1175#ifdef HM_PROFILE_EXIT_DISPATCH
1176 STAMPROFILEADV StatExitDispatch;
1177#endif
1178} HMCPU;
1179/** Pointer to HM VMCPU instance data. */
1180typedef HMCPU *PHMCPU;
1181AssertCompileMemberAlignment(HMCPU, cWorldSwitchExits, 4);
1182AssertCompileMemberAlignment(HMCPU, fCtxChanged, 8);
1183AssertCompileMemberAlignment(HMCPU, HM_UNION_NM(u.) vmx, 8);
1184AssertCompileMemberAlignment(HMCPU, HM_UNION_NM(u.) svm, 8);
1185AssertCompileMemberAlignment(HMCPU, Event, 8);
1186
1187#ifdef IN_RING0
1188VMMR0_INT_DECL(PHMPHYSCPU) hmR0GetCurrentCpu(void);
1189VMMR0_INT_DECL(int) hmR0EnterCpu(PVMCPU pVCpu);
1190
1191# ifdef VBOX_STRICT
1192VMMR0_INT_DECL(void) hmR0DumpRegs(PVMCPU pVCpu);
1193VMMR0_INT_DECL(void) hmR0DumpDescriptor(PCX86DESCHC pDesc, RTSEL Sel, const char *pszMsg);
1194# endif
1195
1196# ifdef VBOX_WITH_KERNEL_USING_XMM
1197DECLASM(int) hmR0VMXStartVMWrapXMM(RTHCUINT fResume, PCPUMCTX pCtx, PVMXVMCSCACHE pVmcsCache, PVM pVM,
1198 PVMCPU pVCpu, PFNHMVMXSTARTVM pfnStartVM);
1199DECLASM(int) hmR0SVMRunWrapXMM(RTHCPHYS pVmcbHostPhys, RTHCPHYS pVmcbPhys, PCPUMCTX pCtx, PVM pVM, PVMCPU pVCpu,
1200 PFNHMSVMVMRUN pfnVMRun);
1201# endif
1202DECLASM(void) hmR0MdsClear(void);
1203#endif /* IN_RING0 */
1204
1205VMM_INT_DECL(int) hmEmulateSvmMovTpr(PVMCPU pVCpu);
1206
1207VMM_INT_DECL(PVMXVMCSINFO) hmGetVmxActiveVmcsInfo(PVMCPU pVCpu);
1208
1209/** @} */
1210
1211RT_C_DECLS_END
1212
1213#endif /* !VMM_INCLUDED_SRC_include_HMInternal_h */
1214
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