VirtualBox

source: vbox/trunk/src/VBox/VMM/include/HMInternal.h@ 105673

Last change on this file since 105673 was 103053, checked in by vboxsync, 10 months ago

VMM: Nested VMX: bugref:10318 Fixed nested-guest (Hyper-V enabled Windows 10) BSODs triggered by split-lock #AC exceptions.
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File size: 57.7 KB
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1/* $Id: HMInternal.h 103053 2024-01-25 09:16:55Z vboxsync $ */
2/** @file
3 * HM - Internal header file.
4 */
5
6/*
7 * Copyright (C) 2006-2023 Oracle and/or its affiliates.
8 *
9 * This file is part of VirtualBox base platform packages, as
10 * available from https://www.virtualbox.org.
11 *
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License
14 * as published by the Free Software Foundation, in version 3 of the
15 * License.
16 *
17 * This program is distributed in the hope that it will be useful, but
18 * WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
20 * General Public License for more details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, see <https://www.gnu.org/licenses>.
24 *
25 * SPDX-License-Identifier: GPL-3.0-only
26 */
27
28#ifndef VMM_INCLUDED_SRC_include_HMInternal_h
29#define VMM_INCLUDED_SRC_include_HMInternal_h
30#ifndef RT_WITHOUT_PRAGMA_ONCE
31# pragma once
32#endif
33
34#include <VBox/cdefs.h>
35#include <VBox/types.h>
36#include <VBox/vmm/stam.h>
37#include <VBox/dis.h>
38#include <VBox/vmm/hm.h>
39#include <VBox/vmm/hm_vmx.h>
40#include <VBox/vmm/hm_svm.h>
41#include <VBox/vmm/pgm.h>
42#include <VBox/vmm/cpum.h>
43#include <VBox/vmm/trpm.h>
44#include <iprt/memobj.h>
45#include <iprt/cpuset.h>
46#include <iprt/mp.h>
47#include <iprt/avl.h>
48#include <iprt/string.h>
49
50#include "VMXInternal.h"
51#include "SVMInternal.h"
52
53#if HC_ARCH_BITS == 32
54# error "32-bit hosts are no longer supported. Go back to 6.0 or earlier!"
55#endif
56
57/** @def HM_PROFILE_EXIT_DISPATCH
58 * Enables profiling of the VM exit handler dispatching. */
59#if 0 || defined(DOXYGEN_RUNNING)
60# define HM_PROFILE_EXIT_DISPATCH
61#endif
62
63RT_C_DECLS_BEGIN
64
65
66/** @defgroup grp_hm_int Internal
67 * @ingroup grp_hm
68 * @internal
69 * @{
70 */
71
72/** Size for the EPT identity page table (1024 4 MB pages to cover the entire address space). */
73#define HM_EPT_IDENTITY_PG_TABLE_SIZE HOST_PAGE_SIZE
74/** Size of the TSS structure + 2 pages for the IO bitmap + end byte. */
75#define HM_VTX_TSS_SIZE (sizeof(VBOXTSS) + 2 * X86_PAGE_SIZE + 1)
76/** Total guest mapped memory needed. */
77#define HM_VTX_TOTAL_DEVHEAP_MEM (HM_EPT_IDENTITY_PG_TABLE_SIZE + HM_VTX_TSS_SIZE)
78
79
80/** @name Macros for enabling and disabling preemption.
81 * These are really just for hiding the RTTHREADPREEMPTSTATE and asserting that
82 * preemption has already been disabled when there is no context hook.
83 * @{ */
84#ifdef VBOX_STRICT
85# define HM_DISABLE_PREEMPT(a_pVCpu) \
86 RTTHREADPREEMPTSTATE PreemptStateInternal = RTTHREADPREEMPTSTATE_INITIALIZER; \
87 Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD) || VMMR0ThreadCtxHookIsEnabled((a_pVCpu))); \
88 RTThreadPreemptDisable(&PreemptStateInternal)
89#else
90# define HM_DISABLE_PREEMPT(a_pVCpu) \
91 RTTHREADPREEMPTSTATE PreemptStateInternal = RTTHREADPREEMPTSTATE_INITIALIZER; \
92 RTThreadPreemptDisable(&PreemptStateInternal)
93#endif /* VBOX_STRICT */
94#define HM_RESTORE_PREEMPT() do { RTThreadPreemptRestore(&PreemptStateInternal); } while(0)
95/** @} */
96
97
98/** @name HM saved state versions.
99 * @{
100 */
101#define HM_SAVED_STATE_VERSION HM_SAVED_STATE_VERSION_SVM_NESTED_HWVIRT
102#define HM_SAVED_STATE_VERSION_SVM_NESTED_HWVIRT 6
103#define HM_SAVED_STATE_VERSION_TPR_PATCHING 5
104#define HM_SAVED_STATE_VERSION_NO_TPR_PATCHING 4
105#define HM_SAVED_STATE_VERSION_2_0_X 3
106/** @} */
107
108
109/**
110 * HM physical (host) CPU information.
111 */
112typedef struct HMPHYSCPU
113{
114 /** The CPU ID. */
115 RTCPUID idCpu;
116 /** The VM_HSAVE_AREA (AMD-V) / VMXON region (Intel) memory backing. */
117 RTR0MEMOBJ hMemObj;
118 /** The physical address of the first page in hMemObj (it's a
119 * physcially contigous allocation if it spans multiple pages). */
120 RTHCPHYS HCPhysMemObj;
121 /** The address of the memory (for pfnEnable). */
122 void *pvMemObj;
123 /** Current ASID (AMD-V) / VPID (Intel). */
124 uint32_t uCurrentAsid;
125 /** TLB flush count. */
126 uint32_t cTlbFlushes;
127 /** Whether to flush each new ASID/VPID before use. */
128 bool fFlushAsidBeforeUse;
129 /** Configured for VT-x or AMD-V. */
130 bool fConfigured;
131 /** Set if the VBOX_HWVIRTEX_IGNORE_SVM_IN_USE hack is active. */
132 bool fIgnoreAMDVInUseError;
133 /** Whether CR4.VMXE was already enabled prior to us enabling it. */
134 bool fVmxeAlreadyEnabled;
135 /** In use by our code. (for power suspend) */
136 bool volatile fInUse;
137#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
138 /** Nested-guest union (put data common to SVM/VMX outside the union). */
139 union
140 {
141 /** Nested-guest SVM data. */
142 struct
143 {
144 /** The active nested-guest MSR permission bitmap memory backing. */
145 RTR0MEMOBJ hNstGstMsrpm;
146 /** The physical address of the first page in hNstGstMsrpm (physcially
147 * contiguous allocation). */
148 RTHCPHYS HCPhysNstGstMsrpm;
149 /** The address of the active nested-guest MSRPM. */
150 void *pvNstGstMsrpm;
151 } svm;
152 /** @todo Nested-VMX. */
153 } n;
154#endif
155} HMPHYSCPU;
156/** Pointer to HMPHYSCPU struct. */
157typedef HMPHYSCPU *PHMPHYSCPU;
158/** Pointer to a const HMPHYSCPU struct. */
159typedef const HMPHYSCPU *PCHMPHYSCPU;
160
161/**
162 * TPR-instruction type.
163 */
164typedef enum
165{
166 HMTPRINSTR_INVALID,
167 HMTPRINSTR_READ,
168 HMTPRINSTR_READ_SHR4,
169 HMTPRINSTR_WRITE_REG,
170 HMTPRINSTR_WRITE_IMM,
171 HMTPRINSTR_JUMP_REPLACEMENT,
172 /** The usual 32-bit paranoia. */
173 HMTPRINSTR_32BIT_HACK = 0x7fffffff
174} HMTPRINSTR;
175
176/**
177 * TPR patch information.
178 */
179typedef struct
180{
181 /** The key is the address of patched instruction. (32 bits GC ptr) */
182 AVLOU32NODECORE Core;
183 /** Original opcode. */
184 uint8_t aOpcode[16];
185 /** Instruction size. */
186 uint32_t cbOp;
187 /** Replacement opcode. */
188 uint8_t aNewOpcode[16];
189 /** Replacement instruction size. */
190 uint32_t cbNewOp;
191 /** Instruction type. */
192 HMTPRINSTR enmType;
193 /** Source operand. */
194 uint32_t uSrcOperand;
195 /** Destination operand. */
196 uint32_t uDstOperand;
197 /** Number of times the instruction caused a fault. */
198 uint32_t cFaults;
199 /** Patch address of the jump replacement. */
200 RTGCPTR32 pJumpTarget;
201} HMTPRPATCH;
202/** Pointer to HMTPRPATCH. */
203typedef HMTPRPATCH *PHMTPRPATCH;
204/** Pointer to a const HMTPRPATCH. */
205typedef const HMTPRPATCH *PCHMTPRPATCH;
206
207
208/**
209 * Makes a HMEXITSTAT::uKey value from a program counter and an exit code.
210 *
211 * @returns 64-bit key
212 * @param a_uPC The RIP + CS.BASE value of the exit.
213 * @param a_uExit The exit code.
214 * @todo Add CPL?
215 */
216#define HMEXITSTAT_MAKE_KEY(a_uPC, a_uExit) (((a_uPC) & UINT64_C(0x0000ffffffffffff)) | (uint64_t)(a_uExit) << 48)
217
218typedef struct HMEXITINFO
219{
220 /** See HMEXITSTAT_MAKE_KEY(). */
221 uint64_t uKey;
222 /** Number of recent hits (depreciates with time). */
223 uint32_t volatile cHits;
224 /** The age + lock. */
225 uint16_t volatile uAge;
226 /** Action or action table index. */
227 uint16_t iAction;
228} HMEXITINFO;
229AssertCompileSize(HMEXITINFO, 16); /* Lots of these guys, so don't add any unnecessary stuff! */
230
231typedef struct HMEXITHISTORY
232{
233 /** The exit timestamp. */
234 uint64_t uTscExit;
235 /** The index of the corresponding HMEXITINFO entry.
236 * UINT32_MAX if none (too many collisions, race, whatever). */
237 uint32_t iExitInfo;
238 /** Figure out later, needed for padding now. */
239 uint32_t uSomeClueOrSomething;
240} HMEXITHISTORY;
241
242/**
243 * Switcher function, HC to the special 64-bit RC.
244 *
245 * @param pVM The cross context VM structure.
246 * @param offCpumVCpu Offset from pVM->cpum to pVM->aCpus[idCpu].cpum.
247 * @returns Return code indicating the action to take.
248 */
249typedef DECLCALLBACKTYPE(int, FNHMSWITCHERHC,(PVM pVM, uint32_t offCpumVCpu));
250/** Pointer to switcher function. */
251typedef FNHMSWITCHERHC *PFNHMSWITCHERHC;
252
253
254/**
255 * HM VM Instance data.
256 * Changes to this must checked against the padding of the hm union in VM!
257 */
258typedef struct HM
259{
260 /** Set when the debug facility has breakpoints/events enabled that requires
261 * us to use the debug execution loop in ring-0. */
262 bool fUseDebugLoop;
263 /** Set when TPR patching is allowed. */
264 bool fTprPatchingAllowed;
265 /** Set when TPR patching is active. */
266 bool fTprPatchingActive;
267 /** Alignment padding. */
268 bool afAlignment1[5];
269
270 struct
271 {
272 /** Set by the ring-0 side of HM to indicate VMX is supported by the CPU. */
273 bool fSupported;
274 /** Set when we've enabled VMX. */
275 bool fEnabled;
276 /** The shift mask employed by the VMX-Preemption timer (set by ring-0). */
277 uint8_t cPreemptTimerShift;
278
279 /** @name Configuration (gets copied if problematic)
280 * @{ */
281 /** Set if Last Branch Record (LBR) is enabled. */
282 bool fLbrCfg;
283 /** Set if VT-x VPID is allowed. */
284 bool fAllowVpid;
285 /** Set if unrestricted guest execution is in use (real and protected mode
286 * without paging). */
287 bool fUnrestrictedGuestCfg;
288 /** Set if the preemption timer should be used if available. Ring-0
289 * quietly clears this if the hardware doesn't support the preemption timer. */
290 bool fUsePreemptTimerCfg;
291 /** Whether to always intercept MOV DRx: 1 (always), 0 (default), -1 (lazy).
292 * In the default case it is only always intercepted when setting DR6 to 0 on
293 * the host results in a value different from X86_DR6_RA1_MASK. */
294 int8_t fAlwaysInterceptMovDRxCfg;
295 /** @} */
296
297 /** Pause-loop exiting (PLE) gap in ticks. */
298 uint32_t cPleGapTicks;
299 /** Pause-loop exiting (PLE) window in ticks. */
300 uint32_t cPleWindowTicks;
301
302 /** Virtual address of the TSS page used for real mode emulation. */
303 R3PTRTYPE(PVBOXTSS) pRealModeTSS;
304 /** Virtual address of the identity page table used for real mode and protected
305 * mode without paging emulation in EPT mode. */
306 R3PTRTYPE(PX86PD) pNonPagingModeEPTPageTable;
307 } vmx;
308
309 struct
310 {
311 /** Set by the ring-0 side of HM to indicate SVM is supported by the CPU. */
312 bool fSupported;
313 /** Set when we've enabled SVM. */
314 bool fEnabled;
315 /** Set when the hack to ignore VERR_SVM_IN_USE is active.
316 * @todo Safe? */
317 bool fIgnoreInUseError;
318 /** Whether to use virtualized VMSAVE/VMLOAD feature. */
319 bool fVirtVmsaveVmload;
320 /** Whether to use virtual GIF feature. */
321 bool fVGif;
322 /** Whether to use LBR virtualization feature. */
323 bool fLbrVirt;
324 bool afAlignment1[2];
325
326 /** Pause filter counter. */
327 uint16_t cPauseFilter;
328 /** Pause filter treshold in ticks. */
329 uint16_t cPauseFilterThresholdTicks;
330 uint32_t u32Alignment2;
331 } svm;
332
333 /** AVL tree with all patches (active or disabled) sorted by guest instruction address.
334 * @todo For @bugref{9217} this AVL tree must be eliminated and instead
335 * sort aPatches by address and do a safe binary search on it. */
336 AVLOU32TREE PatchTree;
337 uint32_t cPatches;
338 HMTPRPATCH aPatches[64];
339
340 /** Guest allocated memory for patching purposes. */
341 RTGCPTR pGuestPatchMem;
342 /** Current free pointer inside the patch block. */
343 RTGCPTR pFreeGuestPatchMem;
344 /** Size of the guest patch memory block. */
345 uint32_t cbGuestPatchMem;
346 uint32_t u32Alignment2;
347
348 /** For ring-3 use only. */
349 struct
350 {
351 /** Last recorded error code during HM ring-0 init. */
352 int32_t rcInit;
353 uint32_t u32Alignment3;
354
355 /** Maximum ASID allowed.
356 * This is mainly for the release log. */
357 uint32_t uMaxAsid;
358 /** World switcher flags (HM_WSF_XXX) for the release log. */
359 uint32_t fWorldSwitcher;
360
361 struct
362 {
363 /** Set if VPID is supported (ring-3 copy). */
364 bool fVpid;
365 /** Whether the CPU supports VMCS fields for swapping EFER (set by ring-0 VMX
366 * init, for logging). */
367 bool fSupportsVmcsEfer;
368 /** Whether to use VMCS shadowing. */
369 bool fUseVmcsShadowing;
370 /** Whether MOV DRx is always intercepted or not (set by ring-0 VMX init, for
371 * logging). */
372 bool fAlwaysInterceptMovDRx;
373
374 /** Host CR0 value (set by ring-0 VMX init, for logging). */
375 uint64_t u64HostCr0;
376 /** Host CR4 value (set by ring-0 VMX init, for logging). */
377 uint64_t u64HostCr4;
378 /** Host SMM monitor control (set by ring-0 VMX init, for logging). */
379 uint64_t u64HostSmmMonitorCtl;
380 /** Host EFER value (set by ring-0 VMX init, for logging and guest NX). */
381 uint64_t u64HostMsrEfer;
382 /** Host IA32_FEATURE_CONTROL MSR (set by ring-0 VMX init, for logging). */
383 uint64_t u64HostFeatCtrl;
384 /** Host IA32_CORE_CAPABILITIES MSR (set by ring-0 VMX init, for logging). */
385 uint64_t u64HostCoreCap;
386 /** Host MSR_MEMORY_CTRL MSR (set by ring-0 VMX init, for logging). */
387 uint64_t u64HostMemoryCtrl;
388
389 /** Host zero'ed DR6 value (set by ring-0 VMX init, for logging). */
390 uint64_t u64HostDr6Zeroed;
391
392 /** The first valid host LBR branch-from-IP stack range. */
393 uint32_t idLbrFromIpMsrFirst;
394 /** The last valid host LBR branch-from-IP stack range. */
395 uint32_t idLbrFromIpMsrLast;
396
397 /** The first valid host LBR branch-to-IP stack range. */
398 uint32_t idLbrToIpMsrFirst;
399 /** The last valid host LBR branch-to-IP stack range. */
400 uint32_t idLbrToIpMsrLast;
401
402 /** Host-physical address for a failing VMXON instruction (for diagnostics, ring-3). */
403 RTHCPHYS HCPhysVmxEnableError;
404 /** VMX MSR values (only for ring-3 consumption). */
405 VMXMSRS Msrs;
406
407 /** Tagged-TLB flush type (only for ring-3 consumption). */
408 VMXTLBFLUSHTYPE enmTlbFlushType;
409 /** Flush type to use for INVEPT (only for ring-3 consumption). */
410 VMXTLBFLUSHEPT enmTlbFlushEpt;
411 /** Flush type to use for INVVPID (only for ring-3 consumption). */
412 VMXTLBFLUSHVPID enmTlbFlushVpid;
413 } vmx;
414
415 struct
416 {
417 /** SVM revision. */
418 uint32_t u32Rev;
419 /** SVM feature bits from cpuid 0x8000000a, ring-3 copy. */
420 uint32_t fFeatures;
421 /** HWCR MSR (for diagnostics). */
422 uint64_t u64MsrHwcr;
423 } svm;
424 } ForR3;
425
426 /** @name Configuration not used (much) after VM setup
427 * @{ */
428 /** The maximum number of resumes loops allowed in ring-0 (safety precaution).
429 * This number is set much higher when RTThreadPreemptIsPending is reliable. */
430 uint32_t cMaxResumeLoopsCfg;
431 /** Set if nested paging is enabled.
432 * Config value that is copied to HMR0PERVM::fNestedPaging on setup. */
433 bool fNestedPagingCfg;
434 /** Set if large pages are enabled (requires nested paging).
435 * Config only, passed on the PGM where it really belongs.
436 * @todo move to PGM */
437 bool fLargePages;
438 /** Set if we can support 64-bit guests or not.
439 * Config value that is copied to HMR0PERVM::fAllow64BitGuests on setup. */
440 bool fAllow64BitGuestsCfg;
441 /** Set when we initialize VT-x or AMD-V once for all CPUs. */
442 bool fGlobalInit;
443 /** Set if hardware APIC virtualization is enabled.
444 * @todo Not really used by HM, move to APIC where it's actually used. */
445 bool fVirtApicRegs;
446 /** Set if posted interrupt processing is enabled.
447 * @todo Not really used by HM, move to APIC where it's actually used. */
448 bool fPostedIntrs;
449 /** VM needs workaround for missing TLB flush in OS/2, see ticketref:20625.
450 * @note Currently only heeded by AMD-V. */
451 bool fMissingOS2TlbFlushWorkaround;
452 /** @} */
453
454 /** @name Processed into HMR0PERVCPU::fWorldSwitcher by ring-0 on VM init.
455 * @{ */
456 /** Set if indirect branch prediction barrier on VM exit. */
457 bool fIbpbOnVmExit;
458 /** Set if indirect branch prediction barrier on VM entry. */
459 bool fIbpbOnVmEntry;
460 /** Set if level 1 data cache should be flushed on VM entry. */
461 bool fL1dFlushOnVmEntry;
462 /** Set if level 1 data cache should be flushed on EMT scheduling. */
463 bool fL1dFlushOnSched;
464 /** Set if MDS related buffers should be cleared on VM entry. */
465 bool fMdsClearOnVmEntry;
466 /** Set if MDS related buffers should be cleared on EMT scheduling. */
467 bool fMdsClearOnSched;
468 /** Set if host manages speculation control settings.
469 * @todo doesn't do anything ... */
470 bool fSpecCtrlByHost;
471 /** @} */
472
473 /** Set when we've finalized the VMX / SVM initialization in ring-3
474 * (hmR3InitFinalizeR0Intel / hmR3InitFinalizeR0Amd). */
475 bool fInitialized;
476
477 bool afAlignment2[5];
478
479 STAMCOUNTER StatTprPatchSuccess;
480 STAMCOUNTER StatTprPatchFailure;
481 STAMCOUNTER StatTprReplaceSuccessCr8;
482 STAMCOUNTER StatTprReplaceSuccessVmc;
483 STAMCOUNTER StatTprReplaceFailure;
484} HM;
485/** Pointer to HM VM instance data. */
486typedef HM *PHM;
487AssertCompileMemberAlignment(HM, StatTprPatchSuccess, 8);
488AssertCompileMemberAlignment(HM, vmx, 8);
489AssertCompileMemberAlignment(HM, svm, 8);
490AssertCompileMemberAlignment(HM, StatTprPatchSuccess, 8);
491AssertCompile(RTASSERT_OFFSET_OF(HM, PatchTree) <= 64); /* First cache line has the essentials for both VT-x and SVM operation. */
492
493
494/**
495 * Per-VM ring-0 instance data for HM.
496 */
497typedef struct HMR0PERVM
498{
499 /** The maximum number of resumes loops allowed in ring-0 (safety precaution).
500 * This number is set much higher when RTThreadPreemptIsPending is reliable. */
501 uint32_t cMaxResumeLoops;
502
503 /** Set if nested paging is enabled. */
504 bool fNestedPaging;
505 /** Set if we can support 64-bit guests or not. */
506 bool fAllow64BitGuests;
507 bool afAlignment1[1];
508
509 /** AMD-V specific data. */
510 struct HMR0SVMVM
511 {
512 /** Set if erratum 170 affects the AMD cpu. */
513 bool fAlwaysFlushTLB;
514 } svm;
515
516 /** VT-x specific data. */
517 struct HMR0VMXVM
518 {
519 /** Set if unrestricted guest execution is in use (real and protected mode
520 * without paging). */
521 bool fUnrestrictedGuest;
522 /** Set if the preemption timer is in use. */
523 bool fUsePreemptTimer;
524 /** Whether to use VMCS shadowing. */
525 bool fUseVmcsShadowing;
526 /** Set if Last Branch Record (LBR) is enabled. */
527 bool fLbr;
528 /** Set always intercept MOV DRx. */
529 bool fAlwaysInterceptMovDRx;
530 bool afAlignment2[2];
531
532 /** Set if VPID is supported (copy in HM::vmx::fVpidForRing3). */
533 bool fVpid;
534 /** Tagged-TLB flush type. */
535 VMXTLBFLUSHTYPE enmTlbFlushType;
536 /** Flush type to use for INVEPT. */
537 VMXTLBFLUSHEPT enmTlbFlushEpt;
538 /** Flush type to use for INVVPID. */
539 VMXTLBFLUSHVPID enmTlbFlushVpid;
540
541 /** The host LBR TOS (top-of-stack) MSR id. */
542 uint32_t idLbrTosMsr;
543
544 /** The first valid host LBR branch-from-IP stack range. */
545 uint32_t idLbrFromIpMsrFirst;
546 /** The last valid host LBR branch-from-IP stack range. */
547 uint32_t idLbrFromIpMsrLast;
548
549 /** The first valid host LBR branch-to-IP stack range. */
550 uint32_t idLbrToIpMsrFirst;
551 /** The last valid host LBR branch-to-IP stack range. */
552 uint32_t idLbrToIpMsrLast;
553
554 /** Pointer to the VMREAD bitmap. */
555 R0PTRTYPE(void *) pvVmreadBitmap;
556 /** Pointer to the VMWRITE bitmap. */
557 R0PTRTYPE(void *) pvVmwriteBitmap;
558
559 /** Pointer to the shadow VMCS read-only fields array. */
560 R0PTRTYPE(uint32_t *) paShadowVmcsRoFields;
561 /** Pointer to the shadow VMCS read/write fields array. */
562 R0PTRTYPE(uint32_t *) paShadowVmcsFields;
563 /** Number of elements in the shadow VMCS read-only fields array. */
564 uint32_t cShadowVmcsRoFields;
565 /** Number of elements in the shadow VMCS read-write fields array. */
566 uint32_t cShadowVmcsFields;
567
568 /** Host-physical address of the APIC-access page. */
569 RTHCPHYS HCPhysApicAccess;
570 /** Host-physical address of the VMREAD bitmap. */
571 RTHCPHYS HCPhysVmreadBitmap;
572 /** Host-physical address of the VMWRITE bitmap. */
573 RTHCPHYS HCPhysVmwriteBitmap;
574
575#ifdef VBOX_WITH_CRASHDUMP_MAGIC
576 /** Host-physical address of the crash-dump scratch area. */
577 RTHCPHYS HCPhysScratch;
578 /** Pointer to the crash-dump scratch bitmap. */
579 R0PTRTYPE(uint8_t *) pbScratch;
580#endif
581
582 /** Ring-0 memory object for per-VM VMX structures. */
583 RTR0MEMOBJ hMemObj;
584 /** Virtual address of the APIC-access page (not used). */
585 R0PTRTYPE(uint8_t *) pbApicAccess;
586 } vmx;
587} HMR0PERVM;
588/** Pointer to HM's per-VM ring-0 instance data. */
589typedef HMR0PERVM *PHMR0PERVM;
590
591
592/** @addtogroup grp_hm_int_svm SVM Internal
593 * @{ */
594/** SVM VMRun function, see SVMR0VMRun(). */
595typedef DECLCALLBACKTYPE(int, FNHMSVMVMRUN,(PVMCC pVM, PVMCPUCC pVCpu, RTHCPHYS HCPhysVMCB));
596/** Pointer to a SVM VMRun function. */
597typedef R0PTRTYPE(FNHMSVMVMRUN *) PFNHMSVMVMRUN;
598
599/**
600 * SVM nested-guest VMCB cache.
601 *
602 * Contains VMCB fields from the nested-guest VMCB before they're modified by
603 * SVM R0 code for hardware-assisted SVM execution of a nested-guest.
604 *
605 * A VMCB field needs to be cached when it needs to be modified for execution using
606 * hardware-assisted SVM and any of the following are true:
607 * - If the original field needs to be inspected during execution of the
608 * nested-guest or \#VMEXIT processing.
609 * - If the field is written back to memory on \#VMEXIT by the physical CPU.
610 *
611 * A VMCB field needs to be restored only when the field is written back to
612 * memory on \#VMEXIT by the physical CPU and thus would be visible to the
613 * guest.
614 *
615 * @remarks Please update hmR3InfoSvmNstGstVmcbCache() when changes are made to
616 * this structure.
617 */
618typedef struct SVMNESTEDVMCBCACHE
619{
620 /** Cache of CRX read intercepts. */
621 uint16_t u16InterceptRdCRx;
622 /** Cache of CRX write intercepts. */
623 uint16_t u16InterceptWrCRx;
624 /** Cache of DRX read intercepts. */
625 uint16_t u16InterceptRdDRx;
626 /** Cache of DRX write intercepts. */
627 uint16_t u16InterceptWrDRx;
628
629 /** Cache of the pause-filter threshold. */
630 uint16_t u16PauseFilterThreshold;
631 /** Cache of the pause-filter count. */
632 uint16_t u16PauseFilterCount;
633
634 /** Cache of exception intercepts. */
635 uint32_t u32InterceptXcpt;
636 /** Cache of control intercepts. */
637 uint64_t u64InterceptCtrl;
638
639 /** Cache of the TSC offset. */
640 uint64_t u64TSCOffset;
641
642 /** Cache of V_INTR_MASKING bit. */
643 bool fVIntrMasking;
644 /** Cache of the nested-paging bit. */
645 bool fNestedPaging;
646 /** Cache of the LBR virtualization bit. */
647 bool fLbrVirt;
648 /** Whether the VMCB is cached by HM. */
649 bool fCacheValid;
650 /** Alignment. */
651 bool afPadding0[4];
652} SVMNESTEDVMCBCACHE;
653/** Pointer to the SVMNESTEDVMCBCACHE structure. */
654typedef SVMNESTEDVMCBCACHE *PSVMNESTEDVMCBCACHE;
655/** Pointer to a const SVMNESTEDVMCBCACHE structure. */
656typedef const SVMNESTEDVMCBCACHE *PCSVMNESTEDVMCBCACHE;
657AssertCompileSizeAlignment(SVMNESTEDVMCBCACHE, 8);
658
659/** @} */
660
661
662/** @addtogroup grp_hm_int_vmx VMX Internal
663 * @{ */
664
665/** @name Host-state restoration flags.
666 * @note If you change these values don't forget to update the assembly
667 * defines as well!
668 * @{
669 */
670#define VMX_RESTORE_HOST_SEL_DS RT_BIT(0)
671#define VMX_RESTORE_HOST_SEL_ES RT_BIT(1)
672#define VMX_RESTORE_HOST_SEL_FS RT_BIT(2)
673#define VMX_RESTORE_HOST_SEL_GS RT_BIT(3)
674#define VMX_RESTORE_HOST_SEL_TR RT_BIT(4)
675#define VMX_RESTORE_HOST_GDTR RT_BIT(5)
676#define VMX_RESTORE_HOST_IDTR RT_BIT(6)
677#define VMX_RESTORE_HOST_GDT_READ_ONLY RT_BIT(7)
678#define VMX_RESTORE_HOST_GDT_NEED_WRITABLE RT_BIT(8)
679#define VMX_RESTORE_HOST_CAN_USE_WRFSBASE_AND_WRGSBASE RT_BIT(9)
680/**
681 * This _must_ be the top most bit, so that we can easily check that it and
682 * something else is set w/o having to do two checks like this:
683 * @code
684 * if ( (pVCpu->hm.s.vmx.fRestoreHostFlags & VMX_RESTORE_HOST_REQUIRED)
685 * && (pVCpu->hm.s.vmx.fRestoreHostFlags & ~VMX_RESTORE_HOST_REQUIRED))
686 * @endcode
687 * Instead we can then do:
688 * @code
689 * if (pVCpu->hm.s.vmx.fRestoreHostFlags > VMX_RESTORE_HOST_REQUIRED)
690 * @endcode
691 */
692#define VMX_RESTORE_HOST_REQUIRED RT_BIT(10)
693/** @} */
694
695/**
696 * Host-state restoration structure.
697 *
698 * This holds host-state fields that require manual restoration.
699 * Assembly version found in HMInternal.mac (should be automatically verified).
700 */
701typedef struct VMXRESTOREHOST
702{
703 RTSEL uHostSelDS; /**< 0x00 */
704 RTSEL uHostSelES; /**< 0x02 */
705 RTSEL uHostSelFS; /**< 0x04 */
706 X86XDTR64 HostGdtr; /**< 0x06 - should be aligned by its 64-bit member. */
707 RTSEL uHostSelGS; /**< 0x10 */
708 RTSEL uHostSelTR; /**< 0x12 */
709 RTSEL uHostSelSS; /**< 0x14 - not restored, just for fetching */
710 X86XDTR64 HostGdtrRw; /**< 0x16 - should be aligned by its 64-bit member. */
711 RTSEL uHostSelCS; /**< 0x20 - not restored, just for fetching */
712 uint8_t abPadding1[4]; /**< 0x22 */
713 X86XDTR64 HostIdtr; /**< 0x26 - should be aligned by its 64-bit member. */
714 uint64_t uHostFSBase; /**< 0x30 */
715 uint64_t uHostGSBase; /**< 0x38 */
716} VMXRESTOREHOST;
717/** Pointer to VMXRESTOREHOST. */
718typedef VMXRESTOREHOST *PVMXRESTOREHOST;
719AssertCompileSize(X86XDTR64, 10);
720AssertCompileMemberOffset(VMXRESTOREHOST, HostGdtr.uAddr, 0x08);
721AssertCompileMemberOffset(VMXRESTOREHOST, HostGdtrRw.uAddr, 0x18);
722AssertCompileMemberOffset(VMXRESTOREHOST, HostIdtr.uAddr, 0x28);
723AssertCompileMemberOffset(VMXRESTOREHOST, uHostFSBase, 0x30);
724AssertCompileSize(VMXRESTOREHOST, 64);
725AssertCompileSizeAlignment(VMXRESTOREHOST, 8);
726
727/**
728 * VMX StartVM function.
729 *
730 * @returns VBox status code (no informational stuff).
731 * @param pVmcsInfo Pointer to the VMCS info (for cached host RIP and RSP).
732 * @param pVCpu Pointer to the cross context per-CPU structure.
733 * @param fResume Whether to use VMRESUME (true) or VMLAUNCH (false).
734 */
735typedef DECLCALLBACKTYPE(int, FNHMVMXSTARTVM,(PVMXVMCSINFO pVmcsInfo, PVMCPUCC pVCpu, bool fResume));
736/** Pointer to a VMX StartVM function. */
737typedef R0PTRTYPE(FNHMVMXSTARTVM *) PFNHMVMXSTARTVM;
738/** @} */
739
740
741/**
742 * HM VMCPU Instance data.
743 *
744 * Note! If you change members of this struct, make sure to check if the
745 * assembly counterpart in HMInternal.mac needs to be updated as well.
746 *
747 * Note! The members here are ordered and aligned based on estimated frequency of
748 * usage and grouped to fit within a cache line in hot code paths. Even subtle
749 * changes here have a noticeable effect in the bootsector benchmarks. Modify with
750 * care.
751 */
752typedef struct HMCPU
753{
754 /** Set when the TLB has been checked until we return from the world switch. */
755 bool volatile fCheckedTLBFlush;
756 /** Set when we're using VT-x or AMD-V at that moment.
757 * @todo r=bird: Misleading description. For AMD-V this will be set the first
758 * time HMCanExecuteGuest() is called and only cleared again by
759 * HMR3ResetCpu(). For VT-x it will be set by HMCanExecuteGuest when we
760 * can execute something in VT-x mode, and cleared if we cannot.
761 *
762 * The field is much more about recording the last HMCanExecuteGuest
763 * return value than anything about any "moment". */
764 bool fActive;
765
766 /** Whether we should use the debug loop because of single stepping or special
767 * debug breakpoints / events are armed. */
768 bool fUseDebugLoop;
769
770 /** Whether \#UD needs to be intercepted (required by certain GIM providers). */
771 bool fGIMTrapXcptUD;
772 /** Whether \#GP needs to be intercepted for mesa driver workaround. */
773 bool fTrapXcptGpForLovelyMesaDrv;
774 /** Whether we're executing a single instruction. */
775 bool fSingleInstruction;
776 /** Whether \#DE needs to be intercepted (may be required by GCM). */
777 bool fGCMTrapXcptDE;
778
779 bool afAlignment0[1];
780
781 /** An additional error code used for some gurus. */
782 uint32_t u32HMError;
783 /** The last exit-to-ring-3 reason. */
784 int32_t rcLastExitToR3;
785 /** CPU-context changed flags (see HM_CHANGED_xxx). */
786 uint64_t fCtxChanged;
787
788 /** VT-x data. */
789 struct HMCPUVMX
790 {
791 /** @name Guest information.
792 * @{ */
793 /** Guest VMCS information shared with ring-3. */
794 VMXVMCSINFOSHARED VmcsInfo;
795 /** Nested-guest VMCS information shared with ring-3. */
796 VMXVMCSINFOSHARED VmcsInfoNstGst;
797 /** Whether the nested-guest VMCS was the last current VMCS (shadow copy for ring-3).
798 * @see HMR0PERVCPU::vmx.fSwitchedToNstGstVmcs */
799 bool fSwitchedToNstGstVmcsCopyForRing3;
800 /** Whether the static guest VMCS controls has been merged with the
801 * nested-guest VMCS controls. */
802 bool fMergedNstGstCtls;
803 /** Whether the nested-guest VMCS has been copied to the shadow VMCS. */
804 bool fCopiedNstGstToShadowVmcs;
805 /** Whether flushing the TLB is required due to switching to/from the
806 * nested-guest. */
807 bool fSwitchedNstGstFlushTlb;
808 /** Alignment. */
809 bool afAlignment0[4];
810 /** Cached guest APIC-base MSR for identifying when to map the APIC-access page. */
811 uint64_t u64GstMsrApicBase;
812 /** @} */
813
814 /** @name Error reporting and diagnostics.
815 * @{ */
816 /** VT-x error-reporting (mainly for ring-3 propagation). */
817 struct
818 {
819 RTCPUID idCurrentCpu;
820 RTCPUID idEnteredCpu;
821 RTHCPHYS HCPhysCurrentVmcs;
822 uint32_t u32VmcsRev;
823 uint32_t u32InstrError;
824 uint32_t u32ExitReason;
825 uint32_t u32GuestIntrState;
826 } LastError;
827 /** @} */
828 } vmx;
829
830 /** SVM data. */
831 struct HMCPUSVM
832 {
833 /** Whether to emulate long mode support for sysenter/sysexit like intel CPUs
834 * does. This means intercepting \#UD to emulate the instructions in
835 * long-mode and to intercept reads and writes to the SYSENTER MSRs in order to
836 * preserve the upper 32 bits written to them (AMD will ignore and discard). */
837 bool fEmulateLongModeSysEnterExit;
838 uint8_t au8Alignment0[7];
839
840 /** Cache of the nested-guest's VMCB fields that we modify in order to run the
841 * nested-guest using AMD-V. This will be restored on \#VMEXIT. */
842 SVMNESTEDVMCBCACHE NstGstVmcbCache;
843 } svm;
844
845 /** Event injection state. */
846 HMEVENT Event;
847
848 /** Current shadow paging mode for updating CR4.
849 * @todo move later (@bugref{9217}). */
850 PGMMODE enmShadowMode;
851 uint32_t u32TemporaryPadding;
852
853 /** The PAE PDPEs used with Nested Paging (only valid when
854 * VMCPU_FF_HM_UPDATE_PAE_PDPES is set). */
855 X86PDPE aPdpes[4];
856
857 /* These two comes because they are accessed from assembly and we don't
858 want to detail all the stats in the assembly version of this structure. */
859 STAMCOUNTER StatVmxWriteHostRip;
860 STAMCOUNTER StatVmxWriteHostRsp;
861 STAMCOUNTER StatVmxVmLaunch;
862 STAMCOUNTER StatVmxVmResume;
863
864 STAMPROFILEADV StatEntry;
865 STAMPROFILEADV StatPreExit;
866 STAMPROFILEADV StatExitHandling;
867 STAMPROFILEADV StatExitIO;
868 STAMPROFILEADV StatExitMovCRx;
869 STAMPROFILEADV StatExitXcptNmi;
870 STAMPROFILEADV StatExitVmentry;
871 STAMPROFILEADV StatImportGuestState;
872 STAMPROFILEADV StatExportGuestState;
873 STAMPROFILEADV StatLoadGuestFpuState;
874 STAMPROFILEADV StatInGC;
875 STAMPROFILEADV StatPoke;
876 STAMPROFILEADV StatSpinPoke;
877 STAMPROFILEADV StatSpinPokeFailed;
878
879 STAMCOUNTER StatInjectInterrupt;
880 STAMCOUNTER StatInjectXcpt;
881 STAMCOUNTER StatInjectReflect;
882 STAMCOUNTER StatInjectConvertDF;
883 STAMCOUNTER StatInjectInterpret;
884 STAMCOUNTER StatInjectReflectNPF;
885
886 STAMCOUNTER StatImportGuestStateFallback;
887 STAMCOUNTER StatReadToTransientFallback;
888
889 STAMCOUNTER StatExitAll;
890 STAMCOUNTER StatDebugExitAll;
891 STAMCOUNTER StatNestedExitAll;
892 STAMCOUNTER StatExitShadowNM;
893 STAMCOUNTER StatExitGuestNM;
894 STAMCOUNTER StatExitShadowPF; /**< Misleading, currently used for MMIO \#PFs as well. */
895 STAMCOUNTER StatExitShadowPFEM;
896 STAMCOUNTER StatExitGuestPF;
897 STAMCOUNTER StatExitGuestUD;
898 STAMCOUNTER StatExitGuestSS;
899 STAMCOUNTER StatExitGuestNP;
900 STAMCOUNTER StatExitGuestTS;
901 STAMCOUNTER StatExitGuestOF;
902 STAMCOUNTER StatExitGuestGP;
903 STAMCOUNTER StatExitGuestDE;
904 STAMCOUNTER StatExitGuestDF;
905 STAMCOUNTER StatExitGuestBR;
906 STAMCOUNTER StatExitGuestAC;
907 STAMCOUNTER StatExitGuestACSplitLock;
908 STAMCOUNTER StatExitGuestDB;
909 STAMCOUNTER StatExitGuestMF;
910 STAMCOUNTER StatExitGuestBP;
911 STAMCOUNTER StatExitGuestXF;
912 STAMCOUNTER StatExitGuestXcpUnk;
913 STAMCOUNTER StatExitDRxWrite;
914 STAMCOUNTER StatExitDRxRead;
915 STAMCOUNTER StatExitCR0Read;
916 STAMCOUNTER StatExitCR2Read;
917 STAMCOUNTER StatExitCR3Read;
918 STAMCOUNTER StatExitCR4Read;
919 STAMCOUNTER StatExitCR8Read;
920 STAMCOUNTER StatExitCR0Write;
921 STAMCOUNTER StatExitCR2Write;
922 STAMCOUNTER StatExitCR3Write;
923 STAMCOUNTER StatExitCR4Write;
924 STAMCOUNTER StatExitCR8Write;
925 STAMCOUNTER StatExitRdmsr;
926 STAMCOUNTER StatExitWrmsr;
927 STAMCOUNTER StatExitClts;
928 STAMCOUNTER StatExitXdtrAccess;
929 STAMCOUNTER StatExitLmsw;
930 STAMCOUNTER StatExitIOWrite;
931 STAMCOUNTER StatExitIORead;
932 STAMCOUNTER StatExitIOStringWrite;
933 STAMCOUNTER StatExitIOStringRead;
934 STAMCOUNTER StatExitIntWindow;
935 STAMCOUNTER StatExitExtInt;
936 STAMCOUNTER StatExitHostNmiInGC;
937 STAMCOUNTER StatExitHostNmiInGCIpi;
938 STAMCOUNTER StatExitPreemptTimer;
939 STAMCOUNTER StatExitTprBelowThreshold;
940 STAMCOUNTER StatExitTaskSwitch;
941 STAMCOUNTER StatExitApicAccess;
942 STAMCOUNTER StatExitReasonNpf;
943
944 STAMCOUNTER StatNestedExitReasonNpf;
945 STAMCOUNTER StatNestedExitACSplitLock;
946
947 STAMCOUNTER StatFlushPage;
948 STAMCOUNTER StatFlushPageManual;
949 STAMCOUNTER StatFlushPhysPageManual;
950 STAMCOUNTER StatFlushTlb;
951 STAMCOUNTER StatFlushTlbNstGst;
952 STAMCOUNTER StatFlushTlbManual;
953 STAMCOUNTER StatFlushTlbWorldSwitch;
954 STAMCOUNTER StatNoFlushTlbWorldSwitch;
955 STAMCOUNTER StatFlushEntire;
956 STAMCOUNTER StatFlushAsid;
957 STAMCOUNTER StatFlushNestedPaging;
958 STAMCOUNTER StatFlushTlbInvlpgVirt;
959 STAMCOUNTER StatFlushTlbInvlpgPhys;
960 STAMCOUNTER StatTlbShootdown;
961 STAMCOUNTER StatTlbShootdownFlush;
962
963 STAMCOUNTER StatSwitchPendingHostIrq;
964 STAMCOUNTER StatSwitchTprMaskedIrq;
965 STAMCOUNTER StatSwitchGuestIrq;
966 STAMCOUNTER StatSwitchHmToR3FF;
967 STAMCOUNTER StatSwitchVmReq;
968 STAMCOUNTER StatSwitchPgmPoolFlush;
969 STAMCOUNTER StatSwitchDma;
970 STAMCOUNTER StatSwitchExitToR3;
971 STAMCOUNTER StatSwitchLongJmpToR3;
972 STAMCOUNTER StatSwitchMaxResumeLoops;
973 STAMCOUNTER StatSwitchHltToR3;
974 STAMCOUNTER StatSwitchApicAccessToR3;
975 STAMCOUNTER StatSwitchPreempt;
976 STAMCOUNTER StatSwitchNstGstVmexit;
977
978 STAMCOUNTER StatTscParavirt;
979 STAMCOUNTER StatTscOffset;
980 STAMCOUNTER StatTscIntercept;
981
982 STAMCOUNTER StatDRxArmed;
983 STAMCOUNTER StatDRxContextSwitch;
984 STAMCOUNTER StatDRxIoCheck;
985
986 STAMCOUNTER StatExportMinimal;
987 STAMCOUNTER StatExportFull;
988 STAMCOUNTER StatLoadGuestFpu;
989 STAMCOUNTER StatExportHostState;
990
991 STAMCOUNTER StatVmxCheckBadRmSelBase;
992 STAMCOUNTER StatVmxCheckBadRmSelLimit;
993 STAMCOUNTER StatVmxCheckBadRmSelAttr;
994 STAMCOUNTER StatVmxCheckBadV86SelBase;
995 STAMCOUNTER StatVmxCheckBadV86SelLimit;
996 STAMCOUNTER StatVmxCheckBadV86SelAttr;
997 STAMCOUNTER StatVmxCheckRmOk;
998 STAMCOUNTER StatVmxCheckBadSel;
999 STAMCOUNTER StatVmxCheckBadRpl;
1000 STAMCOUNTER StatVmxCheckPmOk;
1001 STAMCOUNTER StatVmxCheck1;
1002 STAMCOUNTER StatVmxCheck2;
1003 STAMCOUNTER StatVmxCheckDisabled;
1004 STAMCOUNTER StatVmxCheckOk;
1005
1006 STAMCOUNTER StatVmxPreemptionRecalcingDeadline;
1007 STAMCOUNTER StatVmxPreemptionRecalcingDeadlineExpired;
1008 STAMCOUNTER StatVmxPreemptionReusingDeadline;
1009 STAMCOUNTER StatVmxPreemptionReusingDeadlineExpired;
1010
1011#ifdef VBOX_WITH_STATISTICS
1012 STAMCOUNTER aStatExitReason[MAX_EXITREASON_STAT];
1013 STAMCOUNTER aStatNestedExitReason[MAX_EXITREASON_STAT];
1014 STAMCOUNTER aStatInjectedIrqs[256];
1015 STAMCOUNTER aStatInjectedXcpts[X86_XCPT_LAST + 1];
1016#endif
1017#ifdef HM_PROFILE_EXIT_DISPATCH
1018 STAMPROFILEADV StatExitDispatch;
1019#endif
1020} HMCPU;
1021/** Pointer to HM VMCPU instance data. */
1022typedef HMCPU *PHMCPU;
1023AssertCompileMemberAlignment(HMCPU, fCheckedTLBFlush, 4);
1024AssertCompileMemberAlignment(HMCPU, fCtxChanged, 8);
1025AssertCompileMemberAlignment(HMCPU, vmx, 8);
1026AssertCompileMemberAlignment(HMCPU, vmx.VmcsInfo, 8);
1027AssertCompileMemberAlignment(HMCPU, vmx.VmcsInfoNstGst, 8);
1028AssertCompileMemberAlignment(HMCPU, svm, 8);
1029AssertCompileMemberAlignment(HMCPU, Event, 8);
1030
1031
1032/**
1033 * HM per-VCpu ring-0 only instance data.
1034 */
1035typedef struct HMR0PERVCPU
1036{
1037 /** World switch exit counter. */
1038 uint32_t volatile cWorldSwitchExits;
1039 /** TLB flush count. */
1040 uint32_t cTlbFlushes;
1041 /** The last CPU we were executing code on (NIL_RTCPUID for the first time). */
1042 RTCPUID idLastCpu;
1043 /** The CPU ID of the CPU currently owning the VMCS. Set in
1044 * HMR0Enter and cleared in HMR0Leave. */
1045 RTCPUID idEnteredCpu;
1046 /** Current ASID in use by the VM. */
1047 uint32_t uCurrentAsid;
1048
1049 /** Set if we need to flush the TLB during the world switch. */
1050 bool fForceTLBFlush;
1051 /** Whether we've completed the inner HM leave function. */
1052 bool fLeaveDone;
1053 /** Whether we're using the hyper DR7 or guest DR7. */
1054 bool fUsingHyperDR7;
1055 /** Whether we are currently executing in the debug loop.
1056 * Mainly for assertions. */
1057 bool fUsingDebugLoop;
1058 /** Set if we using the debug loop and wish to intercept RDTSC. */
1059 bool fDebugWantRdTscExit;
1060 /** Set if XCR0 needs to be saved/restored when entering/exiting guest code
1061 * execution. */
1062 bool fLoadSaveGuestXcr0;
1063 /** Set if we need to clear the trap flag because of single stepping. */
1064 bool fClearTrapFlag;
1065
1066 bool afPadding1[1];
1067 /** World switcher flags (HM_WSF_XXX - was CPUMCTX::fWorldSwitcher in 6.1). */
1068 uint32_t fWorldSwitcher;
1069 /** The raw host TSC value from the last VM exit (set by HMR0A.asm). */
1070 uint64_t uTscExit;
1071
1072 /** VT-x data. */
1073 struct HMR0CPUVMX
1074 {
1075 /** Ring-0 pointer to the hardware-assisted VMX execution function. */
1076 PFNHMVMXSTARTVM pfnStartVm;
1077 /** Absolute TSC deadline. */
1078 uint64_t uTscDeadline;
1079 /** The deadline version number. */
1080 uint64_t uTscDeadlineVersion;
1081
1082 /** @name Guest information.
1083 * @{ */
1084 /** Guest VMCS information. */
1085 VMXVMCSINFO VmcsInfo;
1086 /** Nested-guest VMCS information. */
1087 VMXVMCSINFO VmcsInfoNstGst;
1088 /* Whether the nested-guest VMCS was the last current VMCS (authoritative copy).
1089 * @see HMCPU::vmx.fSwitchedToNstGstVmcsCopyForRing3 */
1090 bool fSwitchedToNstGstVmcs;
1091 bool afAlignment0[7];
1092 /** Pointer to the VMX transient info during VM-exit. */
1093 PVMXTRANSIENT pVmxTransient;
1094 /** @} */
1095
1096 /** @name Host information.
1097 * @{ */
1098 /** Host LSTAR MSR to restore lazily while leaving VT-x. */
1099 uint64_t u64HostMsrLStar;
1100 /** Host STAR MSR to restore lazily while leaving VT-x. */
1101 uint64_t u64HostMsrStar;
1102 /** Host SF_MASK MSR to restore lazily while leaving VT-x. */
1103 uint64_t u64HostMsrSfMask;
1104 /** Host KernelGS-Base MSR to restore lazily while leaving VT-x. */
1105 uint64_t u64HostMsrKernelGsBase;
1106 /** The mask of lazy MSRs swap/restore state, see VMX_LAZY_MSRS_XXX. */
1107 uint32_t fLazyMsrs;
1108 /** Whether the host MSR values are up-to-date in the auto-load/store MSR area. */
1109 bool fUpdatedHostAutoMsrs;
1110 /** Alignment. */
1111 uint8_t au8Alignment0[3];
1112 /** Which host-state bits to restore before being preempted, see
1113 * VMX_RESTORE_HOST_XXX. */
1114 uint32_t fRestoreHostFlags;
1115 /** Alignment. */
1116 uint32_t u32Alignment0;
1117 /** The host-state restoration structure. */
1118 VMXRESTOREHOST RestoreHost;
1119 /** @} */
1120 } vmx;
1121
1122 /** SVM data. */
1123 struct HMR0CPUSVM
1124 {
1125 /** Ring 0 handlers for VT-x. */
1126 PFNHMSVMVMRUN pfnVMRun;
1127
1128 /** Physical address of the host VMCB which holds additional host-state. */
1129 RTHCPHYS HCPhysVmcbHost;
1130 /** R0 memory object for the host VMCB which holds additional host-state. */
1131 RTR0MEMOBJ hMemObjVmcbHost;
1132
1133 /** Physical address of the guest VMCB. */
1134 RTHCPHYS HCPhysVmcb;
1135 /** R0 memory object for the guest VMCB. */
1136 RTR0MEMOBJ hMemObjVmcb;
1137 /** Pointer to the guest VMCB. */
1138 R0PTRTYPE(PSVMVMCB) pVmcb;
1139
1140 /** Physical address of the MSR bitmap (8 KB). */
1141 RTHCPHYS HCPhysMsrBitmap;
1142 /** R0 memory object for the MSR bitmap (8 KB). */
1143 RTR0MEMOBJ hMemObjMsrBitmap;
1144 /** Pointer to the MSR bitmap. */
1145 R0PTRTYPE(void *) pvMsrBitmap;
1146
1147 /** Whether VTPR with V_INTR_MASKING set is in effect, indicating
1148 * we should check if the VTPR changed on every VM-exit. */
1149 bool fSyncVTpr;
1150 bool afAlignment[7];
1151
1152 /** Pointer to the SVM transient info during VM-exit. */
1153 PSVMTRANSIENT pSvmTransient;
1154 /** Host's TSC_AUX MSR (used when RDTSCP doesn't cause VM-exits). */
1155 uint64_t u64HostTscAux;
1156
1157 /** For saving stack space, the disassembler state is allocated here
1158 * instead of on the stack. */
1159 DISSTATE Dis;
1160 } svm;
1161} HMR0PERVCPU;
1162/** Pointer to HM ring-0 VMCPU instance data. */
1163typedef HMR0PERVCPU *PHMR0PERVCPU;
1164AssertCompileMemberAlignment(HMR0PERVCPU, cWorldSwitchExits, 4);
1165AssertCompileMemberAlignment(HMR0PERVCPU, fForceTLBFlush, 4);
1166AssertCompileMemberAlignment(HMR0PERVCPU, vmx.RestoreHost, 8);
1167
1168
1169/** @name HM_WSF_XXX - @bugref{9453}, @bugref{9087}
1170 * @note If you change these values don't forget to update the assembly
1171 * defines as well!
1172 * @{ */
1173/** Touch IA32_PRED_CMD.IBPB on VM exit. */
1174#define HM_WSF_IBPB_EXIT RT_BIT_32(0)
1175/** Touch IA32_PRED_CMD.IBPB on VM entry. */
1176#define HM_WSF_IBPB_ENTRY RT_BIT_32(1)
1177/** Touch IA32_FLUSH_CMD.L1D on VM entry. */
1178#define HM_WSF_L1D_ENTRY RT_BIT_32(2)
1179/** Flush MDS buffers on VM entry. */
1180#define HM_WSF_MDS_ENTRY RT_BIT_32(3)
1181
1182/** Touch IA32_FLUSH_CMD.L1D on VM scheduling. */
1183#define HM_WSF_L1D_SCHED RT_BIT_32(16)
1184/** Flush MDS buffers on VM scheduling. */
1185#define HM_WSF_MDS_SCHED RT_BIT_32(17)
1186/** @} */
1187
1188
1189#ifdef IN_RING0
1190extern bool g_fHmVmxSupported;
1191extern uint32_t g_fHmHostKernelFeatures;
1192extern uint32_t g_uHmMaxAsid;
1193extern bool g_fHmVmxUsePreemptTimer;
1194extern uint8_t g_cHmVmxPreemptTimerShift;
1195extern bool g_fHmVmxSupportsVmcsEfer;
1196extern uint64_t g_uHmVmxHostCr0;
1197extern uint64_t g_uHmVmxHostCr4;
1198extern uint64_t g_uHmVmxHostMsrEfer;
1199extern uint64_t g_uHmVmxHostSmmMonitorCtl;
1200extern uint64_t g_uHmVmxHostCoreCap;
1201extern uint64_t g_uHmVmxHostMemoryCtrl;
1202extern bool g_fHmSvmSupported;
1203extern uint32_t g_uHmSvmRev;
1204extern uint32_t g_fHmSvmFeatures;
1205
1206extern SUPHWVIRTMSRS g_HmMsrs;
1207
1208
1209VMMR0_INT_DECL(PHMPHYSCPU) hmR0GetCurrentCpu(void);
1210VMMR0_INT_DECL(int) hmR0EnterCpu(PVMCPUCC pVCpu);
1211
1212# ifdef VBOX_STRICT
1213# define HM_DUMP_REG_FLAGS_GPRS RT_BIT(0)
1214# define HM_DUMP_REG_FLAGS_FPU RT_BIT(1)
1215# define HM_DUMP_REG_FLAGS_MSRS RT_BIT(2)
1216# define HM_DUMP_REG_FLAGS_ALL (HM_DUMP_REG_FLAGS_GPRS | HM_DUMP_REG_FLAGS_FPU | HM_DUMP_REG_FLAGS_MSRS)
1217
1218VMMR0_INT_DECL(void) hmR0DumpRegs(PVMCPUCC pVCpu, uint32_t fFlags);
1219VMMR0_INT_DECL(void) hmR0DumpDescriptor(PCX86DESCHC pDesc, RTSEL Sel, const char *pszMsg);
1220# endif
1221
1222DECLASM(void) hmR0MdsClear(void);
1223#endif /* IN_RING0 */
1224
1225
1226/** @addtogroup grp_hm_int_svm SVM Internal
1227 * @{ */
1228VMM_INT_DECL(int) hmEmulateSvmMovTpr(PVMCC pVM, PVMCPUCC pVCpu);
1229
1230/**
1231 * Prepares for and executes VMRUN (64-bit register context).
1232 *
1233 * @returns VBox status code (no informational stuff).
1234 * @param pVM The cross context VM structure. (Not used.)
1235 * @param pVCpu The cross context virtual CPU structure.
1236 * @param HCPhyspVMCB Physical address of the VMCB.
1237 *
1238 * @remarks With spectre mitigations and the usual need for speed (/ micro
1239 * optimizations), we have a bunch of variations of this code depending
1240 * on a few precoditions. In release builds, the code is entirely
1241 * without conditionals. Debug builds have a couple of assertions that
1242 * shouldn't ever be triggered.
1243 *
1244 * @{
1245 */
1246DECLASM(int) hmR0SvmVmRun_SansXcr0_SansIbpbEntry_SansIbpbExit(PVMCC pVM, PVMCPUCC pVCpu, RTHCPHYS HCPhyspVMCB);
1247DECLASM(int) hmR0SvmVmRun_WithXcr0_SansIbpbEntry_SansIbpbExit(PVMCC pVM, PVMCPUCC pVCpu, RTHCPHYS HCPhyspVMCB);
1248DECLASM(int) hmR0SvmVmRun_SansXcr0_WithIbpbEntry_SansIbpbExit(PVMCC pVM, PVMCPUCC pVCpu, RTHCPHYS HCPhyspVMCB);
1249DECLASM(int) hmR0SvmVmRun_WithXcr0_WithIbpbEntry_SansIbpbExit(PVMCC pVM, PVMCPUCC pVCpu, RTHCPHYS HCPhyspVMCB);
1250DECLASM(int) hmR0SvmVmRun_SansXcr0_SansIbpbEntry_WithIbpbExit(PVMCC pVM, PVMCPUCC pVCpu, RTHCPHYS HCPhyspVMCB);
1251DECLASM(int) hmR0SvmVmRun_WithXcr0_SansIbpbEntry_WithIbpbExit(PVMCC pVM, PVMCPUCC pVCpu, RTHCPHYS HCPhyspVMCB);
1252DECLASM(int) hmR0SvmVmRun_SansXcr0_WithIbpbEntry_WithIbpbExit(PVMCC pVM, PVMCPUCC pVCpu, RTHCPHYS HCPhyspVMCB);
1253DECLASM(int) hmR0SvmVmRun_WithXcr0_WithIbpbEntry_WithIbpbExit(PVMCC pVM, PVMCPUCC pVCpu, RTHCPHYS HCPhyspVMCB);
1254/** @} */
1255
1256/** @} */
1257
1258
1259/** @addtogroup grp_hm_int_vmx VMX Internal
1260 * @{ */
1261VMM_INT_DECL(PVMXVMCSINFOSHARED) hmGetVmxActiveVmcsInfoShared(PVMCPUCC pVCpu);
1262
1263/**
1264 * Used on platforms with poor inline assembly support to retrieve all the
1265 * info from the CPU and put it in the @a pRestoreHost structure.
1266 */
1267DECLASM(void) hmR0VmxExportHostSegmentRegsAsmHlp(PVMXRESTOREHOST pRestoreHost, bool fHaveFsGsBase);
1268
1269/**
1270 * Restores some host-state fields that need not be done on every VM-exit.
1271 *
1272 * @returns VBox status code.
1273 * @param fRestoreHostFlags Flags of which host registers needs to be
1274 * restored.
1275 * @param pRestoreHost Pointer to the host-restore structure.
1276 */
1277DECLASM(int) VMXRestoreHostState(uint32_t fRestoreHostFlags, PVMXRESTOREHOST pRestoreHost);
1278
1279/**
1280 * VMX StartVM functions.
1281 *
1282 * @returns VBox status code (no informational stuff).
1283 * @param pVmcsInfo Pointer to the VMCS info (for cached host RIP and RSP).
1284 * @param pVCpu Pointer to the cross context per-CPU structure of the
1285 * calling EMT.
1286 * @param fResume Whether to use VMRESUME (true) or VMLAUNCH (false).
1287 *
1288 * @remarks With spectre mitigations and the usual need for speed (/ micro
1289 * optimizations), we have a bunch of variations of this code depending
1290 * on a few precoditions. In release builds, the code is entirely
1291 * without conditionals. Debug builds have a couple of assertions that
1292 * shouldn't ever be triggered.
1293 *
1294 * @{
1295 */
1296DECLASM(int) hmR0VmxStartVm_SansXcr0_SansIbpbEntry_SansL1dEntry_SansMdsEntry_SansIbpbExit(PVMXVMCSINFO pVmcsInfo, PVMCPUCC pVCpu, bool fResume);
1297DECLASM(int) hmR0VmxStartVm_WithXcr0_SansIbpbEntry_SansL1dEntry_SansMdsEntry_SansIbpbExit(PVMXVMCSINFO pVmcsInfo, PVMCPUCC pVCpu, bool fResume);
1298DECLASM(int) hmR0VmxStartVm_SansXcr0_WithIbpbEntry_SansL1dEntry_SansMdsEntry_SansIbpbExit(PVMXVMCSINFO pVmcsInfo, PVMCPUCC pVCpu, bool fResume);
1299DECLASM(int) hmR0VmxStartVm_WithXcr0_WithIbpbEntry_SansL1dEntry_SansMdsEntry_SansIbpbExit(PVMXVMCSINFO pVmcsInfo, PVMCPUCC pVCpu, bool fResume);
1300DECLASM(int) hmR0VmxStartVm_SansXcr0_SansIbpbEntry_WithL1dEntry_SansMdsEntry_SansIbpbExit(PVMXVMCSINFO pVmcsInfo, PVMCPUCC pVCpu, bool fResume);
1301DECLASM(int) hmR0VmxStartVm_WithXcr0_SansIbpbEntry_WithL1dEntry_SansMdsEntry_SansIbpbExit(PVMXVMCSINFO pVmcsInfo, PVMCPUCC pVCpu, bool fResume);
1302DECLASM(int) hmR0VmxStartVm_SansXcr0_WithIbpbEntry_WithL1dEntry_SansMdsEntry_SansIbpbExit(PVMXVMCSINFO pVmcsInfo, PVMCPUCC pVCpu, bool fResume);
1303DECLASM(int) hmR0VmxStartVm_WithXcr0_WithIbpbEntry_WithL1dEntry_SansMdsEntry_SansIbpbExit(PVMXVMCSINFO pVmcsInfo, PVMCPUCC pVCpu, bool fResume);
1304DECLASM(int) hmR0VmxStartVm_SansXcr0_SansIbpbEntry_SansL1dEntry_WithMdsEntry_SansIbpbExit(PVMXVMCSINFO pVmcsInfo, PVMCPUCC pVCpu, bool fResume);
1305DECLASM(int) hmR0VmxStartVm_WithXcr0_SansIbpbEntry_SansL1dEntry_WithMdsEntry_SansIbpbExit(PVMXVMCSINFO pVmcsInfo, PVMCPUCC pVCpu, bool fResume);
1306DECLASM(int) hmR0VmxStartVm_SansXcr0_WithIbpbEntry_SansL1dEntry_WithMdsEntry_SansIbpbExit(PVMXVMCSINFO pVmcsInfo, PVMCPUCC pVCpu, bool fResume);
1307DECLASM(int) hmR0VmxStartVm_WithXcr0_WithIbpbEntry_SansL1dEntry_WithMdsEntry_SansIbpbExit(PVMXVMCSINFO pVmcsInfo, PVMCPUCC pVCpu, bool fResume);
1308DECLASM(int) hmR0VmxStartVm_SansXcr0_SansIbpbEntry_WithL1dEntry_WithMdsEntry_SansIbpbExit(PVMXVMCSINFO pVmcsInfo, PVMCPUCC pVCpu, bool fResume);
1309DECLASM(int) hmR0VmxStartVm_WithXcr0_SansIbpbEntry_WithL1dEntry_WithMdsEntry_SansIbpbExit(PVMXVMCSINFO pVmcsInfo, PVMCPUCC pVCpu, bool fResume);
1310DECLASM(int) hmR0VmxStartVm_SansXcr0_WithIbpbEntry_WithL1dEntry_WithMdsEntry_SansIbpbExit(PVMXVMCSINFO pVmcsInfo, PVMCPUCC pVCpu, bool fResume);
1311DECLASM(int) hmR0VmxStartVm_WithXcr0_WithIbpbEntry_WithL1dEntry_WithMdsEntry_SansIbpbExit(PVMXVMCSINFO pVmcsInfo, PVMCPUCC pVCpu, bool fResume);
1312DECLASM(int) hmR0VmxStartVm_SansXcr0_SansIbpbEntry_SansL1dEntry_SansMdsEntry_WithIbpbExit(PVMXVMCSINFO pVmcsInfo, PVMCPUCC pVCpu, bool fResume);
1313DECLASM(int) hmR0VmxStartVm_WithXcr0_SansIbpbEntry_SansL1dEntry_SansMdsEntry_WithIbpbExit(PVMXVMCSINFO pVmcsInfo, PVMCPUCC pVCpu, bool fResume);
1314DECLASM(int) hmR0VmxStartVm_SansXcr0_WithIbpbEntry_SansL1dEntry_SansMdsEntry_WithIbpbExit(PVMXVMCSINFO pVmcsInfo, PVMCPUCC pVCpu, bool fResume);
1315DECLASM(int) hmR0VmxStartVm_WithXcr0_WithIbpbEntry_SansL1dEntry_SansMdsEntry_WithIbpbExit(PVMXVMCSINFO pVmcsInfo, PVMCPUCC pVCpu, bool fResume);
1316DECLASM(int) hmR0VmxStartVm_SansXcr0_SansIbpbEntry_WithL1dEntry_SansMdsEntry_WithIbpbExit(PVMXVMCSINFO pVmcsInfo, PVMCPUCC pVCpu, bool fResume);
1317DECLASM(int) hmR0VmxStartVm_WithXcr0_SansIbpbEntry_WithL1dEntry_SansMdsEntry_WithIbpbExit(PVMXVMCSINFO pVmcsInfo, PVMCPUCC pVCpu, bool fResume);
1318DECLASM(int) hmR0VmxStartVm_SansXcr0_WithIbpbEntry_WithL1dEntry_SansMdsEntry_WithIbpbExit(PVMXVMCSINFO pVmcsInfo, PVMCPUCC pVCpu, bool fResume);
1319DECLASM(int) hmR0VmxStartVm_WithXcr0_WithIbpbEntry_WithL1dEntry_SansMdsEntry_WithIbpbExit(PVMXVMCSINFO pVmcsInfo, PVMCPUCC pVCpu, bool fResume);
1320DECLASM(int) hmR0VmxStartVm_SansXcr0_SansIbpbEntry_SansL1dEntry_WithMdsEntry_WithIbpbExit(PVMXVMCSINFO pVmcsInfo, PVMCPUCC pVCpu, bool fResume);
1321DECLASM(int) hmR0VmxStartVm_WithXcr0_SansIbpbEntry_SansL1dEntry_WithMdsEntry_WithIbpbExit(PVMXVMCSINFO pVmcsInfo, PVMCPUCC pVCpu, bool fResume);
1322DECLASM(int) hmR0VmxStartVm_SansXcr0_WithIbpbEntry_SansL1dEntry_WithMdsEntry_WithIbpbExit(PVMXVMCSINFO pVmcsInfo, PVMCPUCC pVCpu, bool fResume);
1323DECLASM(int) hmR0VmxStartVm_WithXcr0_WithIbpbEntry_SansL1dEntry_WithMdsEntry_WithIbpbExit(PVMXVMCSINFO pVmcsInfo, PVMCPUCC pVCpu, bool fResume);
1324DECLASM(int) hmR0VmxStartVm_SansXcr0_SansIbpbEntry_WithL1dEntry_WithMdsEntry_WithIbpbExit(PVMXVMCSINFO pVmcsInfo, PVMCPUCC pVCpu, bool fResume);
1325DECLASM(int) hmR0VmxStartVm_WithXcr0_SansIbpbEntry_WithL1dEntry_WithMdsEntry_WithIbpbExit(PVMXVMCSINFO pVmcsInfo, PVMCPUCC pVCpu, bool fResume);
1326DECLASM(int) hmR0VmxStartVm_SansXcr0_WithIbpbEntry_WithL1dEntry_WithMdsEntry_WithIbpbExit(PVMXVMCSINFO pVmcsInfo, PVMCPUCC pVCpu, bool fResume);
1327DECLASM(int) hmR0VmxStartVm_WithXcr0_WithIbpbEntry_WithL1dEntry_WithMdsEntry_WithIbpbExit(PVMXVMCSINFO pVmcsInfo, PVMCPUCC pVCpu, bool fResume);
1328/** @} */
1329
1330/** @} */
1331
1332/** @} */
1333
1334RT_C_DECLS_END
1335
1336#endif /* !VMM_INCLUDED_SRC_include_HMInternal_h */
1337
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